From 1064d12c6d080b808f2132ba275c28204baa7a3e Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Thu, 27 Feb 2025 15:50:15 +0800 Subject: [PATCH] phy: rockchip: mipi csi2 dphy fixes error of clk0 enable enable too early may lead to mipi csi2 overflow Change-Id: Ib4d1f59803b8dcfdea8ba219fe8dc9667db35428 Signed-off-by: Zefa Chen --- .../phy/rockchip/phy-rockchip-csi2-dphy-hw.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c b/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c index 00a49fd45c07..db265f27bcd3 100644 --- a/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c +++ b/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c @@ -879,10 +879,13 @@ static int csi2_dphy_hw_stream_on(struct csi2_dphy *dphy, write_csi2_dphy_reg_mask(hw, CSI2PHY_CLK_CONTINUE_MODE, 0x30, CSI2PHY_CLK_CONTINUE_MODE_MASK); } else { - if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT))) + if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT)) && + hw->drv_data->chip_id < CHIP_ID_RK3588) val |= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT); if (dphy->phy_index % 3 == DPHY1) { + if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT))) + val |= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT); val |= (GENMASK(sensor->lanes - 1, 0) << CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT); if (!(sensor->mbus.bus.mipi_csi2.flags & @@ -1054,12 +1057,15 @@ static int csi2_dphy_hw_quick_stream_on(struct csi2_dphy *dphy, CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) | (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT); } else { - if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT))) + if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT)) && + hw->drv_data->chip_id < CHIP_ID_RK3588) val |= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT); - if (dphy->phy_index % 3 == DPHY1) + if (dphy->phy_index % 3 == DPHY1) { val |= (GENMASK(sensor->lanes - 1, 0) << CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT); + val |= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT); + } if (dphy->phy_index % 3 == DPHY2) { val |= (GENMASK(sensor->lanes - 1, 0) << @@ -1093,12 +1099,15 @@ static int csi2_dphy_hw_quick_stream_off(struct csi2_dphy *dphy, CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) | (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT); } else { - if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT))) + if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT)) && + hw->drv_data->chip_id < CHIP_ID_RK3588) val |= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT); - if (dphy->phy_index % 3 == DPHY1) + if (dphy->phy_index % 3 == DPHY1) { val |= (GENMASK(sensor->lanes - 1, 0) << CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT); + val |= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT); + } if (dphy->phy_index % 3 == DPHY2) { val |= (GENMASK(sensor->lanes - 1, 0) <<