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vlock: for support double frq out [1/1]

Browse Source 
PD#SWPL-12698

Problem:
Add feature for support input 25Hz, 30Hz

Solution:
Add feature for support input 25Hz, 30Hz

Verify:
tl1

Change-Id: I753547078e26b77edd6e69f452afcd9d49a17063
Signed-off-by: Yong Qin <yong.qin@amlogic.com>
This commit is contained in:
Yong Qin
2019-08-19 16:29:49 +08:00
committed by Tao Zeng
parent d73d13eacf
commit 109fb2b673
10 changed files with 81 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/amlogic/tl1_t962x2_t309.dts
View File

@@ -505,7 +505,7 @@
};
amlvecm {
compatible = "amlogic, vecm";
compatible = "amlogic, vecm-tl1";
dev_name = "aml_vecm";
status = "okay";
gamma_en = <1>;/*1:enabel ;0:disable*/

2
arch/arm/boot/dts/amlogic/tm2_t962x3_ab301.dts
View File

@@ -510,7 +510,7 @@
};
amlvecm {
compatible = "amlogic, vecm-tl1";
compatible = "amlogic, vecm-tm2";
dev_name = "aml_vecm";
status = "okay";
gamma_en = <1>;/*1:enabel ;0:disable*/

2
arch/arm/boot/dts/amlogic/tm2_t962x3_t312.dts
View File

@@ -516,7 +516,7 @@
};
amlvecm {
compatible = "amlogic, vecm-tl1";
compatible = "amlogic, vecm-tm2";
dev_name = "aml_vecm";
status = "okay";
gamma_en = <1>;/*1:enabel ;0:disable*/

2
arch/arm64/boot/dts/amlogic/tl1_t962x2_t309.dts
View File

@@ -503,7 +503,7 @@
};
amlvecm {
compatible = "amlogic, vecm";
compatible = "amlogic, vecm-tl1";
dev_name = "aml_vecm";
status = "okay";
gamma_en = <1>;/*1:enabel ;0:disable*/

2
arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g.dts
View File

@@ -520,7 +520,7 @@
};
amlvecm {
compatible = "amlogic, vecm";
compatible = "amlogic, vecm-tl1";
dev_name = "aml_vecm";
status = "okay";
gamma_en = <1>;/*1:enabel ;0:disable*/

2
arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g.dts
View File

@@ -514,7 +514,7 @@
};
amlvecm {
compatible = "amlogic, vecm";
compatible = "amlogic, vecm-tl1";
dev_name = "aml_vecm";
status = "okay";
gamma_en = <1>;/*1:enabel ;0:disable*/

2
arch/arm64/boot/dts/amlogic/tm2_t962x3_ab301.dts
View File

@@ -508,7 +508,7 @@
};
amlvecm {
compatible = "amlogic, vecm";
compatible = "amlogic, vecm-tm2";
dev_name = "aml_vecm";
status = "okay";
gamma_en = <1>;/*1:enabel ;0:disable*/

8
drivers/amlogic/media/enhancement/amvecm/amvecm.c
View File

@@ -6799,7 +6799,7 @@ static const struct vecm_match_data_s vecm_dt_tl1 = {
};
static const struct vecm_match_data_s vecm_dt_sm1 = {
.vlk_support = true,
.vlk_support = false,
.vlk_new_fsm = 1,
.vlk_hwver = vlock_hw_ver2,
.vlk_phlock_en = false,
@@ -6807,7 +6807,7 @@ static const struct vecm_match_data_s vecm_dt_sm1 = {
};
static const struct vecm_match_data_s vecm_dt_tm2 = {
.vlk_support = true,
.vlk_support = false,
.vlk_new_fsm = 1,
.vlk_hwver = vlock_hw_ver2,
.vlk_phlock_en = false,
@@ -6823,6 +6823,10 @@ static const struct of_device_id aml_vecm_dt_match[] = {
.compatible = "amlogic, vecm-tl1",
.data = &vecm_dt_tl1,
},
{
.compatible = "amlogic, vecm-sm1",
.data = &vecm_dt_sm1,
},
{
.compatible = "amlogic, vecm-tm2",
.data = &vecm_dt_tm2,

91
drivers/amlogic/media/enhancement/amvecm/vlock.c
View File

@@ -484,9 +484,15 @@ static void vlock_setting(struct vframe_s *vf,
WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
1, 28, 1);
} else {
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1))
WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
1, 28, 1);
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
if ((input_hz > 0) && (output_hz > 0) &&
(input_hz * 2 == output_hz))
WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
0, 28, 1);
else
WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
1, 28, 1);
}
}
freq_hz = input_hz | (output_hz << 8);
WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL, freq_hz, 0, 16);
@@ -494,9 +500,14 @@ static void vlock_setting(struct vframe_s *vf,
*Ifrm_cnt_mod:0x3001(bit23~16);
*(output_freq/input_freq)*Ifrm_cnt_mod must be integer
*/
if (vlock_adapt == 0)
WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL, 1, 16, 8);
else
if (vlock_adapt == 0) {
if ((output_hz > 0) && (input_hz > 0))
WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
output_hz / input_hz, 16, 8);
else
WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
1, 16, 8);
} else
WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
input_hz, 16, 8);
temp_value = READ_VPP_REG(enc_max_line_addr);
@@ -539,9 +550,15 @@ static void vlock_setting(struct vframe_s *vf,
WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
1, 28, 1);
} else {
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1))
WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
1, 28, 1);
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
if ((input_hz > 0) && (output_hz > 0) &&
(input_hz * 2 == output_hz))
WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
0, 28, 1);
else
WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
1, 28, 1);
}
}
freq_hz = input_hz | (output_hz << 8);
WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL, freq_hz, 0, 16);
@@ -550,7 +567,12 @@ static void vlock_setting(struct vframe_s *vf,
*(output_freq/input_freq)*Ifrm_cnt_mod must be integer
*/
if (vlock_adapt == 0)
WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL, 1, 16, 8);
if ((output_hz > 0) && (input_hz > 0))
WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
output_hz / input_hz, 16, 8);
else
WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
1, 16, 8);
else
WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
input_hz, 16, 8);
@@ -1070,6 +1092,10 @@ static void vlock_enable_step3_soft_enc(void)
return;
}
ia = (READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST) + last_i_vsync + 1) / 2;
/*for 25Hz->50Hz, 30Hz->60Hz*/
if (READ_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL, 16, 8) == 2)
ia = ia / 2;
oa = READ_VPP_REG(VPU_VLOCK_RO_VS_O_DIST);
if ((ia == 0) || (oa == 0)) {
@@ -1280,7 +1306,12 @@ static void vlock_enable_step3_pll(void)
ia = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST) / 2;
else
ia = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST);
/*for 25Hz->50Hz, 30Hz->60Hz*/
if (READ_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL, 16, 8) == 2)
ia = ia / 2;
oa = READ_VPP_REG(VPU_VLOCK_RO_VS_O_DIST);
abs_cnt = abs(ia - oa);
if (abs_cnt > (oa / 3)) {
if (vlock_debug & VLOCK_DEBUG_INFO)
@@ -1730,8 +1761,7 @@ void vlock_dt_match_init(struct vecm_match_data_s *pdata)
void vlock_set_phase(u32 percent)
{
u32 vs_i_val = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST);
/*u32 vs_o_val = READ_VPP_REG(VPU_VLOCK_RO_VS_O_DIST);*/
u32 ia = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST);
u32 data = 0;
if (!vlock.phlock_en)
@@ -1743,7 +1773,7 @@ void vlock_set_phase(u32 percent)
}
vlock.phlock_percent = percent;
data = (vs_i_val * (100 + vlock.phlock_percent))/200;
data = (ia * (100 + vlock.phlock_percent)) / 200;
WRITE_VPP_REG(VPU_VLOCK_LOOP1_PHSDIF_TGT, data);
vlock_reset(1);
@@ -1784,16 +1814,13 @@ void vlock_phaselock_check(struct stvlock_sig_sts *pvlock,
{
/*vs_i*/
u32 ia = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST);
u32 oa = READ_VPP_REG(VPU_VLOCK_RO_VS_O_DIST);
u32 val, pre;
if (vlock.phlock_en) {
if ((pvlock->frame_cnt_in % 20) == 0) {
/*ia = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST);*/
ia = (ia + oa) / 2;
pre = READ_VPP_REG(VPU_VLOCK_LOOP1_PHSDIF_TGT);
val = (ia * (100 + vlock.phlock_percent))/200;
if (val != pre) {
if (abs(val - pre) > 5) {
WRITE_VPP_REG(VPU_VLOCK_LOOP1_PHSDIF_TGT, val);
vlock_reset(1);
vlock_reset(0);
@@ -1875,18 +1902,29 @@ u32 vlock_fsm_check_support(struct stvlock_sig_sts *pvlock,
struct vframe_s *vf, struct vinfo_s *vinfo)
{
u32 ret = true;
u32 vs_support = false;
if (((pvlock->input_hz != pvlock->output_hz) && (vlock_adapt == 0)) ||
(pvlock->input_hz == 0) || (pvlock->output_hz == 0) ||
/* ex:30Hz->30Hz 50Hz->50Hz ...*/
if ((pvlock->input_hz > 0) &&
(pvlock->input_hz == pvlock->output_hz))
vs_support = true;
/* ex:30Hz->60Hz 25Hz->50Hz */
if ((pvlock->input_hz > 0) &&
(pvlock->input_hz * 2 == pvlock->output_hz))
vs_support = true;
if ((!vs_support && (vlock_adapt == 0)) ||
(pvlock->input_hz == 0) || (pvlock->output_hz == 0) ||
(((vf->type_original & VIDTYPE_TYPEMASK)
!= VIDTYPE_PROGRESSIVE) &&
is_meson_txlx_package_962E())) {
if (vlock_debug & VLOCK_DEBUG_INFO) {
pr_info("[%s] for no support case!!!\n",
__func__);
pr_info("input_hz:%d, output_hz:%d\n",
pvlock->input_hz, pvlock->output_hz);
pr_info("[%s] for no support case!!! vf:0x%x\n",
__func__, vf->type_original);
pr_info("vs_sup:%d input_hz:%d, output_hz:%d\n",
vs_support, pvlock->input_hz,
pvlock->output_hz);
pr_info("type_original:0x%x\n", vf->type_original);
}
ret = false;
@@ -1899,8 +1937,12 @@ u32 vlock_fsm_check_support(struct stvlock_sig_sts *pvlock,
ret = false;
}
if (vinfo->fr_adj_type == VOUT_FR_ADJ_NONE)
if (vinfo->fr_adj_type == VOUT_FR_ADJ_NONE) {
if (vlock_debug & VLOCK_DEBUG_INFO)
pr_info("[%s] for adj_type VOUT_FR_ADJ_NONE!!!\n",
__func__);
ret = false;
}
return ret;
}
@@ -2584,6 +2626,7 @@ void vlock_param_config(struct device_node *node)
vlock_line_limit = val;
#ifdef CONFIG_AMLOGIC_LCD
/* lock vlock config data from LCD module */
schedule_work(&aml_lcd_vlock_param_work);
#endif

2
drivers/amlogic/media/enhancement/amvecm/vlock.h
View File

@@ -23,7 +23,7 @@
#include <linux/amlogic/media/vfm/vframe.h>
#include "linux/amlogic/media/amvecm/ve.h"
#define VLOCK_VER "Ref.2019/7/29:FR_ADJ_NONE not support vlock"
#define VLOCK_VER "Ref.2019/8/18:vlock for double frq out"
#define VLOCK_REG_NUM 33