From 10d25e24d5946c815e014bd9061ecf7e1ed59bfe Mon Sep 17 00:00:00 2001
From: Sugar Zhang <sugar.zhang@rock-chips.com>
Date: Tue, 12 Nov 2024 17:57:52 +0800
Subject: [PATCH] ASoC: rockchip: sai: Simplify the Fsync Lost Threshold

Simplify the lost threshold config per sample rate.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ic032a91ae7c3727f299fdab17acbabe879e57b1d
---
 sound/soc/rockchip/rockchip_sai.c | 37 ++++++++++++++++++++++---------
 sound/soc/rockchip/rockchip_sai.h |  1 +
 2 files changed, 27 insertions(+), 11 deletions(-)

diff --git a/sound/soc/rockchip/rockchip_sai.c b/sound/soc/rockchip/rockchip_sai.c
index cbc720f5f9ab..febc94ed1592 100644
--- a/sound/soc/rockchip/rockchip_sai.c
+++ b/sound/soc/rockchip/rockchip_sai.c
@@ -106,29 +106,42 @@ static bool rockchip_sai_stream_valid(struct snd_pcm_substream *substream,
 	return false;
 }
 
-static int rockchip_sai_fsync_lost_detect(struct rk_sai_dev *sai, bool en)
+static int rockchip_sai_fsync_lost_threshold_cfg(struct rk_sai_dev *sai,
+						 unsigned int sample_rate)
 {
-	unsigned int fw, cnt;
+	unsigned int div, cnt, mclk_rate;
 
 	if (sai->is_master_mode || sai->version < SAI_VER_2311)
 		return 0;
 
-	regmap_read(sai->regmap, SAI_FSCR, &fw);
-	cnt = SAI_FSCR_FW_V(fw) << 1; /* two fsync lost */
+	regmap_read(sai->regmap, SAI_CKR, &div);
+	div = SAI_CKR_MDIV_V(div);
+	mclk_rate = clk_get_rate(sai->mclk) / div;
+
+	cnt = (mclk_rate + sample_rate - 1) / sample_rate;
+	cnt = cnt << 1; /* two fsync lost */
+
+	/* the cnt is cycles of SCLK from cru, not external SCLK */
+	regmap_update_bits(sai->regmap, SAI_FS_TIMEOUT,
+			   SAI_FS_TIMEOUT_VAL_MASK,
+			   SAI_FS_TIMEOUT_VAL(cnt));
+
+	return 0;
+}
+
+static int rockchip_sai_fsync_lost_detect(struct rk_sai_dev *sai, bool en)
+{
+	if (sai->is_master_mode || sai->version < SAI_VER_2311)
+		return 0;
 
 	regmap_update_bits(sai->regmap, SAI_INTCR,
 			   SAI_INTCR_FSLOSTC, SAI_INTCR_FSLOSTC);
 	regmap_update_bits(sai->regmap, SAI_INTCR,
 			   SAI_INTCR_FSLOST_MASK,
 			   SAI_INTCR_FSLOST(en));
-	/*
-	 * the cnt is cycles of SCLK from cru, not external SCLK.
-	 * so, suggest to set SCLK freq equal to external SCLK
-	 * in SLAVE mode.
-	 */
 	regmap_update_bits(sai->regmap, SAI_FS_TIMEOUT,
-			   SAI_FS_TIMEOUT_VAL_MASK | SAI_FS_TIMEOUT_EN_MASK,
-			   SAI_FS_TIMEOUT_VAL(cnt) | SAI_FS_TIMEOUT_EN(en));
+			   SAI_FS_TIMEOUT_EN_MASK,
+			   SAI_FS_TIMEOUT_EN(en));
 
 	return 0;
 }
@@ -641,6 +654,8 @@ static int rockchip_sai_hw_params(struct snd_pcm_substream *substream,
 				   SAI_CKR_MDIV(div_bclk));
 	}
 
+	rockchip_sai_fsync_lost_threshold_cfg(sai, params_rate(params));
+
 	rockchip_utils_get_performance(substream, params, dai, fifo);
 
 	return 0;
diff --git a/sound/soc/rockchip/rockchip_sai.h b/sound/soc/rockchip/rockchip_sai.h
index 00320aced846..a94d840f66cd 100644
--- a/sound/soc/rockchip/rockchip_sai.h
+++ b/sound/soc/rockchip/rockchip_sai.h
@@ -95,6 +95,7 @@
 /* CKR Clock Generation Register */
 #define SAI_CKR_MDIV_MASK		GENMASK(14, 3)
 #define SAI_CKR_MDIV(x)			((x - 1) << 3)
+#define SAI_CKR_MDIV_V(v)		((((v) & SAI_CKR_MDIV_MASK) >> 3) + 1)
 #define SAI_CKR_MSS_MASK		BIT(2)
 #define SAI_CKR_MSS_SLAVE		BIT(2)
 #define SAI_CKR_MSS_MASTER		0