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drm/rockchip: vop3: add support rk3528
Signed-off-by: Sandy Huang <hjc@rock-chips.com> Change-Id: Iaea5ccff625c0bc8d0cfe0d81a90b193c26c06b1
This commit is contained in:
Sandy Huang
@@ -26,6 +26,7 @@
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#define VOP2_MINOR(version) (((version) >> 16) & 0xff)
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#define VOP2_BUILD(version) ((version) & 0xffff)
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#define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263)
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#define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023)
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#define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786)
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@@ -3705,6 +3705,13 @@ static void vop2_initial(struct drm_crtc *crtc)
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if (is_vop3(vop2))
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VOP_CTRL_SET(vop2, esmart_lb_mode, vop2->data->esmart_lb_mode);
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/*
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* This is unused and error init value for rk3528 vp1, if less of this config,
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* vp1 can't display normally.
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*/
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if (vop2->version == VOP_VERSION_RK3528)
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vop2_mask_write(vop2, 0x700, 0x3, 4, 0, 0, true);
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VOP_CTRL_SET(vop2, cfg_done_en, 1);
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/*
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* Disable auto gating, this is a workaround to
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@@ -49,6 +49,36 @@ static const uint32_t formats_for_cluster[] = {
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DRM_FORMAT_Y210, /* yuv422_10bit non-Linear mode only */
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};
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static const uint32_t formats_for_vop3_cluster[] = {
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DRM_FORMAT_XRGB2101010,
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DRM_FORMAT_ARGB2101010,
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DRM_FORMAT_XBGR2101010,
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DRM_FORMAT_ABGR2101010,
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_XBGR8888,
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DRM_FORMAT_ABGR8888,
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DRM_FORMAT_RGB888,
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DRM_FORMAT_BGR888,
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DRM_FORMAT_RGB565,
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DRM_FORMAT_BGR565,
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DRM_FORMAT_NV12, /* yuv420_8bit linear mode, 2 plane */
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DRM_FORMAT_NV21, /* yvu420_8bit linear mode, 2 plane */
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DRM_FORMAT_NV16, /* yuv422_8bit linear mode, 2 plane */
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DRM_FORMAT_NV61, /* yvu422_8bit linear mode, 2 plane */
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DRM_FORMAT_NV24, /* yuv444_8bit linear mode, 2 plane */
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DRM_FORMAT_NV42, /* yvu444_8bit linear mode, 2 plane */
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DRM_FORMAT_NV15, /* yuv420_10bit linear mode, 2 plane, no padding */
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#ifdef CONFIG_NO_GKI
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DRM_FORMAT_NV20, /* yuv422_10bit linear mode, 2 plane, no padding */
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DRM_FORMAT_NV30, /* yuv444_10bit linear mode, 2 plane, no padding */
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#endif
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DRM_FORMAT_YUV420_8BIT, /* yuv420_8bit non-Linear mode only */
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DRM_FORMAT_YUV420_10BIT, /* yuv420_10bit non-Linear mode only */
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DRM_FORMAT_YUYV, /* yuv422_8bit non-Linear mode only*/
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DRM_FORMAT_Y210, /* yuv422_10bit non-Linear mode only */
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};
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static const uint32_t formats_for_esmart[] = {
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_ARGB8888,
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@@ -196,6 +226,49 @@ static const uint64_t format_modifiers_afbc_no_linear_mode[] = {
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DRM_FORMAT_MOD_INVALID,
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};
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static const uint64_t format_modifiers_afbc_tiled[] = {
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DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16),
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DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
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AFBC_FORMAT_MOD_SPARSE),
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DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
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AFBC_FORMAT_MOD_YTR),
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DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
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AFBC_FORMAT_MOD_CBR),
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DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
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AFBC_FORMAT_MOD_YTR |
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AFBC_FORMAT_MOD_SPARSE),
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DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
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AFBC_FORMAT_MOD_CBR |
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AFBC_FORMAT_MOD_SPARSE),
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DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
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AFBC_FORMAT_MOD_YTR |
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AFBC_FORMAT_MOD_CBR),
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DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
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AFBC_FORMAT_MOD_YTR |
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AFBC_FORMAT_MOD_CBR |
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AFBC_FORMAT_MOD_SPARSE),
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/* SPLIT mandates SPARSE, RGB modes mandates YTR */
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DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
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AFBC_FORMAT_MOD_YTR |
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AFBC_FORMAT_MOD_SPARSE |
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AFBC_FORMAT_MOD_SPLIT),
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DRM_FORMAT_MOD_ROCKCHIP_TILED(ROCKCHIP_TILED_BLOCK_SIZE_8x8),
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DRM_FORMAT_MOD_ROCKCHIP_TILED(ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0),
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DRM_FORMAT_MOD_ROCKCHIP_TILED(ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE1),
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DRM_FORMAT_MOD_LINEAR,
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DRM_FORMAT_MOD_INVALID,
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};
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static const u32 sdr2hdr_bt1886eotf_yn_for_hlg_hdr[65] = {
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0,
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1, 7, 17, 35,
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@@ -437,6 +510,16 @@ static const int rk3568_vop_axi_intrs[] = {
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};
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static const struct vop_intr rk3528_vop_axi_intr[] = {
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{
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.intrs = rk3568_vop_axi_intrs,
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.nintrs = ARRAY_SIZE(rk3568_vop_axi_intrs),
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.status = VOP_REG(RK3568_SYS0_INT_STATUS, 0xfe, 0),
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.enable = VOP_REG_MASK(RK3568_SYS0_INT_EN, 0xfe, 0),
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.clear = VOP_REG_MASK(RK3568_SYS0_INT_CLR, 0xfe, 0),
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},
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};
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static const struct vop_intr rk3568_vop_axi_intr[] = {
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{
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.intrs = rk3568_vop_axi_intrs,
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@@ -688,6 +771,144 @@ static const struct vop2_wb_data rk3568_vop_wb_data = {
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.regs = &rk3568_vop_wb_regs,
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};
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static const struct vop2_video_port_regs rk3528_vop_vp0_regs = {
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.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0),
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.overlay_mode = VOP_REG(RK3528_OVL_PORT0_CTRL, 0x1, 0),
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.dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0xffffffff, 0),
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.out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0),
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.dclk_div2 = VOP_REG(RK3568_VP0_CLK_CTRL, 0x1, 4),
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.p2i_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 5),
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.dsp_filed_pol = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 6),
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.dsp_interlace = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 7),
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.dsp_data_swap = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1f, 8),
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.post_dsp_out_r2y = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 15),
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.pre_dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 16),
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.dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17),
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.dither_down_sel = VOP_REG(RK3568_VP0_DSP_CTRL, 0x3, 18),
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.dither_down_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 20),
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.gamma_update_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 22),
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.dsp_lut_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 28),
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.standby = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31),
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.bg_mix_ctrl = VOP_REG(RK3528_OVL_PORT0_BG_MIX_CTRL, 0xffff, 0),
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.bg_dly = VOP_REG(RK3528_OVL_PORT0_BG_MIX_CTRL, 0xff, 24),
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.pre_scan_htiming = VOP_REG(RK3568_VP0_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
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.hpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
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.vpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
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.post_scl_factor = VOP_REG(RK3568_VP0_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
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.post_scl_ctrl = VOP_REG(RK3568_VP0_POST_SCL_CTRL, 0x3, 0),
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.htotal_pw = VOP_REG(RK3568_VP0_DSP_HTOTAL_HS_END, 0xffffffff, 0),
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.hact_st_end = VOP_REG(RK3568_VP0_DSP_HACT_ST_END, 0xffffffff, 0),
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.dsp_vtotal = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 16),
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.sw_dsp_vtotal_imd = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1, 15),
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.dsp_vs_end = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 0),
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.vact_st_end = VOP_REG(RK3568_VP0_DSP_VACT_ST_END, 0x1fff1fff, 0),
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.vact_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
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.vs_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
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.vpost_st_end_f1 = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
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.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
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.layer_sel = VOP_REG(RK3528_OVL_PORT0_LAYER_SEL, 0xffff, 0),
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.hdr_src_color_ctrl = VOP_REG(RK3528_HDR_SRC_COLOR_CTRL, 0xffffffff, 0),
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.hdr_dst_color_ctrl = VOP_REG(RK3528_HDR_DST_COLOR_CTRL, 0xffffffff, 0),
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.hdr_src_alpha_ctrl = VOP_REG(RK3528_HDR_SRC_ALPHA_CTRL, 0xffffffff, 0),
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.hdr_dst_alpha_ctrl = VOP_REG(RK3528_HDR_DST_ALPHA_CTRL, 0xffffffff, 0),
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};
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static const struct vop2_video_port_regs rk3528_vop_vp1_regs = {
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.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 1),
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.overlay_mode = VOP_REG(RK3528_OVL_PORT1_CTRL, 0x1, 0),
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.dsp_background = VOP_REG(RK3568_VP1_DSP_BG, 0xffffffff, 0),
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.out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0),
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.core_dclk_div = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 4),
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.p2i_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 5),
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.dsp_filed_pol = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 6),
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.dsp_interlace = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 7),
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.dsp_data_swap = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1f, 8),
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.post_dsp_out_r2y = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 15),
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.pre_dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 16),
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.dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17),
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.dither_down_sel = VOP_REG(RK3568_VP1_DSP_CTRL, 0x3, 18),
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.dither_down_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 20),
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.gamma_update_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 22),
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.dsp_lut_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 28),
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.standby = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31),
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.bg_mix_ctrl = VOP_REG(RK3528_OVL_PORT1_BG_MIX_CTRL, 0xffff, 0),
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.bg_dly = VOP_REG(RK3528_OVL_PORT1_BG_MIX_CTRL, 0xff, 24),
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.pre_scan_htiming = VOP_REG(RK3568_VP1_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
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.hpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
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.vpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
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.post_scl_factor = VOP_REG(RK3568_VP1_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
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.post_scl_ctrl = VOP_REG(RK3568_VP1_POST_SCL_CTRL, 0x3, 0),
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.htotal_pw = VOP_REG(RK3568_VP1_DSP_HTOTAL_HS_END, 0xffffffff, 0),
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.hact_st_end = VOP_REG(RK3568_VP1_DSP_HACT_ST_END, 0xffffffff, 0),
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.dsp_vtotal = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 16),
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.sw_dsp_vtotal_imd = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1, 15),
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.dsp_vs_end = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 0),
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.vact_st_end = VOP_REG(RK3568_VP1_DSP_VACT_ST_END, 0x1fff1fff, 0),
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.vact_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
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.vs_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
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.vpost_st_end_f1 = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
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.bcsh_brightness = VOP_REG(RK3568_VP1_BCSH_BCS, 0xff, 0),
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.bcsh_contrast = VOP_REG(RK3568_VP1_BCSH_BCS, 0x1ff, 8),
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.bcsh_sat_con = VOP_REG(RK3568_VP1_BCSH_BCS, 0x3ff, 20),
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.bcsh_out_mode = VOP_REG(RK3568_VP1_BCSH_BCS, 0x3, 30),
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.bcsh_sin_hue = VOP_REG(RK3568_VP1_BCSH_H, 0x1ff, 0),
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.bcsh_cos_hue = VOP_REG(RK3568_VP1_BCSH_H, 0x1ff, 16),
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.bcsh_r2y_csc_mode = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x3, 6),
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.bcsh_r2y_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 4),
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.bcsh_y2r_csc_mode = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x3, 2),
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.bcsh_y2r_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 0),
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.bcsh_en = VOP_REG(RK3568_VP1_BCSH_COLOR_BAR, 0x1, 31),
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.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
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.layer_sel = VOP_REG(RK3528_OVL_PORT1_LAYER_SEL, 0xffff, 0),
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};
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static const struct vop3_ovl_mix_regs rk3528_vop_vp0_layer_mix_regs = {
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.src_color_ctrl = VOP_REG(RK3528_OVL_PORT0_MIX0_SRC_COLOR_CTRL, 0xffffffff, 0),
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.dst_color_ctrl = VOP_REG(RK3528_OVL_PORT0_MIX0_DST_COLOR_CTRL, 0xffffffff, 0),
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.src_alpha_ctrl = VOP_REG(RK3528_OVL_PORT0_MIX0_SRC_ALPHA_CTRL, 0xffffffff, 0),
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.dst_alpha_ctrl = VOP_REG(RK3528_OVL_PORT0_MIX0_DST_ALPHA_CTRL, 0xffffffff, 0),
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};
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static const struct vop3_ovl_mix_regs rk3528_vop_vp1_layer_mix_regs = {
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.src_color_ctrl = VOP_REG(RK3528_OVL_PORT1_MIX0_SRC_COLOR_CTRL, 0xffffffff, 0),
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.dst_color_ctrl = VOP_REG(RK3528_OVL_PORT1_MIX0_DST_COLOR_CTRL, 0xffffffff, 0),
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.src_alpha_ctrl = VOP_REG(RK3528_OVL_PORT1_MIX0_SRC_ALPHA_CTRL, 0xffffffff, 0),
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.dst_alpha_ctrl = VOP_REG(RK3528_OVL_PORT1_MIX0_DST_ALPHA_CTRL, 0xffffffff, 0),
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};
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static const struct vop3_ovl_regs rk3528_vop_vp0_ovl_regs = {
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.layer_mix_regs = &rk3528_vop_vp0_layer_mix_regs,
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};
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static const struct vop3_ovl_regs rk3528_vop_vp1_ovl_regs = {
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.layer_mix_regs = &rk3528_vop_vp1_layer_mix_regs,
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};
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static const struct vop2_video_port_data rk3528_vop_video_ports[] = {
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{
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.id = 0,
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.soc_id = { 0x3528, 0x3528 },
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.lut_dma_rid = 14,
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.feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
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.gamma_lut_len = 1024,
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.max_output = { 4096, 4096 },
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.pre_scan_max_dly = { 43, 53, 53, 42 },
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.intr = &rk3568_vp0_intr,
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.regs = &rk3528_vop_vp0_regs,
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.ovl_regs = &rk3528_vop_vp0_ovl_regs,
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},
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{
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.id = 1,
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.soc_id = { 0x3528, 0x3528 },
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.feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
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.max_output = { 720, 576 },
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.pre_scan_max_dly = { 37, 40, 40, 40 },
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.intr = &rk3568_vp1_intr,
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.regs = &rk3528_vop_vp1_regs,
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.ovl_regs = &rk3528_vop_vp1_ovl_regs,
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},
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};
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static const struct vop2_video_port_regs rk3568_vop_vp0_regs = {
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.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0),
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.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 0),
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@@ -1465,6 +1686,16 @@ static const struct vop2_layer_data rk3568_vop_layers[] = {
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};
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static const struct vop2_cluster_regs rk3528_vop_cluster0 = {
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.afbc_enable = VOP_REG(RK3568_CLUSTER0_CTRL, 0x1, 1),
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.enable = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 0),
|
||||
.lb_mode = VOP_REG(RK3568_CLUSTER0_CTRL, 0xf, 4),
|
||||
.src_color_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
|
||||
.dst_color_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
|
||||
.src_alpha_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
|
||||
.dst_alpha_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
|
||||
};
|
||||
|
||||
static const struct vop2_cluster_regs rk3568_vop_cluster0 = {
|
||||
.afbc_enable = VOP_REG(RK3568_CLUSTER0_CTRL, 0x1, 1),
|
||||
.enable = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 0),
|
||||
@@ -1525,6 +1756,24 @@ static const struct vop_afbc rk3568_cluster0_afbc = {
|
||||
.ymirror = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE, 0x1, 3),
|
||||
};
|
||||
|
||||
static const struct vop2_scl_regs rk3528_cluster0_win_scl = {
|
||||
.scale_yrgb_x = VOP_REG(RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
|
||||
.scale_yrgb_y = VOP_REG(RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
|
||||
.yrgb_ver_scl_mode = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL1, 0x3, 14),
|
||||
.yrgb_hor_scl_mode = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL1, 0x3, 22),
|
||||
|
||||
.vsd_yrgb_gt2 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 28),
|
||||
.vsd_yrgb_gt4 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 29),
|
||||
.vsd_cbcr_gt2 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 30),
|
||||
.vsd_cbcr_gt4 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 31),
|
||||
|
||||
.vsd_avg2 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 18),/* supported from vop3 */
|
||||
.vsd_avg4 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 19),
|
||||
.xavg_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 27),
|
||||
.xgt_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 24),
|
||||
.xgt_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x3, 25),
|
||||
};
|
||||
|
||||
static const struct vop2_scl_regs rk3568_cluster0_win_scl = {
|
||||
.scale_yrgb_x = VOP_REG(RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
|
||||
.scale_yrgb_y = VOP_REG(RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
|
||||
@@ -1643,6 +1892,9 @@ static const struct vop2_scl_regs rk3568_esmart_win_scl = {
|
||||
.vsd_yrgb_gt4 = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 9),
|
||||
.vsd_cbcr_gt2 = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 10),
|
||||
.vsd_cbcr_gt4 = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 11),
|
||||
.xavg_en = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 20),/* supported from vop3 */
|
||||
.xgt_en = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 21),
|
||||
.xgt_mode = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x3, 22),
|
||||
};
|
||||
|
||||
static const struct vop2_scl_regs rk3568_area1_scl = {
|
||||
@@ -1756,6 +2008,31 @@ static const struct vop2_win_regs *rk3568_area_data[] = {
|
||||
&rk3568_area3_data
|
||||
};
|
||||
|
||||
static const struct vop2_win_regs rk3528_cluster0_win_data = {
|
||||
.scl = &rk3528_cluster0_win_scl,
|
||||
.afbc = &rk3568_cluster0_afbc,
|
||||
.cluster = &rk3528_vop_cluster0,
|
||||
.enable = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0),
|
||||
.format = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x3f, 1),
|
||||
.tile_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 7),
|
||||
.rb_swap = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 14),
|
||||
.uv_swap = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 17),
|
||||
.dither_up = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 18),
|
||||
.act_info = VOP_REG(RK3568_CLUSTER0_WIN0_ACT_INFO, 0x1fff1fff, 0),
|
||||
.dsp_info = VOP_REG(RK3568_CLUSTER0_WIN0_DSP_INFO, 0x0fff0fff, 0),
|
||||
.dsp_st = VOP_REG(RK3568_CLUSTER0_WIN0_DSP_ST, 0x1fff1fff, 0),
|
||||
.yrgb_mst = VOP_REG(RK3568_CLUSTER0_WIN0_YRGB_MST, 0xffffffff, 0),
|
||||
.uv_mst = VOP_REG(RK3568_CLUSTER0_WIN0_CBR_MST, 0xffffffff, 0),
|
||||
.yuv_clip = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 19),
|
||||
.yrgb_vir = VOP_REG(RK3568_CLUSTER0_WIN0_VIR, 0xffff, 0),
|
||||
.uv_vir = VOP_REG(RK3568_CLUSTER0_WIN0_VIR, 0xffff, 16),
|
||||
.y2r_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 8),
|
||||
.r2y_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 9),
|
||||
.csc_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x7, 10),
|
||||
.axi_yrgb_id = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL2, 0x1f, 0),
|
||||
.axi_uv_id = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL2, 0x1f, 5),
|
||||
};
|
||||
|
||||
static const struct vop2_win_regs rk3568_cluster0_win_data = {
|
||||
.scl = &rk3568_cluster0_win_scl,
|
||||
.afbc = &rk3568_cluster0_afbc,
|
||||
@@ -1866,9 +2143,208 @@ static const struct vop2_win_regs rk3568_esmart_win_data = {
|
||||
.y2r_en = VOP_REG(RK3568_ESMART0_CTRL0, 0x1, 0),
|
||||
.r2y_en = VOP_REG(RK3568_ESMART0_CTRL0, 0x1, 1),
|
||||
.csc_mode = VOP_REG(RK3568_ESMART0_CTRL0, 0x3, 2),
|
||||
.csc_13bit_en = VOP_REG(RK3568_ESMART0_CTRL0, 0x1, 16),
|
||||
.ymirror = VOP_REG(RK3568_ESMART0_CTRL1, 0x1, 31),
|
||||
.color_key = VOP_REG(RK3568_ESMART0_COLOR_KEY_CTRL, 0x3fffffff, 0),
|
||||
.color_key_en = VOP_REG(RK3568_ESMART0_COLOR_KEY_CTRL, 0x1, 31),
|
||||
.scale_engine_num = VOP_REG(RK3568_ESMART0_CTRL0, 0x3, 12),/* supported from vop3 */
|
||||
};
|
||||
|
||||
/*
|
||||
* RK3528 VOP with 1 Cluster win and 4 Esmart win.
|
||||
* Every Esmart win support 4 multi-region.
|
||||
* VP0 can use Cluster win and Esmart0/1/2
|
||||
* VP1 can use Esmart 2/3
|
||||
*
|
||||
* Scale filter mode:
|
||||
*
|
||||
* * Cluster:
|
||||
* * Support prescale down:
|
||||
* * H/V: gt2/avg2 or gt4/avg4
|
||||
* * After prescale down:
|
||||
* * nearest-neighbor/bilinear/bicubic for scale up
|
||||
* * nearest-neighbor/bilinear for scale down
|
||||
*
|
||||
* * Esmart:
|
||||
* * Support prescale down:
|
||||
* * H: gt2/avg2 or gt4/avg4
|
||||
* * V: gt2 or gt4
|
||||
* * After prescale down:
|
||||
* * nearest-neighbor/bilinear/bicubic for scale up
|
||||
* * nearest-neighbor/bilinear/average for scale down
|
||||
*/
|
||||
static const struct vop2_win_data rk3528_vop_win_data[] = {
|
||||
{
|
||||
.name = "Esmart0-win0",
|
||||
.phys_id = ROCKCHIP_VOP2_ESMART0,
|
||||
.formats = formats_for_esmart,
|
||||
.nformats = ARRAY_SIZE(formats_for_esmart),
|
||||
.format_modifiers = format_modifiers,
|
||||
.base = 0x0,
|
||||
.layer_sel_id = { 1, 0xff, 0xff, 0xff },
|
||||
.supported_rotations = DRM_MODE_REFLECT_Y,
|
||||
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
|
||||
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
|
||||
.vsu_filter_mode = VOP2_SCALE_UP_BIL,
|
||||
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
|
||||
.hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
|
||||
.vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT,/* gt only */
|
||||
.regs = &rk3568_esmart_win_data,
|
||||
.area = rk3568_area_data,
|
||||
.area_size = ARRAY_SIZE(rk3568_area_data),
|
||||
.type = DRM_PLANE_TYPE_PRIMARY,
|
||||
.axi_id = 0,
|
||||
.axi_yrgb_id = 0x06,
|
||||
.axi_uv_id = 0x07,
|
||||
.scale_engine_num = 0,
|
||||
.possible_crtcs = 0x1,/* vp0 only */
|
||||
.max_upscale_factor = 8,
|
||||
.max_downscale_factor = 8,
|
||||
.dly = { 27, 45, 48 },
|
||||
.feature = WIN_FEATURE_MULTI_AREA | WIN_FEATURE_Y2R_13BIT_DEPTH,
|
||||
},
|
||||
|
||||
{
|
||||
.name = "Esmart1-win0",
|
||||
.phys_id = ROCKCHIP_VOP2_ESMART1,
|
||||
.formats = formats_for_esmart,
|
||||
.nformats = ARRAY_SIZE(formats_for_esmart),
|
||||
.format_modifiers = format_modifiers,
|
||||
.base = 0x200,
|
||||
.layer_sel_id = { 2, 0xff, 0xff, 0xff },
|
||||
.supported_rotations = DRM_MODE_REFLECT_Y,
|
||||
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
|
||||
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
|
||||
.vsu_filter_mode = VOP2_SCALE_UP_BIL,
|
||||
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
|
||||
.hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
|
||||
.vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT,/* gt only */
|
||||
.regs = &rk3568_esmart_win_data,
|
||||
.area = rk3568_area_data,
|
||||
.area_size = ARRAY_SIZE(rk3568_area_data),
|
||||
.type = DRM_PLANE_TYPE_OVERLAY,
|
||||
.axi_id = 0,
|
||||
.axi_yrgb_id = 0x08,
|
||||
.axi_uv_id = 0x09,
|
||||
.scale_engine_num = 1,
|
||||
.possible_crtcs = 0x1,/* vp0 only */
|
||||
.max_upscale_factor = 8,
|
||||
.max_downscale_factor = 8,
|
||||
.dly = { 27, 45, 48 },
|
||||
.feature = WIN_FEATURE_MULTI_AREA,
|
||||
},
|
||||
|
||||
{
|
||||
.name = "Esmart2-win0",
|
||||
.phys_id = ROCKCHIP_VOP2_ESMART2,
|
||||
.base = 0x400,
|
||||
.formats = formats_for_esmart,
|
||||
.nformats = ARRAY_SIZE(formats_for_esmart),
|
||||
.format_modifiers = format_modifiers,
|
||||
.layer_sel_id = { 3, 0, 0xff, 0xff },
|
||||
.supported_rotations = DRM_MODE_REFLECT_Y,
|
||||
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
|
||||
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
|
||||
.vsu_filter_mode = VOP2_SCALE_UP_BIL,
|
||||
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
|
||||
.hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
|
||||
.vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT,/* gt only */
|
||||
.regs = &rk3568_esmart_win_data,
|
||||
.area = rk3568_area_data,
|
||||
.area_size = ARRAY_SIZE(rk3568_area_data),
|
||||
.type = DRM_PLANE_TYPE_OVERLAY,
|
||||
.axi_id = 0,
|
||||
.axi_yrgb_id = 0x0a,
|
||||
.axi_uv_id = 0x0b,
|
||||
.scale_engine_num = 2,
|
||||
.possible_crtcs = 0x3,/* vp0 or vp1 */
|
||||
.max_upscale_factor = 8,
|
||||
.max_downscale_factor = 8,
|
||||
.dly = { 27, 45, 48 },
|
||||
.feature = WIN_FEATURE_MULTI_AREA,
|
||||
},
|
||||
|
||||
{
|
||||
.name = "Esmart3-win0",
|
||||
.phys_id = ROCKCHIP_VOP2_ESMART3,
|
||||
.formats = formats_for_esmart,
|
||||
.nformats = ARRAY_SIZE(formats_for_esmart),
|
||||
.format_modifiers = format_modifiers,
|
||||
.base = 0x600,
|
||||
.layer_sel_id = { 0xff, 1, 0xff, 0xff },
|
||||
.supported_rotations = DRM_MODE_REFLECT_Y,
|
||||
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
|
||||
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
|
||||
.vsu_filter_mode = VOP2_SCALE_UP_BIL,
|
||||
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
|
||||
.hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
|
||||
.vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT,/* gt only */
|
||||
.regs = &rk3568_esmart_win_data,
|
||||
.area = rk3568_area_data,
|
||||
.area_size = ARRAY_SIZE(rk3568_area_data),
|
||||
.type = DRM_PLANE_TYPE_PRIMARY,
|
||||
.axi_id = 0,
|
||||
.axi_yrgb_id = 0x0c,
|
||||
.axi_uv_id = 0x0d,
|
||||
.scale_engine_num = 3,
|
||||
.possible_crtcs = 0x2,/* vp1 only */
|
||||
.max_upscale_factor = 8,
|
||||
.max_downscale_factor = 8,
|
||||
.dly = { 27, 45, 48 },
|
||||
.feature = WIN_FEATURE_MULTI_AREA,
|
||||
},
|
||||
|
||||
{
|
||||
.name = "Cluster0-win0",
|
||||
.phys_id = ROCKCHIP_VOP2_CLUSTER0,
|
||||
.base = 0x00,
|
||||
.formats = formats_for_vop3_cluster,
|
||||
.nformats = ARRAY_SIZE(formats_for_vop3_cluster),
|
||||
.format_modifiers = format_modifiers_afbc_tiled,
|
||||
.layer_sel_id = { 0, 0xff, 0xff, 0xff },
|
||||
.supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
|
||||
DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
|
||||
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
|
||||
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
|
||||
.vsu_filter_mode = VOP2_SCALE_UP_BIL,
|
||||
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
|
||||
.hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
|
||||
.vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
|
||||
.regs = &rk3528_cluster0_win_data,
|
||||
.axi_yrgb_id = 0x02,
|
||||
.axi_uv_id = 0x03,
|
||||
.possible_crtcs = 0x1,/* vp0 only */
|
||||
.max_upscale_factor = 8,
|
||||
.max_downscale_factor = 8,
|
||||
.dly = { 27, 27, 21 },
|
||||
.type = DRM_PLANE_TYPE_OVERLAY,
|
||||
.feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN | WIN_FEATURE_Y2R_13BIT_DEPTH,
|
||||
},
|
||||
|
||||
{
|
||||
.name = "Cluster0-win1",
|
||||
.phys_id = ROCKCHIP_VOP2_CLUSTER0,
|
||||
.base = 0x80,
|
||||
.layer_sel_id = { 0, 0xff, 0xff, 0xff },
|
||||
.formats = formats_for_cluster,
|
||||
.nformats = ARRAY_SIZE(formats_for_cluster),
|
||||
.format_modifiers = format_modifiers_afbc_tiled,
|
||||
.supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
|
||||
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
|
||||
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
|
||||
.vsu_filter_mode = VOP2_SCALE_UP_BIL,
|
||||
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
|
||||
.hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
|
||||
.vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
|
||||
.regs = &rk3528_cluster0_win_data,
|
||||
.axi_yrgb_id = 0x04,
|
||||
.axi_uv_id = 0x05,
|
||||
.possible_crtcs = 0x1,/* vp0 only */
|
||||
.max_upscale_factor = 8,
|
||||
.max_downscale_factor = 8,
|
||||
.type = DRM_PLANE_TYPE_OVERLAY,
|
||||
.feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -2604,6 +3080,36 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
|
||||
},
|
||||
};
|
||||
|
||||
static const struct vop2_ctrl rk3528_vop_ctrl = {
|
||||
.cfg_done_en = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 15),
|
||||
.wb_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 14),
|
||||
.auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 31),
|
||||
.aclk_pre_auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 7),
|
||||
.if_ctrl_cfg_done_imd = VOP_REG(RK3568_DSP_IF_POL, 0x1, 28),
|
||||
.version = VOP_REG(RK3568_VERSION_INFO, 0xffff, 16),
|
||||
.lut_dma_en = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1, 0),
|
||||
.rgb_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 0),
|
||||
.hdmi0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 1),
|
||||
.bt656_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 7),
|
||||
.rgb_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 8),
|
||||
.hdmi0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 10),
|
||||
.bt656_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 5),
|
||||
.bt656_dclk_pol = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 6),
|
||||
.hdmi_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 4),
|
||||
.hdmi_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 7),
|
||||
.esmart_lb_mode = VOP_REG(RK3568_LUT_PORT_SEL, 0x3, 26),
|
||||
.win_vp_id[ROCKCHIP_VOP2_CLUSTER0] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 0),
|
||||
.win_vp_id[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 16),
|
||||
.win_vp_id[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 20),
|
||||
.win_vp_id[ROCKCHIP_VOP2_ESMART2] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 24),
|
||||
.win_vp_id[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 28),
|
||||
.win_dly[ROCKCHIP_VOP2_CLUSTER0] = VOP_REG(RK3528_OVL_SYS_CLUSTER0_CTRL, 0xffff, 0),
|
||||
.win_dly[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3528_OVL_SYS_ESMART0_CTRL, 0xff, 0),
|
||||
.win_dly[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3528_OVL_SYS_ESMART1_CTRL, 0xff, 0),
|
||||
.win_dly[ROCKCHIP_VOP2_ESMART2] = VOP_REG(RK3528_OVL_SYS_ESMART2_CTRL, 0xff, 0),
|
||||
.win_dly[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3528_OVL_SYS_ESMART3_CTRL, 0xff, 0),
|
||||
};
|
||||
|
||||
static const struct vop_grf_ctrl rk3568_sys_grf_ctrl = {
|
||||
.grf_bt656_clk_inv = VOP_REG(RK3568_GRF_VO_CON1, 0x1, 1),
|
||||
.grf_bt1120_clk_inv = VOP_REG(RK3568_GRF_VO_CON1, 0x1, 2),
|
||||
@@ -2769,6 +3275,19 @@ static const struct vop2_ctrl rk3588_vop_ctrl = {
|
||||
.win_dly[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 24),
|
||||
};
|
||||
|
||||
static const struct vop_dump_regs rk3528_dump_regs[] = {
|
||||
{ RK3568_REG_CFG_DONE, "SYS" },
|
||||
{ RK3528_OVL_SYS, "OVL_SYS" },
|
||||
{ RK3528_OVL_PORT0_CTRL, "OVL_VP0" },
|
||||
{ RK3528_OVL_PORT1_CTRL, "OVL_VP1" },
|
||||
{ RK3568_VP0_DSP_CTRL, "VP0" },
|
||||
{ RK3568_VP1_DSP_CTRL, "VP1" },
|
||||
{ RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0" },
|
||||
{ RK3568_ESMART0_CTRL0, "Esmart0" },
|
||||
{ RK3568_ESMART1_CTRL0, "Esmart1" },
|
||||
{ RK3568_SMART0_CTRL0, "Esmart2" },
|
||||
{ RK3568_SMART1_CTRL0, "Esmart3" },
|
||||
};
|
||||
|
||||
static const struct vop_dump_regs rk3568_dump_regs[] = {
|
||||
{ RK3568_REG_CFG_DONE, "SYS" },
|
||||
@@ -2803,6 +3322,27 @@ static const struct vop_dump_regs rk3588_dump_regs[] = {
|
||||
{ RK3568_HDR_LUT_CTRL, "HDR" },
|
||||
};
|
||||
|
||||
static const struct vop2_data rk3528_vop = {
|
||||
.version = VOP_VERSION_RK3528,
|
||||
.nr_vps = 2,
|
||||
.nr_mixers = 4,
|
||||
.nr_layers = 4,
|
||||
.nr_gammas = 1,
|
||||
.esmart_lb_mode = VOP3_ESMART_FOUR_2K_MODE,
|
||||
.max_input = { 4096, 2304 },
|
||||
.max_output = { 4096, 2304 },
|
||||
.ctrl = &rk3528_vop_ctrl,
|
||||
.axi_intr = rk3528_vop_axi_intr,
|
||||
.nr_axi_intr = ARRAY_SIZE(rk3528_vop_axi_intr),
|
||||
.vp = rk3528_vop_video_ports,
|
||||
.wb = &rk3568_vop_wb_data,
|
||||
.layer = rk3568_vop_layers,
|
||||
.win = rk3528_vop_win_data,
|
||||
.win_size = ARRAY_SIZE(rk3528_vop_win_data),
|
||||
.dump_regs = rk3528_dump_regs,
|
||||
.dump_regs_size = ARRAY_SIZE(rk3528_dump_regs),
|
||||
};
|
||||
|
||||
static const struct vop2_data rk3568_vop = {
|
||||
.version = VOP_VERSION_RK3568,
|
||||
.nr_vps = 3,
|
||||
@@ -2862,6 +3402,8 @@ static const struct vop2_data rk3588_vop = {
|
||||
};
|
||||
|
||||
static const struct of_device_id vop2_dt_match[] = {
|
||||
{ .compatible = "rockchip,rk3528-vop",
|
||||
.data = &rk3528_vop },
|
||||
{ .compatible = "rockchip,rk3568-vop",
|
||||
.data = &rk3568_vop },
|
||||
{ .compatible = "rockchip,rk3588-vop",
|
||||
|
||||
@@ -1208,6 +1208,52 @@
|
||||
#define RK3588_VP3_BCSH_BCS 0xF64
|
||||
#define RK3588_VP3_BCSH_H 0xF68
|
||||
#define RK3588_VP3_BCSH_COLOR_BAR 0xF6C
|
||||
#define RK3528_OVL_SYS 0x500
|
||||
#define RK3528_OVL_SYS_PORT_SEL_IMD 0x504
|
||||
#define RK3528_OVL_SYS_GATING_EN_IMD 0x508
|
||||
#define RK3528_OVL_SYS_CLUSTER0_CTRL 0x510
|
||||
#define RK3528_OVL_SYS_ESMART0_CTRL 0x520
|
||||
#define RK3528_OVL_SYS_ESMART1_CTRL 0x524
|
||||
#define RK3528_OVL_SYS_ESMART2_CTRL 0x528
|
||||
#define RK3528_OVL_SYS_ESMART3_CTRL 0x52C
|
||||
#define RK3528_CLUSTER0_MIX_SRC_COLOR_CTRL 0x530
|
||||
#define RK3528_CLUSTER0_MIX_DST_COLOR_CTRL 0x534
|
||||
#define RK3528_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x538
|
||||
#define RK3528_CLUSTER0_MIX_DST_ALPHA_CTRL 0x53c
|
||||
#define RK3528_OVL_PORT0_CTRL 0x600
|
||||
#define RK3528_OVL_PORT0_LAYER_SEL 0x604
|
||||
#define RK3528_OVL_PORT0_MIX0_SRC_COLOR_CTRL 0x620
|
||||
#define RK3528_OVL_PORT0_MIX0_DST_COLOR_CTRL 0x624
|
||||
#define RK3528_OVL_PORT0_MIX0_SRC_ALPHA_CTRL 0x628
|
||||
#define RK3528_OVL_PORT0_MIX0_DST_ALPHA_CTRL 0x62C
|
||||
#define RK3528_OVL_PORT0_MIX1_SRC_COLOR_CTRL 0x630
|
||||
#define RK3528_OVL_PORT0_MIX1_DST_COLOR_CTRL 0x634
|
||||
#define RK3528_OVL_PORT0_MIX1_SRC_ALPHA_CTRL 0x638
|
||||
#define RK3528_OVL_PORT0_MIX1_DST_ALPHA_CTRL 0x63C
|
||||
#define RK3528_OVL_PORT0_MIX2_SRC_COLOR_CTRL 0x640
|
||||
#define RK3528_OVL_PORT0_MIX2_DST_COLOR_CTRL 0x644
|
||||
#define RK3528_OVL_PORT0_MIX2_SRC_ALPHA_CTRL 0x648
|
||||
#define RK3528_OVL_PORT0_MIX2_DST_ALPHA_CTRL 0x64C
|
||||
#define RK3528_HDR_SRC_COLOR_CTRL 0x660
|
||||
#define RK3528_HDR_DST_COLOR_CTRL 0x664
|
||||
#define RK3528_HDR_SRC_ALPHA_CTRL 0x668
|
||||
#define RK3528_HDR_DST_ALPHA_CTRL 0x66C
|
||||
#define RK3528_OVL_PORT0_BG_MIX_CTRL 0x670
|
||||
#define RK3528_OVL_PORT1_CTRL 0x700
|
||||
#define RK3528_OVL_PORT1_LAYER_SEL 0x704
|
||||
#define RK3528_OVL_PORT1_MIX0_SRC_COLOR_CTRL 0x720
|
||||
#define RK3528_OVL_PORT1_MIX0_DST_COLOR_CTRL 0x724
|
||||
#define RK3528_OVL_PORT1_MIX0_SRC_ALPHA_CTRL 0x728
|
||||
#define RK3528_OVL_PORT1_MIX0_DST_ALPHA_CTRL 0x72C
|
||||
#define RK3528_OVL_PORT1_MIX1_SRC_COLOR_CTRL 0x730
|
||||
#define RK3528_OVL_PORT1_MIX1_DST_COLOR_CTRL 0x734
|
||||
#define RK3528_OVL_PORT1_MIX1_SRC_ALPHA_CTRL 0x738
|
||||
#define RK3528_OVL_PORT1_MIX1_DST_ALPHA_CTRL 0x73C
|
||||
#define RK3528_OVL_PORT1_MIX2_SRC_COLOR_CTRL 0x740
|
||||
#define RK3528_OVL_PORT1_MIX2_DST_COLOR_CTRL 0x744
|
||||
#define RK3528_OVL_PORT1_MIX2_SRC_ALPHA_CTRL 0x748
|
||||
#define RK3528_OVL_PORT1_MIX2_DST_ALPHA_CTRL 0x74C
|
||||
#define RK3528_OVL_PORT1_BG_MIX_CTRL 0x770
|
||||
|
||||
/* Overlay registers definition */
|
||||
#define RK3568_OVL_CTRL 0x600
|
||||
@@ -1252,6 +1298,8 @@
|
||||
/* Cluster0 register definition */
|
||||
#define RK3568_CLUSTER0_WIN0_CTRL0 0x1000
|
||||
#define RK3568_CLUSTER0_WIN0_CTRL1 0x1004
|
||||
#define RK3528_CLUSTER0_WIN0_CTRL1 0x1004
|
||||
#define RK3528_CLUSTER0_WIN0_CTRL2 0x1008
|
||||
#define RK3568_CLUSTER0_WIN0_CTRL2 0x1008
|
||||
#define RK3568_CLUSTER0_WIN0_YRGB_MST 0x1010
|
||||
#define RK3568_CLUSTER0_WIN0_CBR_MST 0x1014
|
||||
@@ -1272,6 +1320,8 @@
|
||||
|
||||
#define RK3568_CLUSTER0_WIN1_CTRL0 0x1080
|
||||
#define RK3568_CLUSTER0_WIN1_CTRL1 0x1084
|
||||
#define RK3528_CLUSTER0_WIN1_CTRL1 0x1084
|
||||
#define RK3528_CLUSTER0_WIN1_CTRL2 0x1088
|
||||
#define RK3568_CLUSTER0_WIN1_YRGB_MST 0x1090
|
||||
#define RK3568_CLUSTER0_WIN1_CBR_MST 0x1094
|
||||
#define RK3568_CLUSTER0_WIN1_VIR 0x1098
|
||||
|
||||
Reference in New Issue
Block a user