From ca7627f2a44b6815b2f23f4da2d0fc996bd20424 Mon Sep 17 00:00:00 2001 From: Hisping Lin Date: Fri, 22 Dec 2023 09:52:47 +0800 Subject: [PATCH 01/22] tee: optee: interrupt an RPC depend on shutdown flag Fixes: e6c7ea7d4da7 ("tee: optee: interrupt an RPC when supplicant has been killed") Change-Id: I33f33af02afb75bda5d68c9731fe636bb97132fe Signed-off-by: Hisping Lin --- drivers/tee/optee/core.c | 8 ++++++++ drivers/tee/optee/optee_private.h | 1 + drivers/tee/optee/supp.c | 13 +++++-------- 3 files changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c index 6ea80add7378..6abf2acec14c 100644 --- a/drivers/tee/optee/core.c +++ b/drivers/tee/optee/core.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -624,6 +625,13 @@ static int optee_remove(struct platform_device *pdev) */ static void optee_shutdown(struct platform_device *pdev) { + struct optee *optee = platform_get_drvdata(pdev); + + /* Tell requesting thread to interrupt an RPC */ + smp_store_mb(optee->supp.shutdown, true); + /* Wait requesting thread to release resources */ + mdelay(200); + optee_disable_shm_cache(platform_get_drvdata(pdev)); } diff --git a/drivers/tee/optee/optee_private.h b/drivers/tee/optee/optee_private.h index ea09533e30cd..8af2c97c8c09 100644 --- a/drivers/tee/optee/optee_private.h +++ b/drivers/tee/optee/optee_private.h @@ -64,6 +64,7 @@ struct optee_supp { struct list_head reqs; struct idr idr; struct completion reqs_c; + bool shutdown; }; /** diff --git a/drivers/tee/optee/supp.c b/drivers/tee/optee/supp.c index 2d556b79a67e..a8656a72d83a 100644 --- a/drivers/tee/optee/supp.c +++ b/drivers/tee/optee/supp.c @@ -82,7 +82,6 @@ u32 optee_supp_thrd_req(struct tee_context *ctx, u32 func, size_t num_params, struct optee_supp_req *req; bool interruptable; u32 ret; - unsigned long timeleft; int id; struct optee_supp_req *get_req; @@ -117,14 +116,12 @@ u32 optee_supp_thrd_req(struct tee_context *ctx, u32 func, size_t num_params, * exclusive access again. */ while (wait_for_completion_interruptible(&req->c)) { - pr_err("Warning, Interrupting an RPC to supplicant!\n"); - timeleft = wait_for_completion_timeout(&req->c, msecs_to_jiffies(2000)); - if (timeleft) { - /* get completion, it means tee-supplicant is alive. */ - break; - } else { - /* timeout, it means tee-supplicant is dead, interrupting an RPC. */ + if (supp->shutdown) { + /* Reboot happen, tee-supplicant is dead, interrupt an RPC */ interruptable = true; + } else { + /* Deep sleep, tee-supplicant is freeze, wait tee-supplicant */ + continue; } mutex_lock(&supp->mutex); From 22999ca74381dc316acb7efbdefa60c76f8789a2 Mon Sep 17 00:00:00 2001 From: Dingxian Wen Date: Wed, 27 Dec 2023 18:15:32 +0800 Subject: [PATCH 02/22] media: rockchip: hdmirx: make sure to bind to big cpu1 Signed-off-by: Dingxian Wen Change-Id: I7f81e13e02911ff970c179a1a7def0f01417c0c3 --- .../platform/rockchip/hdmirx/rk_hdmirx.c | 25 +++++++++++++------ 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c b/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c index d3c54ba16e9f..7f67328fe557 100644 --- a/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c +++ b/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c @@ -81,6 +81,7 @@ MODULE_PARM_DESC(low_latency, "low_latency en(0-1)"); #define NO_LOCK_CFG_RETRY_TIME 300 #define WAIT_LOCK_STABLE_TIME 20 #define WAIT_AVI_PKT_TIME 300 +#define BIG_CPU_PHY_ID 5 #define is_validfs(x) (x == 32000 || \ x == 44100 || \ @@ -4589,9 +4590,9 @@ static int hdmirx_probe(struct platform_device *pdev) struct v4l2_device *v4l2_dev; struct v4l2_ctrl_handler *hdl; struct resource *res; - int ret, irq, cpu_aff; struct hdmirx_cec_data cec_data; struct cpumask cpumask; + int ret, irq, cpu_aff, phy_cpuid, i; hdmirx_dev = devm_kzalloc(dev, sizeof(*hdmirx_dev), GFP_KERNEL); if (!hdmirx_dev) @@ -4618,12 +4619,22 @@ static int hdmirx_probe(struct platform_device *pdev) * in order to quickly respond to FIQ and prevent them from affecting * each other. */ - if (sip_cpu_logical_map_mpidr(0) == 0) { - cpu_aff = sip_cpu_logical_map_mpidr(5); - hdmirx_dev->bound_cpu = 5; - } else { - cpu_aff = sip_cpu_logical_map_mpidr(1); - hdmirx_dev->bound_cpu = 1; + for (i = 0; i < 8; i++) { + cpu_aff = sip_cpu_logical_map_mpidr(i); + phy_cpuid = (cpu_aff >> 8) & 0xf; + if (phy_cpuid == BIG_CPU_PHY_ID) { + hdmirx_dev->bound_cpu = i; + hdmirx_dev->phy_cpuid = phy_cpuid; + break; + } + } + + if (!hdmirx_dev->phy_cpuid) { + dev_info(dev, "%s: Failed to get phy_cpuid, use default BIG_CPU_PHY_ID!\n", + __func__); + cpu_aff = BIG_CPU_PHY_ID << 8; + hdmirx_dev->bound_cpu = BIG_CPU_PHY_ID; + hdmirx_dev->phy_cpuid = BIG_CPU_PHY_ID; } sip_fiq_control(RK_SIP_FIQ_CTRL_SET_AFF, RK_IRQ_HDMIRX_HDMI, cpu_aff); From 920198cd6ccee5df18fcc24a67286ad44d5bea5e Mon Sep 17 00:00:00 2001 From: Lan Honglin Date: Fri, 15 Dec 2023 17:55:03 +0800 Subject: [PATCH 03/22] media: i2c: imx415 adapt sleep_wakeup Change-Id: Ie371b8dc92718e13d3abe97a8809e859e918e7a7 Signed-off-by: Lan Honglin --- drivers/media/i2c/imx415.c | 84 +++++++++++++++++++++++++++++++++----- 1 file changed, 74 insertions(+), 10 deletions(-) diff --git a/drivers/media/i2c/imx415.c b/drivers/media/i2c/imx415.c index 2cf6561e2222..6de1c2f3d925 100644 --- a/drivers/media/i2c/imx415.c +++ b/drivers/media/i2c/imx415.c @@ -53,6 +53,8 @@ #include #include #include "../platform/rockchip/isp/rkisp_tb_helper.h" +#include "cam-tb-setup.h" +#include "cam-sleep-wakeup.h" #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x08) @@ -242,6 +244,7 @@ struct imx415 { bool has_init_exp; struct preisp_hdrae_exp_s init_hdrae_exp; struct v4l2_fwnode_endpoint bus_cfg; + struct cam_sw_info *cam_sw_inf; }; static struct rkmodule_csi_dphy_param dcphy_param = { @@ -2435,11 +2438,6 @@ int __imx415_power_on(struct imx415 *imx415) } if (!imx415->is_thunderboot) { - ret = regulator_bulk_enable(IMX415_NUM_SUPPLIES, imx415->supplies); - if (ret < 0) { - dev_err(dev, "Failed to enable regulators\n"); - goto err_pinctrl; - } if (!IS_ERR(imx415->power_gpio)) gpiod_direction_output(imx415->power_gpio, 1); /* At least 500ns between power raising and XCLR */ @@ -2463,18 +2461,28 @@ int __imx415_power_on(struct imx415 *imx415) goto err_clk; } + cam_sw_regulator_bulk_init(imx415->cam_sw_inf, IMX415_NUM_SUPPLIES, imx415->supplies); + + if (imx415->is_thunderboot) + return 0; + /* At least 20us between XCLR and I2C communication */ - if (!imx415->is_thunderboot) - usleep_range(20*1000, 30*1000); + usleep_range(20*1000, 30*1000); + + ret = regulator_bulk_enable(IMX415_NUM_SUPPLIES, imx415->supplies); + if (ret < 0) { + dev_err(dev, "Failed to enable regulators\n"); + goto err_pinctrl; + } return 0; +err_pinctrl: + clk_disable_unprepare(imx415->xvclk); + err_clk: if (!IS_ERR(imx415->reset_gpio)) gpiod_direction_output(imx415->reset_gpio, 1); - regulator_bulk_disable(IMX415_NUM_SUPPLIES, imx415->supplies); - -err_pinctrl: if (!IS_ERR_OR_NULL(imx415->pins_sleep)) pinctrl_select_state(imx415->pinctrl, imx415->pins_sleep); @@ -2509,6 +2517,51 @@ static void __imx415_power_off(struct imx415 *imx415) regulator_bulk_disable(IMX415_NUM_SUPPLIES, imx415->supplies); } +#if IS_REACHABLE(CONFIG_VIDEO_CAM_SLEEP_WAKEUP) +static int __maybe_unused imx415_resume(struct device *dev) +{ + int ret; + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx415 *imx415 = to_imx415(sd); + + cam_sw_prepare_wakeup(imx415->cam_sw_inf, dev); + + usleep_range(4000, 5000); + cam_sw_write_array(imx415->cam_sw_inf); + + if (__v4l2_ctrl_handler_setup(&imx415->ctrl_handler)) + dev_err(dev, "__v4l2_ctrl_handler_setup fail!"); + + if (imx415->has_init_exp && imx415->cur_mode != NO_HDR) { // hdr mode + ret = imx415_ioctl(&imx415->subdev, PREISP_CMD_SET_HDRAE_EXP, + &imx415->cam_sw_inf->hdr_ae); + if (ret) { + dev_err(&imx415->client->dev, "set exp fail in hdr mode\n"); + return ret; + } + } + return 0; +} + +static int __maybe_unused imx415_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx415 *imx415 = to_imx415(sd); + + cam_sw_write_array_cb_init(imx415->cam_sw_inf, client, + (void *)imx415->cur_mode->reg_list, + (sensor_write_array)imx415_write_array); + cam_sw_prepare_sleep(imx415->cam_sw_inf); + + return 0; +} +#else +#define imx415_resume NULL +#define imx415_suspend NULL +#endif + static int __maybe_unused imx415_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); @@ -2614,6 +2667,7 @@ static int imx415_get_selection(struct v4l2_subdev *sd, static const struct dev_pm_ops imx415_pm_ops = { SET_RUNTIME_PM_OPS(imx415_runtime_suspend, imx415_runtime_resume, NULL) + SET_LATE_SYSTEM_SLEEP_PM_OPS(imx415_suspend, imx415_resume) }; #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API @@ -3027,6 +3081,14 @@ static int imx415_probe(struct i2c_client *client, goto err_power_off; #endif + if (!imx415->cam_sw_inf) { + imx415->cam_sw_inf = cam_sw_init(); + cam_sw_clk_init(imx415->cam_sw_inf, imx415->xvclk, imx415->cur_mode->xvclk); + cam_sw_reset_pin_init(imx415->cam_sw_inf, imx415->reset_gpio, 1); + if (!IS_ERR(imx415->power_gpio)) + cam_sw_pwdn_pin_init(imx415->cam_sw_inf, imx415->power_gpio, 0); + } + memset(facing, 0, sizeof(facing)); if (strcmp(imx415->module_facing, "back") == 0) facing[0] = 'b'; @@ -3074,6 +3136,8 @@ static int imx415_remove(struct i2c_client *client) v4l2_ctrl_handler_free(&imx415->ctrl_handler); mutex_destroy(&imx415->mutex); + cam_sw_deinit(imx415->cam_sw_inf); + pm_runtime_disable(&client->dev); if (!pm_runtime_status_suspended(&client->dev)) __imx415_power_off(imx415); From 5a0f616be97799fbabc4e295281a4e0dcdc6b769 Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Tue, 2 Jan 2024 19:16:55 +0800 Subject: [PATCH 04/22] drm/bridge: synopsys: Fixes compilation errors when cec core is not compiled Fix error: implicit declaration of function 'cec_queue_pin_hpd_event'. Fixes: 5fe797153df8 ("drm: bridge: dw-hdmi: Support report cec hpd") Change-Id: I4ddae31d5b72b17fdd33fbc28ca454dc57377f74 Signed-off-by: Algea Cao --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 5d20a72a186f..3ac72c2bcb2c 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -429,10 +429,12 @@ static void repo_hpd_event(struct work_struct *p_work) if (change) { if (hdmi->plat_data->set_ddc_io) hdmi->plat_data->set_ddc_io(data, hdmi->hpd_state); +#if IS_REACHABLE(CONFIG_DRM_DW_HDMI_CEC) if (hdmi->cec_adap->devnode.registered) cec_queue_pin_hpd_event(hdmi->cec_adap, hdmi->hpd_state, ktime_get()); +#endif } drm_bridge_hpd_notify(&hdmi->bridge, status); } From 5f2dd30238200a1fe3f549d1e663772807ff593a Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Tue, 2 Jan 2024 19:18:16 +0800 Subject: [PATCH 05/22] drm/bridge: dw-hdmi-qp: Fixes compilation errors when cec core is not compiled Fix error: implicit declaration of function 'cec_queue_pin_hpd_event'. Fixes: b73433e36e58 ("drm/rockchip: Add dw-hdmi-qp driver") Change-Id: I9268259d42dddd285b3bb8d92a55b7df9ae3c3c1 Signed-off-by: Algea Cao --- drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c index 906f0f628c2a..20bb1408aba7 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -3274,8 +3274,10 @@ void dw_hdmi_qp_cec_set_hpd(struct dw_hdmi_qp *hdmi, bool plug_in, bool change) CEC_PHYS_ADDR_INVALID); if (hdmi->bridge.dev) { +#if IS_REACHABLE(CONFIG_DRM_DW_HDMI_CEC) if (change && hdmi->cec_adap && hdmi->cec_adap->devnode.registered) cec_queue_pin_hpd_event(hdmi->cec_adap, plug_in, ktime_get()); +#endif drm_bridge_hpd_notify(&hdmi->bridge, status); } } From bf7e43d9fe0afc1e5b3bce16191dc51598818d47 Mon Sep 17 00:00:00 2001 From: David Wu Date: Fri, 25 Aug 2023 20:44:30 +0800 Subject: [PATCH 06/22] net: phy: RK630: Add dynamically adjusting the configuration Adjustments occur at two cases: - No linkup within 5s; - The number of packets received within 10 seconds is less than 3, or the packet loss rate is greater than 15%. Signed-off-by: David Wu Change-Id: I8b48bb4377ddb4231fa6f26b4373695fd85cbb26 --- drivers/net/phy/rk630phy.c | 394 +++++++++++++++++++++++++++++++++++-- 1 file changed, 381 insertions(+), 13 deletions(-) diff --git a/drivers/net/phy/rk630phy.c b/drivers/net/phy/rk630phy.c index de76196712cb..a4abd835c9e1 100644 --- a/drivers/net/phy/rk630phy.c +++ b/drivers/net/phy/rk630phy.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #define RK630_PHY_ID 0x00441400 @@ -71,6 +72,39 @@ #define T22_TX_LEVEL_100M 0x2d #define T22_TX_LEVEL_10M 0x32 +/* Long network cable parameters */ +#define RX_DETECT_SCHEDULE_TIME 500 /* ms */ +#define RX_DETECT_INIT_WAIT_TIME 2000 /* ms */ + +#define RX_DETECT_MAX_COUNT (5000 / RX_DETECT_SCHEDULE_TIME) +#define ALL_RX_DETECT_MAX_COUNT (2 * RX_DETECT_MAX_COUNT) + +#define LINKED_MAX_COUNT (10000 / RX_DETECT_SCHEDULE_TIME) +#define ALL_LINKED_MAX_COUNT (2 * LINKED_MAX_COUNT) + +#define RX_PACKET_RECEIVED_COUNTS 3 /* packets */ +#define RX_PACKET_RECEIVED_LOST 15 /* percent */ + +#define RX_SIGNAL_DETECT_TEMP 85000 + +struct rk630_phy_switched { + /* record state */ + bool config; + bool config_mode_10M; + bool finished; + + /* detected process */ + unsigned int detected_count; + bool config_rx_signal; + int old_link; + + /* linked process */ + unsigned int linked_count; + int rx_pkt_cnt; + int rx_crc_err_cnt; + int lost_percent; +}; + struct rk630_phy_priv { struct phy_device *phydev; bool ieee; @@ -78,6 +112,13 @@ struct rk630_phy_priv { struct wake_lock wol_wake_lock; int tx_level_100M; int tx_level_10M; + + struct rk630_phy_switched switched; + /* mutex protect variables between notify thread and delayed work */ + struct mutex lock; + struct delayed_work service_task; + struct thermal_zone_device *tz; + bool disable_switch; }; static void rk630_phy_t22_get_tx_level_from_efuse(struct phy_device *phydev) @@ -192,6 +233,17 @@ static void rk630_phy_set_uaps(struct phy_device *phydev, bool enable) phy_write(phydev, REG_PAGE_SEL, 0x0000); } +static bool rk630_phy_rx_signal_detected(struct phy_device *phydev) +{ + u32 value; + + /* Switch to page 0 */ + phy_write(phydev, REG_PAGE_SEL, 0x0000); + value = phy_read(phydev, 25); + + return (value & BIT(15)) ? false : true; +} + static void rk630_phy_s40_config_init(struct phy_device *phydev) { phy_write(phydev, 0, phy_read(phydev, 0) & ~BIT(13)); @@ -229,8 +281,8 @@ static void rk630_phy_t22_config_init(struct phy_device *phydev) phy_write(phydev, REG_PAGE_SEL, 0x0100); /* Enable offset clock */ phy_write(phydev, 0x10, 0xfbfe); - /* Disable APS */ - phy_write(phydev, REG_PAGE1_APS_CTRL, 0x4824); + /* Disable APS & Rx detected time 2s, default is 4s */ + phy_write(phydev, REG_PAGE1_APS_CTRL, 0x4822); /* Switch to page 2 */ phy_write(phydev, REG_PAGE_SEL, 0x0200); /* PHYAFE TRX optimization */ @@ -242,7 +294,15 @@ static void rk630_phy_t22_config_init(struct phy_device *phydev) /* PHYAFE Gain optimization */ phy_write(phydev, REG_PAGE6_GAIN_ANONTROL, 0x0400); /* PHYAFE EQ optimization */ - phy_write(phydev, REG_PAGE6_AFE_TX_CTRL, 0x1088); + + if (priv->disable_switch) { + /* Rx detected default threshold 160 mv */ + phy_write(phydev, REG_PAGE6_AFE_TX_CTRL, 0x1088); + } else { + /* Rx detected threshold 260 mv */ + phy_write(phydev, REG_PAGE6_AFE_TX_CTRL, 0x10c8); + priv->switched.config_rx_signal = true; + } if (priv->tx_level_100M <= 0 || priv->tx_level_10M <= 0) rk630_phy_t22_get_tx_level_from_efuse(phydev); @@ -305,23 +365,305 @@ static int rk630_phy_config_init(struct phy_device *phydev) return 0; } -static void rk630_link_change_notify(struct phy_device *phydev) +/* config0(default) and config1(0x555e) switched for 100/10M speed */ +static bool rk630_phy_switch_config(struct phy_device *phydev, bool config) { + struct rk630_phy_priv *priv = phydev->priv; + + if (priv->switched.config != config) { + int val; + + val = config ? 0x555e : 0x5540; + phy_write(priv->phydev, REG_PAGE_SEL, 0x0600); + phy_write(priv->phydev, REG_PAGE6_ADC_ANONTROL, val); + phy_write(priv->phydev, REG_PAGE_SEL, 0x0000); + priv->switched.config = config; + + return true; + } + + return false; +} + +/* 10M speed configuration */ +static void rk630_phy_10m_switch_config(struct phy_device *phydev, bool config) +{ + struct rk630_phy_priv *priv = phydev->priv; unsigned int val; - if (phydev->state == PHY_RUNNING || phydev->state == PHY_NOLINK) { - /* Switch to page 6 */ - phy_write(phydev, REG_PAGE_SEL, 0x0600); + if (config == priv->switched.config_mode_10M) + return; + + phy_write(phydev, REG_PAGE_SEL, 0x0600); + val = phy_read(phydev, REG_PAGE6_AFE_TX_CTRL); + val &= ~GENMASK(14, 13); + if (config && !priv->switched.config_mode_10M) + val |= BIT(13); + + priv->switched.config_mode_10M = config; + phy_write(phydev, REG_PAGE6_AFE_TX_CTRL, val); + phy_write(priv->phydev, REG_PAGE_SEL, 0x0000); +} + +static void rk630_phy_switch_rx_signal_config(struct phy_device *phydev, + bool config) +{ + struct rk630_phy_priv *priv = phydev->priv; + + if (priv->switched.config_rx_signal != config) { + int val; + + phy_write(priv->phydev, REG_PAGE_SEL, 0x0600); val = phy_read(phydev, REG_PAGE6_AFE_TX_CTRL); - val &= ~GENMASK(14, 13); - if (phydev->speed == SPEED_10 && phydev->link) - val |= BIT(13); + val &= ~GENMASK(7, 6); + if (config) + val |= GENMASK(7, 6); + else + val |= BIT(7); phy_write(phydev, REG_PAGE6_AFE_TX_CTRL, val); - /* Switch to page 0 */ - phy_write(phydev, REG_PAGE_SEL, 0x0000); + phy_write(priv->phydev, REG_PAGE_SEL, 0x0000); + + priv->switched.config_rx_signal = config; } } +static void rk630_phy_packet_statistics(struct phy_device *phydev, + int *total_cnt, int *crc_err_cnt) +{ + struct rk630_phy_priv *priv = phydev->priv; + + phy_write(priv->phydev, REG_PAGE_SEL, 0x0900); + *total_cnt = phy_read(priv->phydev, 0x1b) << 16; + *total_cnt |= phy_read(priv->phydev, 0x1c); + *crc_err_cnt = phy_read(priv->phydev, 0x1d) << 16; + *crc_err_cnt |= phy_read(priv->phydev, 0x1e); + phy_write(phydev, REG_PAGE_SEL, 0x0000); +} + +static bool rk630_phy_switch_config_by_packets(struct phy_device *phydev) +{ + struct rk630_phy_priv *priv = phydev->priv; + int rx_pkt_cnt, rx_crc_err_cnt; + int total_cnt, total_crc_err_cnt; + int lost_percent; + + rk630_phy_packet_statistics(phydev, &total_cnt, &total_crc_err_cnt); + + rx_pkt_cnt = total_cnt - priv->switched.rx_pkt_cnt; + rx_crc_err_cnt = total_crc_err_cnt - priv->switched.rx_crc_err_cnt; + + priv->switched.rx_pkt_cnt = total_cnt; + priv->switched.rx_crc_err_cnt = total_crc_err_cnt; + + /* less than the minimal received packets during some time */ + if (rx_pkt_cnt < RX_PACKET_RECEIVED_COUNTS) + return true; + + /* Percents packets lost is not good during some time */ + lost_percent = (rx_crc_err_cnt * 100 / rx_pkt_cnt) > RX_PACKET_RECEIVED_LOST; + + /* Just compare with config0's packet lost, update config if it is better + * than config0. + */ + if (((rx_crc_err_cnt * 100 / rx_pkt_cnt) > RX_PACKET_RECEIVED_LOST) && + lost_percent > priv->switched.lost_percent) { + /* Only save config0 lost percent */ + if (!priv->switched.config) + priv->switched.lost_percent = lost_percent; + return true; + } + + /* Only save config0 lost percent */ + if (!priv->switched.config) + priv->switched.lost_percent = lost_percent; + + return false; +} + +static void rk630_phy_service_task(struct work_struct *work) +{ + struct rk630_phy_priv *priv = container_of(work, struct rk630_phy_priv, + service_task.work); + unsigned int delay_time; + int ret, temp; + + mutex_lock(&priv->lock); + if (priv->disable_switch) { + mutex_unlock(&priv->lock); + return; + } + + if (!priv->phydev->link) { + bool signal_detected; + + signal_detected = rk630_phy_rx_signal_detected(priv->phydev); + + /* Read signal */ + if (!signal_detected) { + /* Slow schedule work for 2 * SCHEDULE_TIME, if no signal */ + priv->switched.detected_count = 0; + priv->switched.lost_percent = 0; + priv->switched.finished = false; + priv->switched.linked_count = 0; + delay_time = 2 * RX_DETECT_SCHEDULE_TIME; + /* Goto default config if no rj45 signal plugin */ + rk630_phy_switch_config(priv->phydev, false); + + /* Also go to 10M default config */ + rk630_phy_10m_switch_config(priv->phydev, false); + } else { + priv->switched.detected_count++; + /* Fast schedule work for 1 * SCHEDULE_TIME, if signal + * detected. + */ + delay_time = RX_DETECT_SCHEDULE_TIME; + if (priv->switched.detected_count == RX_DETECT_MAX_COUNT && + !priv->switched.finished) { + /* After it, there is no link, Might be a long cable, + * config1 switched to get better performance during + * some time. + */ + rk630_phy_switch_config(priv->phydev, true); + } else if (priv->switched.detected_count == ALL_RX_DETECT_MAX_COUNT && + !priv->switched.finished) { + /* After another detect, we lost the last chance, + * go back to default config0. + */ + rk630_phy_switch_config(priv->phydev, false); + priv->switched.finished = true; + } else if (priv->switched.detected_count > ALL_RX_DETECT_MAX_COUNT || + priv->switched.finished) { + /* Slow schedule work for 2 * SCHEDULE_TIME, if + * detected finish. + */ + delay_time = 2 * RX_DETECT_SCHEDULE_TIME; + } + } + } else { + /* Detect the packet count and crc error count statistics */ + priv->switched.linked_count++; + /* Fast schedule work for 1 * SCHEDULE_TIME, if linkup detected */ + delay_time = RX_DETECT_SCHEDULE_TIME; + if (priv->switched.linked_count == LINKED_MAX_COUNT && + !priv->switched.finished) { + if (rk630_phy_switch_config_by_packets(priv->phydev)) { + /* Config1 switched to get better performance */ + rk630_phy_switch_config(priv->phydev, true); + + /* Also go to 10M default config */ + if (priv->switched.config && priv->phydev->speed == SPEED_10) + rk630_phy_10m_switch_config(priv->phydev, true); + } + } else if (priv->switched.linked_count == ALL_LINKED_MAX_COUNT && + !priv->switched.finished) { + /* If config switched, we lost the last chance, return to + * default config0. + */ + if (rk630_phy_switch_config_by_packets(priv->phydev)) { + rk630_phy_switch_config(priv->phydev, false); + rk630_phy_10m_switch_config(priv->phydev, false); + } + priv->switched.finished = true; + } else if (priv->switched.linked_count > ALL_LINKED_MAX_COUNT || + priv->switched.finished) { + /* Slow schedule work for 2 * SCHEDULE_TIME, if linkup + * detected finish. + */ + delay_time = 2 * RX_DETECT_SCHEDULE_TIME; + } + } + + if (priv->tz) { + ret = thermal_zone_get_temp(priv->tz, &temp); + if (ret || temp == THERMAL_TEMP_INVALID) + phydev_err(priv->phydev, + "failed to read out thermal zone (%d)\n", ret); + else + rk630_phy_switch_rx_signal_config(priv->phydev, + (temp > RX_SIGNAL_DETECT_TEMP) ? false : true); + } + + schedule_delayed_work(&priv->service_task, msecs_to_jiffies(delay_time)); + mutex_unlock(&priv->lock); +} + +static void rk630_phy_link_change_notify(struct phy_device *phydev) +{ + struct rk630_phy_priv *priv = phydev->priv; + + if (phydev->mdio.addr == PHY_ADDR_T22) { + mutex_lock(&priv->lock); + if (priv->disable_switch) { + mutex_unlock(&priv->lock); + return; + } + + if (priv->switched.old_link && !phydev->link) { + priv->switched.old_link = 0; + priv->switched.linked_count = 0; + schedule_delayed_work(&priv->service_task, + msecs_to_jiffies(RX_DETECT_SCHEDULE_TIME)); + } else if (!priv->switched.old_link && phydev->link) { + /* If linked, keep current config, but if the linked is + * 10M speed, and config1 has been enabled, also switched + * the 10M config. + */ + if (priv->switched.config && phydev->speed == SPEED_10) + rk630_phy_10m_switch_config(phydev, true); + + priv->switched.old_link = 1; + priv->switched.detected_count = 0; + /* Record base packet statistics to compare later, if linked */ + if (!priv->switched.linked_count) + rk630_phy_packet_statistics(priv->phydev, + &priv->switched.rx_pkt_cnt, + &priv->switched.rx_crc_err_cnt); + schedule_delayed_work(&priv->service_task, + msecs_to_jiffies(RX_DETECT_SCHEDULE_TIME)); + } + mutex_unlock(&priv->lock); + } +} + +static ssize_t rk630_phy_disable_switch_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct phy_device *phydev = to_phy_device(dev); + struct rk630_phy_priv *priv = phydev->priv; + int ret; + bool disabled; + + ret = kstrtobool(buf, &disabled); + if (ret) + return count; + + mutex_lock(&priv->lock); + if (disabled) { + cancel_delayed_work_sync(&priv->service_task); + + /* Save to default config */ + rk630_phy_10m_switch_config(priv->phydev, false); + rk630_phy_switch_rx_signal_config(priv->phydev, false); + rk630_phy_switch_config(priv->phydev, false); + + memset(&priv->switched, 0, sizeof(struct rk630_phy_switched)); + } else { + priv->switched.old_link = phydev->link; + /* Rx detected threshold 260 mv */ + rk630_phy_switch_rx_signal_config(priv->phydev, true); + + schedule_delayed_work(&priv->service_task, + msecs_to_jiffies(RX_DETECT_INIT_WAIT_TIME)); + } + priv->disable_switch = disabled; + dev_info(dev, "rk630 phy disable switch to %s\n", disabled ? "true" : "false"); + mutex_unlock(&priv->lock); + + return count; +} +static DEVICE_ATTR_WO(rk630_phy_disable_switch); + static irqreturn_t rk630_wol_irq_thread(int irq, void *dev_id) { struct rk630_phy_priv *priv = (struct rk630_phy_priv *)dev_id; @@ -334,6 +676,7 @@ static irqreturn_t rk630_wol_irq_thread(int irq, void *dev_id) static int rk630_phy_probe(struct phy_device *phydev) { struct rk630_phy_priv *priv; + const char *tz_name; int ret; priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); @@ -362,6 +705,23 @@ static int rk630_phy_probe(struct phy_device *phydev) enable_irq_wake(priv->wol_irq); } + mutex_init(&priv->lock); + INIT_DELAYED_WORK(&priv->service_task, rk630_phy_service_task); + + priv->disable_switch = of_property_read_bool(phydev->mdio.dev.of_node, + "rk630,phy-disable-switch"); + of_property_read_string(phydev->mdio.dev.of_node, "rockchip,thermal-zone", + &tz_name); + priv->tz = thermal_zone_get_zone_by_name(tz_name); + if (IS_ERR(priv->tz)) { + pr_warn("Error getting thermal zone, not yet ready?\n"); + priv->tz = NULL; + } + + ret = device_create_file(&phydev->mdio.dev, &dev_attr_rk630_phy_disable_switch); + if (ret) + return ret; + priv->phydev = phydev; return 0; @@ -384,6 +744,10 @@ static int rk630_phy_suspend(struct phy_device *phydev) phy_write(phydev, REG_INTERRUPT_MASK, BIT(14)); enable_irq(priv->wol_irq); } + + if (!priv->disable_switch) + cancel_delayed_work_sync(&priv->service_task); + return genphy_suspend(phydev); } @@ -397,6 +761,10 @@ static int rk630_phy_resume(struct phy_device *phydev) disable_irq(priv->wol_irq); } + if (!priv->disable_switch) + schedule_delayed_work(&priv->service_task, + msecs_to_jiffies(RX_DETECT_INIT_WAIT_TIME)); + return genphy_resume(phydev); } @@ -407,7 +775,7 @@ static struct phy_driver rk630_phy_driver[] = { .name = "RK630 PHY", .features = PHY_BASIC_FEATURES, .flags = 0, - .link_change_notify = rk630_link_change_notify, + .link_change_notify = rk630_phy_link_change_notify, .probe = rk630_phy_probe, .remove = rk630_phy_remove, .soft_reset = genphy_soft_reset, From cbf09af6d1191b90f2b7856ef23487e3abdef631 Mon Sep 17 00:00:00 2001 From: David Wu Date: Wed, 27 Dec 2023 16:42:28 +0800 Subject: [PATCH 07/22] ARM: dts: rv1106: Add thermal for macphy Signed-off-by: David Wu Change-Id: I3319dfc7cd6377cc6e4ade4b9930474a59441aac --- arch/arm/boot/dts/rv1106.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/rv1106.dtsi b/arch/arm/boot/dts/rv1106.dtsi index ee3a90ba9136..6180d18da690 100644 --- a/arch/arm/boot/dts/rv1106.dtsi +++ b/arch/arm/boot/dts/rv1106.dtsi @@ -1359,6 +1359,7 @@ nvmem-cells = <&macphy_txlevel>; nvmem-cell-names = "txlevel"; bgs,increment = <2>; + rockchip,thermal-zone = "soc-thermal"; }; }; From 10ed38ef37daa3d4f2644ce0d875629cf42d5ef4 Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 10 Oct 2023 16:42:41 +0800 Subject: [PATCH 08/22] arm64: dts: rockchip: rk3528: Add thermal for macphy Signed-off-by: David Wu Change-Id: Ifd46d8a3ae7fd8eca31f413a6d8b7b584c983636 --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index 68f254452f7c..b94c8dc8af72 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -2095,6 +2095,7 @@ pinctrl-0 = <&fephym0_led_link &fephym0_led_spd>; nvmem-cells = <&macphy_txlevel>; nvmem-cell-names = "txlevel"; + rockchip,thermal-zone = "soc-thermal"; }; }; From f8d9b2d3b4576009a97ef0945af2dc18c03d9fe7 Mon Sep 17 00:00:00 2001 From: Cai YiWei Date: Tue, 2 Jan 2024 11:43:44 +0800 Subject: [PATCH 09/22] media: rockchip: isp: fix wait timeout with thunderboot Change-Id: Ied63c17c68e1cd565a3f246655fa9ec66be638b3 Signed-off-by: Cai YiWei --- drivers/media/platform/rockchip/isp/rkisp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/platform/rockchip/isp/rkisp.c b/drivers/media/platform/rockchip/isp/rkisp.c index ac40adfbde33..c9ffd1ed9094 100644 --- a/drivers/media/platform/rockchip/isp/rkisp.c +++ b/drivers/media/platform/rockchip/isp/rkisp.c @@ -1948,6 +1948,9 @@ static void rkisp_start_3a_run(struct rkisp_device *dev) return; v4l2_event_queue(vdev, &ev); + /* thunderboot no need to wait aiq first param */ + if (dev->is_pre_on) + return; /* rk3326/px30 require first params queued before * rkisp_params_configure_isp() called */ From 2846affd16b420a5c7b6529a8d56a52600752b43 Mon Sep 17 00:00:00 2001 From: Cai YiWei Date: Wed, 3 Jan 2024 15:35:29 +0800 Subject: [PATCH 10/22] media: rockchip: isp: add buf cnt info to procfs Change-Id: I78ce99dad93e57c544e150013ccac02868d43f88 Signed-off-by: Cai YiWei --- drivers/media/platform/rockchip/isp/capture.c | 17 +++++++++++++++++ drivers/media/platform/rockchip/isp/capture.h | 1 + drivers/media/platform/rockchip/isp/procfs.c | 19 ++++++++++++------- 3 files changed, 30 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/rockchip/isp/capture.c b/drivers/media/platform/rockchip/isp/capture.c index a43e6e4f9963..6ad7050b4922 100644 --- a/drivers/media/platform/rockchip/isp/capture.c +++ b/drivers/media/platform/rockchip/isp/capture.c @@ -475,6 +475,23 @@ void rkisp_stream_buf_done_early(struct rkisp_device *dev) } } +int rkisp_stream_buf_cnt(struct rkisp_stream *stream) +{ + unsigned long lock_flags = 0; + struct rkisp_buffer *buf, *tmp; + int cnt = 0; + + spin_lock_irqsave(&stream->vbq_lock, lock_flags); + list_for_each_entry_safe(buf, tmp, &stream->buf_queue, queue) + cnt++; + if (stream->curr_buf) + cnt++; + if (stream->next_buf && stream->next_buf != stream->curr_buf) + cnt++; + spin_unlock_irqrestore(&stream->vbq_lock, lock_flags); + return cnt; +} + struct stream_config rkisp_mp_stream_config = { /* constraints */ .max_rsz_width = STREAM_MAX_MP_RSZ_OUTPUT_WIDTH, diff --git a/drivers/media/platform/rockchip/isp/capture.h b/drivers/media/platform/rockchip/isp/capture.h index bbdcf1e6df6e..d382f6cd888c 100644 --- a/drivers/media/platform/rockchip/isp/capture.h +++ b/drivers/media/platform/rockchip/isp/capture.h @@ -342,4 +342,5 @@ int rkisp_fop_release(struct file *file); int rkisp_get_tb_stream_info(struct rkisp_stream *stream, struct rkisp_tb_stream_info *info); int rkisp_free_tb_stream_buf(struct rkisp_stream *stream); +int rkisp_stream_buf_cnt(struct rkisp_stream *stream); #endif /* _RKISP_PATH_VIDEO_H */ diff --git a/drivers/media/platform/rockchip/isp/procfs.c b/drivers/media/platform/rockchip/isp/procfs.c index a0b38ff1f97a..cf2949d5e9db 100644 --- a/drivers/media/platform/rockchip/isp/procfs.c +++ b/drivers/media/platform/rockchip/isp/procfs.c @@ -833,6 +833,7 @@ static int isp_show(struct seq_file *p, void *v) struct rkisp_device *dev = p->private; struct rkisp_isp_subdev *sdev = &dev->isp_sdev; struct rkisp_sensor_info *sensor = dev->active_sensor; + struct rkisp_stream *stream; u32 val = 0; seq_printf(p, "%-10s Version:v%02x.%02x.%02x\n", @@ -864,7 +865,9 @@ static int isp_show(struct seq_file *p, void *v) return 0; if (IS_HDR_RDBK(dev->hdr.op_mode)) { - seq_printf(p, "%-10s mode:frame%d (frame:%d rate:%dms %s time:%dms frameloss:%d) cnt(total:%d X1:%d X2:%d X3:%d)\n", + stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2]; + seq_printf(p, "%-10s mode:frame%d (frame:%d rate:%dms state:%s time:%dms frameloss:%d)" + " cnt(total:%d X1:%d X2:%d X3:%d) rd_bufcnt:%d\n", "Isp Read", dev->rd_mode - 3, dev->dmarx_dev.cur_frame.id, @@ -875,12 +878,13 @@ static int isp_show(struct seq_file *p, void *v) dev->rdbk_cnt, dev->rdbk_cnt_x1, dev->rdbk_cnt_x2, - dev->rdbk_cnt_x3); + dev->rdbk_cnt_x3, + rkisp_stream_buf_cnt(stream)); seq_printf(p, "\t hw link:%d idle:%d vir(mode:%d index:%d)\n", dev->hw_dev->dev_link_num, dev->hw_dev->is_idle, dev->multi_mode, dev->multi_index); } else { - seq_printf(p, "%-10s frame:%d %s time:%dms v-blank:%dus\n", + seq_printf(p, "%-10s frame:%d state:%s time:%dms v-blank:%dus\n", "Isp online", sdev->dbg.id, (dev->isp_state & ISP_FRAME_END) ? "idle" : "working", @@ -899,11 +903,11 @@ static int isp_show(struct seq_file *p, void *v) dev->br_dev.dbg.interval / 1000 / 1000, dev->br_dev.dbg.frameloss); for (val = 0; val < RKISP_MAX_STREAM; val++) { - struct rkisp_stream *stream = &dev->cap_dev.stream[val]; - + stream = &dev->cap_dev.stream[val]; if (!stream->streaming) continue; - seq_printf(p, "%-10s %s Format:%c%c%c%c Size:%dx%d Dcrop(%d,%d|%dx%d) (frame:%d rate:%dms delay:%dms frameloss:%d)\n", + seq_printf(p, "%-10s %s Format:%c%c%c%c Size:%dx%d Dcrop(%d,%d|%dx%d)" + " (frame:%d rate:%dms delay:%dms frameloss:%d bufcnt:%d)\n", "Output", stream->vnode.vdev.name, stream->out_fmt.pixelformat, @@ -919,7 +923,8 @@ static int isp_show(struct seq_file *p, void *v) stream->dbg.id, stream->dbg.interval / 1000 / 1000, stream->dbg.delay / 1000 / 1000, - stream->dbg.frameloss); + stream->dbg.frameloss, + rkisp_stream_buf_cnt(stream)); } switch (dev->isp_ver) { From 4227edfdb3200d2968303fc1fcfa186cd72d539b Mon Sep 17 00:00:00 2001 From: XiaoDong Huang Date: Wed, 27 Dec 2023 11:04:08 +0800 Subject: [PATCH 11/22] ARM: rockchip: rv1106_pm: do wdt save/restore Signed-off-by: XiaoDong Huang Change-Id: Ie805d22a99110162015a51718ec29de2e6008614 --- arch/arm/mach-rockchip/rv1106_pm.c | 26 ++++++++++++++++++++++++++ arch/arm/mach-rockchip/rv1106_pm.h | 10 ++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/arm/mach-rockchip/rv1106_pm.c b/arch/arm/mach-rockchip/rv1106_pm.c index ff26f6b16a0e..fbf7eae02596 100644 --- a/arch/arm/mach-rockchip/rv1106_pm.c +++ b/arch/arm/mach-rockchip/rv1106_pm.c @@ -98,6 +98,8 @@ static void __iomem *firewall_syssram_base; static void __iomem *pmu_base; static void __iomem *nstimer_base; static void __iomem *stimer_base; +static void __iomem *wdt_ns_base; +static void __iomem *wdt_s_base; static void __iomem *mbox_base; static void __iomem *ddrc_base; static void __iomem *ioc_base[5]; @@ -178,6 +180,10 @@ static struct reg_region vd_log_reg_rgns[] = { { REG_REGION(0x304, 0x32c, 4, &pericru_base, WMSK_VAL)}, { REG_REGION(0x800, 0x81c, 4, &pericru_base, WMSK_VAL)}, + /* peri_grf */ + { REG_REGION(0x000, 0x004, 4, &perigrf_base, WMSK_VAL)}, + { REG_REGION(0x090, 0x094, 4, &perigrf_base, WMSK_VAL)}, + /* peri_sgrf */ { REG_REGION(0x004, 0x014, 4, &perisgrf_base, 0)}, { REG_REGION(0x000, 0x000, 4, &perisgrf_base, 0)}, @@ -284,6 +290,14 @@ static struct reg_region vd_log_reg_rgns[] = { { REG_REGION(0x10, 0x10, 4, &stimer_base, 0)}, { REG_REGION(0x20, 0x24, 4, &stimer_base, 0)}, { REG_REGION(0x30, 0x30, 4, &stimer_base, 0)}, + + /* wdt_ns */ + { REG_REGION(0x04, 0x04, 4, &wdt_ns_base, 0)}, + { REG_REGION(0x00, 0x00, 4, &wdt_ns_base, 0)}, + + /* wdt_s */ + { REG_REGION(0x04, 0x04, 4, &wdt_s_base, 0)}, + { REG_REGION(0x00, 0x00, 4, &wdt_s_base, 0)}, }; static int is_rv1103, is_rv1106; @@ -1040,6 +1054,15 @@ static void vd_log_regs_restore(void) writel_relaxed(WITH_16BITS_WMSK(cru_mode), cru_base + 0x280); gic400_restore(); + + writel_relaxed(0xffff0000, pmugrf_base + RV1106_PMUGRF_SOC_CON(4)); + writel_relaxed(0xffff0000, pmugrf_base + RV1106_PMUGRF_SOC_CON(5)); + + if (readl_relaxed(wdt_ns_base + RV1106_WDT_CR) & 0x1) + writel_relaxed(0x76, wdt_ns_base + RV1106_WDT_CRR); + + if (readl_relaxed(wdt_s_base + RV1106_WDT_CR) & 0x1) + writel_relaxed(0x76, wdt_s_base + RV1106_WDT_CRR); } static void rkpm_reg_rgns_init(void) @@ -1182,6 +1205,9 @@ static int __init rv1106_suspend_init(struct device_node *np) nstimer_base = dev_reg_base + RV1106_NSTIMER_OFFSET; stimer_base = dev_reg_base + RV1106_STIMER_OFFSET; + wdt_ns_base = dev_reg_base + RV1106_WDTNS_OFFSET; + wdt_s_base = dev_reg_base + RV1106_WDTS_OFFSET; + pmu_base = dev_reg_base + RV1106_PMU_OFFSET; uartdbg_base = dev_reg_base + RV1106_UART2_OFFSET; pmupvtm_base = dev_reg_base + RV1106_PMUPVTM_OFFSET; diff --git a/arch/arm/mach-rockchip/rv1106_pm.h b/arch/arm/mach-rockchip/rv1106_pm.h index a3db55d09abc..cd07adc1acc6 100644 --- a/arch/arm/mach-rockchip/rv1106_pm.h +++ b/arch/arm/mach-rockchip/rv1106_pm.h @@ -56,6 +56,8 @@ #define RV1106_NSTIMER_OFFSET 0x580000 #define RV1106_STIMER_OFFSET 0x590000 +#define RV1106_WDTNS_OFFSET 0x5a0000 +#define RV1106_WDTS_OFFSET 0x5b0000 #define RV1106_MBOX_OFFSET 0x5c0000 #define RV1106_PMUSRAM_OFFSET 0x670000 #define RV1106_DDRC_OFFSET 0x800000 @@ -185,6 +187,14 @@ #define RV1106_PMU_INFO_TX_CON 0x150 #define RV1106_PMU_SYS_REG(i) (0x1c0 + (i) * 4) +/* wdt */ +#define RV1106_WDT_CR 0x0 +#define RV1106_WDT_TORR 0x4 +#define RV1106_WDT_CCVR 0x8 +#define RV1106_WDT_CRR 0xc +#define RV1106_WDT_STAT 0x10 +#define RV1106_WDT_EOI 0x14 + #define PMU_SUSPEND_MAGIC 0x02468ace #define PMU_RESUME_MAGIC 0x13579bdf From 77a1b088963fc9bb25ee0bea1f243bc6a28fd584 Mon Sep 17 00:00:00 2001 From: Yandong Lin Date: Fri, 15 Sep 2023 16:44:49 +0800 Subject: [PATCH 12/22] video: rockchip: mpp: remove av1dec l2 cache Signed-off-by: Yandong Lin Change-Id: If018c12464264f62db4baa658b75d8942504a765 --- drivers/video/rockchip/mpp/mpp_av1dec.c | 82 ------------------------- 1 file changed, 82 deletions(-) diff --git a/drivers/video/rockchip/mpp/mpp_av1dec.c b/drivers/video/rockchip/mpp/mpp_av1dec.c index 33e118ae6450..b2449a870158 100644 --- a/drivers/video/rockchip/mpp/mpp_av1dec.c +++ b/drivers/video/rockchip/mpp/mpp_av1dec.c @@ -467,87 +467,6 @@ free_task: #define AV1_PP_TILE_SIZE GENMASK_ULL(10, 9) #define AV1_PP_TILE_16X16 BIT(10) -#define AV1_PP_OUT_LUMA_ADR_INDEX 326 -#define AV1_PP_OUT_CHROMA_ADR_INDEX 328 - -#define AV1_L2_CACHE_SHAPER_CTRL 0x20 -#define AV1_L2_CACHE_SHAPER_EN BIT(0) -#define AV1_L2_CACHE_INT_MASK 0x30 -#define AV1_L2_CACHE_PP0_Y_CONFIG0 0x84 -#define AV1_L2_CACHE_PP0_Y_CONFIG2 0x8c -#define AV1_L2_CACHE_PP0_Y_CONFIG3 0x90 -#define AV1_L2_CACHE_PP0_U_CONFIG0 0x98 -#define AV1_L2_CACHE_PP0_U_CONFIG2 0xa0 -#define AV1_L2_CACHE_PP0_U_CONFIG3 0xa4 - -#define AV1_L2_CACHE_RD_ONLY_CTRL 0x204 -#define AV1_L2_CACHE_RD_ONLY_CONFIG 0x208 - -static int av1dec_set_l2_cache(struct av1dec_dev *dec, struct av1dec_task *task) -{ - int val; - u32 *regs = (u32 *)task->reg_class[0].data; - u32 width = (regs[4] >> 19) * 8; - u32 height = ((regs[4] >> 6) & 0x1fff) * 8; - u32 pixel_width = (((regs[322]) >> 27) & 0x1F) == 1 ? 8 : 16; - u32 pre_fetch_height = 136; - u32 max_h; - u32 line_cnt; - u32 line_size; - u32 line_stride; - - /* channel 4, PPU0_Y Configuration */ - /* afbc sharper can't use open cache. - * afbc out must be tile 16x16. - */ - if ((regs[AV1_PP_CONFIG_INDEX] & AV1_PP_TILE_SIZE) != AV1_PP_TILE_16X16) { - line_size = MPP_ALIGN(MPP_ALIGN(width * pixel_width, 8) / 8, 16); - line_stride = MPP_ALIGN(MPP_ALIGN(width * pixel_width, 8) / 8, 16) >> 4; - line_cnt = height; - max_h = pre_fetch_height; - - writel_relaxed(regs[AV1_PP_OUT_LUMA_ADR_INDEX] + 0x1, - dec->reg_base[AV1DEC_CLASS_CACHE] + AV1_L2_CACHE_PP0_Y_CONFIG0); - val = line_size | (line_stride << 16); - writel_relaxed(val, dec->reg_base[AV1DEC_CLASS_CACHE] + AV1_L2_CACHE_PP0_Y_CONFIG2); - - val = line_cnt | (max_h << 16); - writel_relaxed(val, dec->reg_base[AV1DEC_CLASS_CACHE] + AV1_L2_CACHE_PP0_Y_CONFIG3); - - /* channel 5, PPU0_U Configuration */ - line_size = MPP_ALIGN(MPP_ALIGN(width * pixel_width, 8) / 8, 16); - line_stride = MPP_ALIGN(MPP_ALIGN(width * pixel_width, 8) / 8, 16) >> 4; - line_cnt = height >> 1; - max_h = pre_fetch_height >> 1; - - writel_relaxed(regs[AV1_PP_OUT_CHROMA_ADR_INDEX] + 0x1, - dec->reg_base[AV1DEC_CLASS_CACHE] + AV1_L2_CACHE_PP0_U_CONFIG0); - val = line_size | (line_stride << 16); - writel_relaxed(val, dec->reg_base[AV1DEC_CLASS_CACHE] + AV1_L2_CACHE_PP0_U_CONFIG2); - - val = line_cnt | (max_h << 16); - writel_relaxed(val, dec->reg_base[AV1DEC_CLASS_CACHE] + AV1_L2_CACHE_PP0_U_CONFIG3); - /* mask cache irq */ - writel_relaxed(0xf, dec->reg_base[AV1DEC_CLASS_CACHE] + AV1_L2_CACHE_INT_MASK); - - /* shaper enable */ - writel_relaxed(AV1_L2_CACHE_SHAPER_EN, - dec->reg_base[AV1DEC_CLASS_CACHE] + AV1_L2_CACHE_SHAPER_CTRL); - - /* not enable cache en when multi tiles */ - if (!(regs[10] & BIT(1))) - /* cache all en */ - writel_relaxed(0x00000001, dec->reg_base[AV1DEC_CLASS_CACHE] + - AV1_L2_CACHE_RD_ONLY_CONFIG); - /* reorder_e and cache_e */ - writel_relaxed(0x00000081, dec->reg_base[AV1DEC_CLASS_CACHE] + - AV1_L2_CACHE_RD_ONLY_CTRL); - /* wmb */ - wmb(); - } - - return 0; -} #define REG_CONTROL 0x20 #define REG_INTRENBL 0x34 #define REG_ACKNOWLEDGE 0x38 @@ -656,7 +575,6 @@ static int av1dec_run(struct mpp_dev *mpp, struct mpp_task *mpp_task) mpp_debug_enter(); mpp_iommu_flush_tlb(mpp->iommu_info); - av1dec_set_l2_cache(dec, task); av1dec_set_afbc(dec, task); for (i = 0; i < task->w_req_cnt; i++) { From aa47569d066e59b2f40b29d9b9bc5106eab8833e Mon Sep 17 00:00:00 2001 From: Jianwei Fan Date: Fri, 15 Dec 2023 11:45:48 +0000 Subject: [PATCH 13/22] media: i2c: lt8668sx: add lt8668sx hdmi2csi driver Change-Id: I4fba2eb4aca597ba41a08a89c6444f9a715c4630 Signed-off-by: Jianwei Fan --- drivers/media/i2c/Kconfig | 11 + drivers/media/i2c/Makefile | 1 + drivers/media/i2c/lt8668sx.c | 1794 ++++++++++++++++++++++++++++++++++ 3 files changed, 1806 insertions(+) create mode 100644 drivers/media/i2c/lt8668sx.c diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 2202262b7d4a..6b79fa863217 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -420,6 +420,17 @@ config VIDEO_LT8619C To compile this driver as a module, choose M here: the module will be called lt8619c. +config VIDEO_LT8668SX + tristate "Lontium LT8668SX decoder" + depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API + select HDMI + select V4L2_FWNODE + help + Support for the Lontium LT8668SX series type-c/hdmi to MIPI CSI-2 bridge. + + To compile this driver as a module, choose M here: the + module will be called lt8668sx. + config VIDEO_ML86V7667 tristate "OKI ML86V7667 video decoder" depends on VIDEO_V4L2 && I2C diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index 12a0f5971f50..9046d5331b77 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -182,6 +182,7 @@ obj-$(CONFIG_VIDEO_IT6616) += it6616.o obj-$(CONFIG_VIDEO_LT7911D) += lt7911d.o obj-$(CONFIG_VIDEO_LT7911UXC) += lt7911uxc.o obj-$(CONFIG_VIDEO_LT8619C) += lt8619c.o +obj-$(CONFIG_VIDEO_LT8668SX) += lt8668sx.o obj-$(CONFIG_VIDEO_SMIAPP_PLL) += smiapp-pll.o obj-$(CONFIG_VIDEO_AK881X) += ak881x.o obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o diff --git a/drivers/media/i2c/lt8668sx.c b/drivers/media/i2c/lt8668sx.c new file mode 100644 index 000000000000..8d5b63a7e39c --- /dev/null +++ b/drivers/media/i2c/lt8668sx.c @@ -0,0 +1,1794 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Rockchip Electronics Co. Ltd. + * + * lt8668sx HDMI to MIPI CSI-2 bridge driver. + * + * Author: Jianwei Fan + * + * V0.0X01.0X00 first version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00) + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "debug level (0-3)"); + +#define I2C_MAX_XFER_SIZE 128 +#define POLL_INTERVAL_MS 1000 + +#define LT8668SX_LINK_FREQ_1250M 1250000000 +#define LT8668SX_LINK_FREQ_1000M 1000000000 +#define LT8668SX_LINK_FREQ_900M 900000000 +#define LT8668SX_LINK_FREQ_700M 700000000 +#define LT8668SX_LINK_FREQ_650M 650000000 +#define LT8668SX_LINK_FREQ_600M 600000000 +#define LT8668SX_LINK_FREQ_490M 490000000 +#define LT8668SX_LINK_FREQ_400M 400000000 +#define LT8668SX_LINK_FREQ_300M 300000000 +#define LT8668SX_LINK_FREQ_250M 250000000 +#define LT8668SX_LINK_FREQ_200M 200000000 +#define LT8668SX_LINK_FREQ_100M 100000000 + +#define LT8668SX_PIXEL_RATE 800000000 + +#define LT8668SX_CHIPID 0x0119 +#define CHIPID_REGH 0xe101 +#define CHIPID_REGL 0xe100 +#define I2C_EN_REG 0xe0ee +#define I2C_ENABLE 0x1 +#define I2C_DISABLE 0x0 + +#define HACT_H 0xe090 +#define HACT_L 0xe091 + +#define VACT_H 0xe092 +#define VACT_L 0xe093 + +#define PCLK_H 0xe095 +#define PCLK_M 0xe096 +#define PCLK_L 0xe097 + +#define FRAMERATE 0xe094 +#define AUDIO_FS_VALUE 0xe098 +#define INTERLACED 0xe099 + +#define LT8668SX_NAME "LT8668SX" + +static const s64 link_freq_dphy_menu_items[] = { + LT8668SX_LINK_FREQ_1250M, + LT8668SX_LINK_FREQ_650M, + LT8668SX_LINK_FREQ_490M, + LT8668SX_LINK_FREQ_300M, + LT8668SX_LINK_FREQ_200M, + LT8668SX_LINK_FREQ_100M, +}; + +static const s64 link_freq_cphy_menu_items[] = { + LT8668SX_LINK_FREQ_900M, + LT8668SX_LINK_FREQ_700M, + LT8668SX_LINK_FREQ_400M, + LT8668SX_LINK_FREQ_200M, + LT8668SX_LINK_FREQ_100M, +}; + +static const s64 link_freq_cphy_rgb_menu_items[] = { + LT8668SX_LINK_FREQ_1250M, + LT8668SX_LINK_FREQ_1000M, + LT8668SX_LINK_FREQ_600M, + LT8668SX_LINK_FREQ_300M, + LT8668SX_LINK_FREQ_200M, +}; + +struct lt8668sx { + struct v4l2_fwnode_bus_mipi_csi2 bus; + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_ctrl_handler hdl; + struct i2c_client *i2c_client; + struct mutex confctl_mutex; + struct v4l2_ctrl *detect_tx_5v_ctrl; + struct v4l2_ctrl *audio_sampling_rate_ctrl; + struct v4l2_ctrl *audio_present_ctrl; + struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *pixel_rate; + struct delayed_work delayed_work_hotplug; + struct delayed_work delayed_work_res_change; + struct v4l2_dv_timings timings; + struct clk *xvclk; + struct gpio_desc *reset_gpio; + struct gpio_desc *plugin_det_gpio; + struct gpio_desc *power_gpio; + struct work_struct work_i2c_poll; + struct timer_list timer; + const char *module_facing; + const char *module_name; + const char *len_name; + const struct lt8668sx_mode *cur_mode; + const struct lt8668sx_mode *support_modes; + u32 cfg_num; + struct v4l2_fwnode_endpoint bus_cfg; + bool nosignal; + bool enable_hdcp; + bool is_audio_present; + bool power_on; + int plugin_irq; + u32 mbus_fmt_code; + u32 module_index; + u32 audio_sampling_rate; + u32 cur_framerate; + u32 last_framerate; +}; + +static const struct v4l2_dv_timings_cap lt8668sx_timings_cap = { + .type = V4L2_DV_BT_656_1120, + .reserved = { 0 }, + V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 800000000, + V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | + V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, + V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_INTERLACED | + V4L2_DV_BT_CAP_REDUCED_BLANKING | + V4L2_DV_BT_CAP_CUSTOM) +}; + +struct lt8668sx_mode { + u32 width; + u32 height; + struct v4l2_fract max_fps; + u32 hts_def; + u32 vts_def; + u32 exp_def; + u32 mipi_freq_idx; +}; + +static struct rkmodule_csi_dphy_param rk3588_dcphy_param = { + .vendor = PHY_VENDOR_SAMSUNG, + .lp_vol_ref = 3, + .lp_hys_sw = {3, 0, 0, 0}, + .lp_escclk_pol_sel = {1, 0, 0, 0}, + .skew_data_cal_clk = {0, 3, 3, 3}, + .clk_hs_term_sel = 2, + .data_hs_term_sel = {2, 2, 2, 2}, + .reserved = {0}, +}; + +static const struct lt8668sx_mode supported_modes_dphy[] = { + { + .width = 4096, + .height = 2160, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .hts_def = 4400, + .vts_def = 2250, + .mipi_freq_idx = 0, + }, { + .width = 3840, + .height = 2160, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .hts_def = 4400, + .vts_def = 2250, + .mipi_freq_idx = 0, + }, { + .width = 3840, + .height = 2160, + .max_fps = { + .numerator = 10000, + .denominator = 300000, + }, + .hts_def = 4400, + .vts_def = 2250, + .mipi_freq_idx = 1, + }, { + .width = 2560, + .height = 1440, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .hts_def = 2720, + .vts_def = 1481, + .mipi_freq_idx = 2, + }, { + .width = 1920, + .height = 1080, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .hts_def = 2200, + .vts_def = 1125, + .mipi_freq_idx = 3, + }, { + .width = 1600, + .height = 1200, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .hts_def = 2160, + .vts_def = 1250, + .mipi_freq_idx = 3, + }, { + .width = 1280, + .height = 960, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .hts_def = 1712, + .vts_def = 994, + .mipi_freq_idx = 4, + }, { + .width = 1280, + .height = 720, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .hts_def = 1650, + .vts_def = 750, + .mipi_freq_idx = 4, + }, { + .width = 800, + .height = 600, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .hts_def = 1056, + .vts_def = 628, + .mipi_freq_idx = 5, + }, { + .width = 720, + .height = 576, + .max_fps = { + .numerator = 10000, + .denominator = 500000, + }, + .hts_def = 864, + .vts_def = 625, + .mipi_freq_idx = 5, + }, { + .width = 720, + .height = 480, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .hts_def = 858, + .vts_def = 525, + .mipi_freq_idx = 5, + }, +}; + +static const struct lt8668sx_mode supported_modes_cphy[] = { + { + .width = 5120, + .height = 2160, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .hts_def = 5500, + .vts_def = 2250, + .mipi_freq_idx = 0, + }, { + .width = 4096, + .height = 2160, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .hts_def = 4400, + .vts_def = 2250, + .mipi_freq_idx = 1, + }, { + .width = 3840, + .height = 2160, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .hts_def = 4400, + .vts_def = 2250, + .mipi_freq_idx = 1, + }, { + .width = 3840, + .height = 2160, + .max_fps = { + .numerator = 10000, + .denominator = 300000, + }, + .hts_def = 4400, + .vts_def = 2250, + .mipi_freq_idx = 2, + }, { + .width = 2560, + .height = 1440, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .hts_def = 2720, + .vts_def = 1481, + .mipi_freq_idx = 2, + }, { + .width = 1920, + .height = 1080, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .hts_def = 2200, + .vts_def = 1125, + .mipi_freq_idx = 3, + }, { + .width = 1280, + .height = 720, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .hts_def = 1650, + .vts_def = 750, + .mipi_freq_idx = 4, + }, { + .width = 1024, + .height = 768, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .hts_def = 1344, + .vts_def = 806, + .mipi_freq_idx = 4, + }, { + .width = 800, + .height = 600, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .hts_def = 1056, + .vts_def = 628, + .mipi_freq_idx = 4, + }, { + .width = 720, + .height = 576, + .max_fps = { + .numerator = 10000, + .denominator = 500000, + }, + .hts_def = 864, + .vts_def = 625, + .mipi_freq_idx = 4, + }, { + .width = 720, + .height = 480, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .hts_def = 858, + .vts_def = 525, + .mipi_freq_idx = 4, + }, +}; + +static void lt8668sx_format_change(struct v4l2_subdev *sd); +static int lt8668sx_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd); +static int lt8668sx_s_dv_timings(struct v4l2_subdev *sd, + struct v4l2_dv_timings *timings); + +static inline struct lt8668sx *to_lt8668sx(struct v4l2_subdev *sd) +{ + return container_of(sd, struct lt8668sx, sd); +} + +static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + struct i2c_client *client = lt8668sx->i2c_client; + int err; + u8 buf[2] = { 0xFF, reg >> 8}; + u8 reg_addr = reg & 0xFF; + struct i2c_msg msgs[3]; + + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = 2; + msgs[0].buf = buf; + + msgs[1].addr = client->addr; + msgs[1].flags = 0; + msgs[1].len = 1; + msgs[1].buf = ®_addr; + + msgs[2].addr = client->addr; + msgs[2].flags = I2C_M_RD; + msgs[2].len = n; + msgs[2].buf = values; + + err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (err != ARRAY_SIZE(msgs)) { + v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n", + __func__, reg, client->addr); + } +} + +static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + struct i2c_client *client = lt8668sx->i2c_client; + int err, i; + struct i2c_msg msgs[2]; + u8 data[I2C_MAX_XFER_SIZE]; + u8 buf[2] = { 0xFF, reg >> 8}; + + if ((1 + n) > I2C_MAX_XFER_SIZE) { + n = I2C_MAX_XFER_SIZE - 1; + v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n", + reg, 1 + n); + } + + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = 2; + msgs[0].buf = buf; + + msgs[1].addr = client->addr; + msgs[1].flags = 0; + msgs[1].len = 1 + n; + msgs[1].buf = data; + + data[0] = reg & 0xff; + for (i = 0; i < n; i++) + data[1 + i] = values[i]; + + err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (err < 0) { + v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n", + __func__, reg, client->addr); + return; + } +} + +static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg) +{ + u32 val; + + i2c_rd(sd, reg, (u8 __force *)&val, 1); + return val; +} + +static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val) +{ + i2c_wr(sd, reg, &val, 1); +} + +static void lt8668sx_i2c_enable(struct v4l2_subdev *sd) +{ + i2c_wr8(sd, I2C_EN_REG, I2C_ENABLE); +} + +static void lt8668sx_i2c_disable(struct v4l2_subdev *sd) +{ + i2c_wr8(sd, I2C_EN_REG, I2C_DISABLE); +} + +static inline bool tx_5v_power_present(struct v4l2_subdev *sd) +{ + bool ret; + int val, i, cnt; + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + + /* if not use plugin det gpio */ + if (!lt8668sx->plugin_det_gpio) + return true; + + cnt = 0; + for (i = 0; i < 5; i++) { + val = gpiod_get_value(lt8668sx->plugin_det_gpio); + if (val > 0) + cnt++; + usleep_range(500, 600); + } + + ret = (cnt >= 3) ? true : false; + v4l2_dbg(1, debug, sd, "%s: %d\n", __func__, ret); + + return ret; +} + +static inline bool no_signal(struct v4l2_subdev *sd) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + + v4l2_dbg(1, debug, sd, "%s no signal:%d\n", __func__, + lt8668sx->nosignal); + + return lt8668sx->nosignal; +} + +static inline bool audio_present(struct v4l2_subdev *sd) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + + return lt8668sx->is_audio_present; +} + +static int get_audio_sampling_rate(struct v4l2_subdev *sd) +{ + static const int code_to_rate[] = { + 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800, + 88200, 768000, 96000, 705600, 176400, 0, 192000, 0 + }; + + if (no_signal(sd)) + return 0; + + return code_to_rate[2]; +} + +static inline unsigned int fps_calc(const struct v4l2_bt_timings *t) +{ + if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t)) + return 0; + + return DIV_ROUND_CLOSEST((unsigned int)t->pixelclock, + V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t)); +} + +static bool lt8668sx_rcv_supported_res(struct v4l2_subdev *sd, u32 width, + u32 height) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + u32 i; + + for (i = 0; i < lt8668sx->cfg_num; i++) { + if ((lt8668sx->support_modes[i].width == width) && + (lt8668sx->support_modes[i].height == height)) { + break; + } + } + + if (i == lt8668sx->cfg_num) { + v4l2_err(sd, "%s do not support res wxh: %dx%d\n", __func__, + width, height); + return false; + } else { + return true; + } +} + +static int lt8668sx_get_detected_timings(struct v4l2_subdev *sd, + struct v4l2_dv_timings *timings) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + struct v4l2_bt_timings *bt = &timings->bt; + u32 hact, vact; + u32 pixel_clock, fps, halt_pix_clk; + u8 clk_h, clk_m, clk_l; + u8 val_h, val_l; + u8 interlaced, audio_rate; + + memset(timings, 0, sizeof(struct v4l2_dv_timings)); + + clk_h = i2c_rd8(sd, PCLK_H); + clk_m = i2c_rd8(sd, PCLK_M); + clk_l = i2c_rd8(sd, PCLK_L); + halt_pix_clk = ((clk_h << 16) | (clk_m << 8) | clk_l); + pixel_clock = halt_pix_clk * 1000; + + val_h = i2c_rd8(sd, HACT_H); + val_l = i2c_rd8(sd, HACT_L); + hact = ((val_h << 8) | val_l); + + val_h = i2c_rd8(sd, VACT_H); + val_l = i2c_rd8(sd, VACT_L); + vact = (val_h << 8) | val_l; + + fps = i2c_rd8(sd, FRAMERATE); + interlaced = i2c_rd8(sd, INTERLACED); + audio_rate = i2c_rd8(sd, AUDIO_FS_VALUE); + + lt8668sx->nosignal = false; + lt8668sx->is_audio_present = true; + timings->type = V4L2_DV_BT_656_1120; + bt->interlaced = interlaced; + bt->width = hact; + bt->height = vact; + bt->pixelclock = pixel_clock; + lt8668sx->cur_framerate = fps; + lt8668sx->audio_sampling_rate = audio_rate; + + v4l2_info(sd, "act:%dx%d, pixclk:%d, fps:%d, inerlaced:%d, audio_rate:%dk\n", + hact, vact, pixel_clock, fps, interlaced, audio_rate); + + if (!lt8668sx_rcv_supported_res(sd, hact, vact)) { + lt8668sx->nosignal = true; + v4l2_err(sd, "%s: rcv err res, return no signal!\n", __func__); + return -EINVAL; + } + + return 0; +} + +static void lt8668sx_delayed_work_hotplug(struct work_struct *work) +{ + struct delayed_work *dwork = to_delayed_work(work); + struct lt8668sx *lt8668sx = container_of(dwork, + struct lt8668sx, delayed_work_hotplug); + struct v4l2_subdev *sd = <8668sx->sd; + + lt8668sx_s_ctrl_detect_tx_5v(sd); +} + +static void lt8668sx_delayed_work_res_change(struct work_struct *work) +{ + struct delayed_work *dwork = to_delayed_work(work); + struct lt8668sx *lt8668sx = container_of(dwork, + struct lt8668sx, delayed_work_res_change); + struct v4l2_subdev *sd = <8668sx->sd; + + lt8668sx_format_change(sd); +} + +static int lt8668sx_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + + return v4l2_ctrl_s_ctrl(lt8668sx->detect_tx_5v_ctrl, + tx_5v_power_present(sd)); +} + +static int lt8668sx_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + + return v4l2_ctrl_s_ctrl(lt8668sx->audio_sampling_rate_ctrl, + get_audio_sampling_rate(sd)); +} + +static int lt8668sx_s_ctrl_audio_present(struct v4l2_subdev *sd) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + + return v4l2_ctrl_s_ctrl(lt8668sx->audio_present_ctrl, + audio_present(sd)); +} + +static int lt8668sx_update_controls(struct v4l2_subdev *sd) +{ + int ret = 0; + + ret |= lt8668sx_s_ctrl_detect_tx_5v(sd); + ret |= lt8668sx_s_ctrl_audio_sampling_rate(sd); + ret |= lt8668sx_s_ctrl_audio_present(sd); + + return ret; +} + +static bool lt8668sx_match_timings(struct lt8668sx *lt8668sx, const struct v4l2_dv_timings *t1, + const struct v4l2_dv_timings *t2) +{ + if (t1->type != t2->type || t1->type != V4L2_DV_BT_656_1120) + return false; + if (t1->bt.width == t2->bt.width && + t1->bt.height == t2->bt.height && + t1->bt.interlaced == t2->bt.interlaced && + lt8668sx->cur_framerate == lt8668sx->last_framerate) + return true; + + return false; +} + +static int lt8668sx_get_reso_dist(struct lt8668sx *lt8668sx, const struct lt8668sx_mode *mode, + struct v4l2_dv_timings *timings) +{ + struct v4l2_bt_timings *bt = &timings->bt; + u32 cur_fps, dist_fps; + + cur_fps = lt8668sx->cur_framerate; + dist_fps = DIV_ROUND_CLOSEST(mode->max_fps.denominator, mode->max_fps.numerator); + + return abs(mode->width - bt->width) + + abs(mode->height - bt->height) + abs(dist_fps - cur_fps); +} + +static const struct lt8668sx_mode * +lt8668sx_find_best_fit(struct v4l2_subdev *sd) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + int dist; + int cur_best_fit = 0; + int cur_best_fit_dist = -1; + unsigned int i; + + for (i = 0; i < lt8668sx->cfg_num; i++) { + dist = lt8668sx_get_reso_dist(lt8668sx, + <8668sx->support_modes[i], <8668sx->timings); + if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) { + cur_best_fit_dist = dist; + cur_best_fit = i; + } + } + v4l2_info(sd, "find current mode: support_mode[%d], %dx%d@%dfps\n", + cur_best_fit, lt8668sx->support_modes[cur_best_fit].width, + lt8668sx->support_modes[cur_best_fit].height, + DIV_ROUND_CLOSEST(lt8668sx->support_modes[cur_best_fit].max_fps.denominator, + lt8668sx->support_modes[cur_best_fit].max_fps.numerator)); + + return <8668sx->support_modes[cur_best_fit]; +} + +static void lt8668sx_print_dv_timings(struct v4l2_subdev *sd, const char *prefix) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + const struct v4l2_bt_timings *bt = <8668sx->timings.bt; + const struct lt8668sx_mode *mode; + u32 htot, vtot; + u32 fps; + + mode = lt8668sx_find_best_fit(sd); + lt8668sx->cur_mode = mode; + htot = lt8668sx->cur_mode->hts_def; + vtot = lt8668sx->cur_mode->vts_def; + if (bt->interlaced) + vtot /= 2; + + fps = lt8668sx->cur_framerate; + + if (prefix == NULL) + prefix = ""; + + v4l2_info(sd, "%s: %s%ux%u%s%u (%ux%u)\n", sd->name, prefix, + bt->width, bt->height, bt->interlaced ? "i" : "p", + fps, htot, vtot); +} + +static void lt8668sx_format_change(struct v4l2_subdev *sd) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + struct v4l2_dv_timings timings; + const struct v4l2_event lt8668sx_ev_fmt = { + .type = V4L2_EVENT_SOURCE_CHANGE, + .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, + }; + struct v4l2_dv_timings default_timing = + V4L2_DV_BT_CEA_640X480P59_94; + + if (lt8668sx_get_detected_timings(sd, &timings)) { + timings = default_timing; + v4l2_dbg(1, debug, sd, "%s: No signal\n", __func__); + } + + if (!lt8668sx_match_timings(lt8668sx, <8668sx->timings, &timings)) { + /* automatically set timing rather than set by user */ + lt8668sx_s_dv_timings(sd, &timings); + lt8668sx_print_dv_timings(sd, + "Format_change: New format: "); + if (sd->devnode && !lt8668sx->i2c_client->irq) + v4l2_subdev_notify_event(sd, <8668sx_ev_fmt); + } + if (sd->devnode && lt8668sx->i2c_client->irq) + v4l2_subdev_notify_event(sd, <8668sx_ev_fmt); +} + +static int lt8668sx_isr(struct v4l2_subdev *sd, u32 status, bool *handled) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + + schedule_delayed_work(<8668sx->delayed_work_res_change, HZ / 20); + *handled = true; + + return 0; +} + +static irqreturn_t lt8668sx_res_change_irq_handler(int irq, void *dev_id) +{ + struct lt8668sx *lt8668sx = dev_id; + bool handled; + + lt8668sx_isr(<8668sx->sd, 0, &handled); + + return handled ? IRQ_HANDLED : IRQ_NONE; +} + +static irqreturn_t plugin_detect_irq_handler(int irq, void *dev_id) +{ + struct lt8668sx *lt8668sx = dev_id; + + schedule_delayed_work(<8668sx->delayed_work_hotplug, 100); + + return IRQ_HANDLED; +} + +static void lt8668sx_irq_poll_timer(struct timer_list *t) +{ + struct lt8668sx *lt8668sx = from_timer(lt8668sx, t, timer); + + schedule_work(<8668sx->work_i2c_poll); + mod_timer(<8668sx->timer, jiffies + msecs_to_jiffies(POLL_INTERVAL_MS)); +} + +static void lt8668sx_work_i2c_poll(struct work_struct *work) +{ + struct lt8668sx *lt8668sx = container_of(work, + struct lt8668sx, work_i2c_poll); + struct v4l2_subdev *sd = <8668sx->sd; + + lt8668sx_format_change(sd); +} + +static int lt8668sx_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + switch (sub->type) { + case V4L2_EVENT_SOURCE_CHANGE: + return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); + case V4L2_EVENT_CTRL: + return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); + default: + return -EINVAL; + } +} + +static int lt8668sx_g_input_status(struct v4l2_subdev *sd, u32 *status) +{ + *status = 0; + *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; + + v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); + + return 0; +} + +static int lt8668sx_s_dv_timings(struct v4l2_subdev *sd, + struct v4l2_dv_timings *timings) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + + if (!timings) + return -EINVAL; + + if (debug) + v4l2_print_dv_timings(sd->name, "s_dv_timings: ", + timings, false); + + if (lt8668sx_match_timings(lt8668sx, <8668sx->timings, timings)) { + v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); + return 0; + } + + if (!v4l2_valid_dv_timings(timings, + <8668sx_timings_cap, NULL, NULL)) { + v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__); + return -ERANGE; + } + + lt8668sx->timings = *timings; + lt8668sx->last_framerate = lt8668sx->cur_framerate; + + return 0; +} + +static int lt8668sx_g_dv_timings(struct v4l2_subdev *sd, + struct v4l2_dv_timings *timings) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + + *timings = lt8668sx->timings; + + return 0; +} + +static int lt8668sx_enum_dv_timings(struct v4l2_subdev *sd, + struct v4l2_enum_dv_timings *timings) +{ + if (timings->pad != 0) + return -EINVAL; + + return v4l2_enum_dv_timings_cap(timings, + <8668sx_timings_cap, NULL, NULL); +} + +static int lt8668sx_query_dv_timings(struct v4l2_subdev *sd, + struct v4l2_dv_timings *timings) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + + *timings = lt8668sx->timings; + if (debug) + v4l2_print_dv_timings(sd->name, + "query_dv_timings: ", timings, false); + + if (!v4l2_valid_dv_timings(timings, <8668sx_timings_cap, NULL, + NULL)) { + v4l2_dbg(1, debug, sd, "%s: timings out of range\n", + __func__); + + return -ERANGE; + } + + return 0; +} + +static int lt8668sx_dv_timings_cap(struct v4l2_subdev *sd, + struct v4l2_dv_timings_cap *cap) +{ + if (cap->pad != 0) + return -EINVAL; + + *cap = lt8668sx_timings_cap; + + return 0; +} + +static int lt8668sx_g_mbus_config(struct v4l2_subdev *sd, + unsigned int pad, struct v4l2_mbus_config *cfg) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + u32 lane_num = lt8668sx->bus_cfg.bus.mipi_csi2.num_data_lanes; + u32 val = 0; + + val = 1 << (lane_num - 1) | + V4L2_MBUS_CSI2_CHANNEL_0 | + V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; + + cfg->type = lt8668sx->bus_cfg.bus_type; + cfg->flags = val; + + return 0; +} + +static int lt8668sx_s_stream(struct v4l2_subdev *sd, int on) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + const struct lt8668sx_mode *mode; + + mode = lt8668sx_find_best_fit(sd); + lt8668sx->cur_mode = mode; + + v4l2_info(sd, "%s: on: %d, %dx%d@%d\n", + __func__, on, lt8668sx->cur_mode->width, + lt8668sx->cur_mode->height, + DIV_ROUND_CLOSEST(lt8668sx->cur_mode->max_fps.denominator, + lt8668sx->cur_mode->max_fps.numerator)); + + msleep(100); + + return 0; +} + +static int lt8668sx_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + + switch (code->index) { + case 0: + code->code = lt8668sx->mbus_fmt_code; + break; + + default: + return -EINVAL; + } + + return 0; +} + +static int lt8668sx_enum_frame_sizes(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + + if (fse->index >= lt8668sx->cfg_num) + return -EINVAL; + + if (fse->code != lt8668sx->mbus_fmt_code) + return -EINVAL; + + fse->min_width = lt8668sx->support_modes[fse->index].width; + fse->max_width = lt8668sx->support_modes[fse->index].width; + fse->max_height = lt8668sx->support_modes[fse->index].height; + fse->min_height = lt8668sx->support_modes[fse->index].height; + + return 0; +} + +static int lt8668sx_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + const struct lt8668sx_mode *mode; + + mutex_lock(<8668sx->confctl_mutex); + format->format.code = lt8668sx->mbus_fmt_code; + format->format.width = lt8668sx->timings.bt.width; + format->format.height = lt8668sx->timings.bt.height; + format->format.field = + lt8668sx->timings.bt.interlaced ? + V4L2_FIELD_INTERLACED : V4L2_FIELD_NONE; + format->format.colorspace = V4L2_COLORSPACE_SRGB; + mutex_unlock(<8668sx->confctl_mutex); + + mode = lt8668sx_find_best_fit(sd); + lt8668sx->cur_mode = mode; + + __v4l2_ctrl_s_ctrl_int64(lt8668sx->pixel_rate, + LT8668SX_PIXEL_RATE); + __v4l2_ctrl_s_ctrl(lt8668sx->link_freq, + mode->mipi_freq_idx); + + v4l2_dbg(1, debug, sd, "%s: mode->mipi_freq_idx(%d)", + __func__, mode->mipi_freq_idx); + + v4l2_dbg(1, debug, sd, "%s: fmt code:%d, w:%d, h:%d, field code:%d\n", + __func__, format->format.code, format->format.width, + format->format.height, format->format.field); + + return 0; +} + +static int lt8668sx_enum_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum *fie) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + + if (fie->index >= lt8668sx->cfg_num) + return -EINVAL; + + fie->code = lt8668sx->mbus_fmt_code; + + fie->width = lt8668sx->support_modes[fie->index].width; + fie->height = lt8668sx->support_modes[fie->index].height; + fie->interval = lt8668sx->support_modes[fie->index].max_fps; + + return 0; +} + +static int lt8668sx_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + const struct lt8668sx_mode *mode; + + /* is overwritten by get_fmt */ + u32 code = format->format.code; + int ret = lt8668sx_get_fmt(sd, cfg, format); + + format->format.code = code; + + if (ret) + return ret; + + switch (code) { + case MEDIA_BUS_FMT_UYVY8_2X8: + break; + case MEDIA_BUS_FMT_BGR888_1X24: + break; + default: + return -EINVAL; + } + + if (format->which == V4L2_SUBDEV_FORMAT_TRY) + return 0; + + lt8668sx->mbus_fmt_code = format->format.code; + mode = lt8668sx_find_best_fit(sd); + lt8668sx->cur_mode = mode; + + return 0; +} + +static int lt8668sx_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *fi) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + const struct lt8668sx_mode *mode = lt8668sx->cur_mode; + + mutex_lock(<8668sx->confctl_mutex); + fi->interval = mode->max_fps; + mutex_unlock(<8668sx->confctl_mutex); + + return 0; +} + +static void lt8668sx_get_module_inf(struct lt8668sx *lt8668sx, + struct rkmodule_inf *inf) +{ + memset(inf, 0, sizeof(*inf)); + strscpy(inf->base.sensor, LT8668SX_NAME, sizeof(inf->base.sensor)); + strscpy(inf->base.module, lt8668sx->module_name, sizeof(inf->base.module)); + strscpy(inf->base.lens, lt8668sx->len_name, sizeof(inf->base.lens)); +} + +static long lt8668sx_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + long ret = 0; + struct rkmodule_csi_dphy_param *dphy_param; + + switch (cmd) { + case RKMODULE_GET_MODULE_INFO: + lt8668sx_get_module_inf(lt8668sx, (struct rkmodule_inf *)arg); + break; + case RKMODULE_GET_HDMI_MODE: + *(int *)arg = RKMODULE_HDMIIN_MODE; + break; + case RKMODULE_SET_CSI_DPHY_PARAM: + dphy_param = (struct rkmodule_csi_dphy_param *)arg; + if (dphy_param->vendor == PHY_VENDOR_SAMSUNG) + rk3588_dcphy_param = *dphy_param; + dev_dbg(<8668sx->i2c_client->dev, + "sensor set dphy param\n"); + break; + case RKMODULE_GET_CSI_DPHY_PARAM: + dphy_param = (struct rkmodule_csi_dphy_param *)arg; + *dphy_param = rk3588_dcphy_param; + dev_dbg(<8668sx->i2c_client->dev, + "sensor get dphy param\n"); + break; + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} + +static int lt8668sx_s_power(struct v4l2_subdev *sd, int on) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + int ret = 0; + + mutex_lock(<8668sx->confctl_mutex); + + if (lt8668sx->power_on == !!on) + goto unlock_and_return; + + if (on) + lt8668sx->power_on = true; + else + lt8668sx->power_on = false; + +unlock_and_return: + mutex_unlock(<8668sx->confctl_mutex); + + return ret; +} + +#ifdef CONFIG_COMPAT +static long lt8668sx_compat_ioctl32(struct v4l2_subdev *sd, + unsigned int cmd, unsigned long arg) +{ + void __user *up = compat_ptr(arg); + struct rkmodule_inf *inf; + long ret; + int *seq; + struct rkmodule_csi_dphy_param *dphy_param; + + switch (cmd) { + case RKMODULE_GET_MODULE_INFO: + inf = kzalloc(sizeof(*inf), GFP_KERNEL); + if (!inf) { + ret = -ENOMEM; + return ret; + } + + ret = lt8668sx_ioctl(sd, cmd, inf); + if (!ret) { + ret = copy_to_user(up, inf, sizeof(*inf)); + if (ret) + ret = -EFAULT; + } + kfree(inf); + break; + case RKMODULE_GET_HDMI_MODE: + seq = kzalloc(sizeof(*seq), GFP_KERNEL); + if (!seq) { + ret = -ENOMEM; + return ret; + } + + ret = lt8668sx_ioctl(sd, cmd, seq); + if (!ret) { + ret = copy_to_user(up, seq, sizeof(*seq)); + if (ret) + ret = -EFAULT; + } + kfree(seq); + break; + case RKMODULE_SET_CSI_DPHY_PARAM: + dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL); + if (!dphy_param) { + ret = -ENOMEM; + return ret; + } + + ret = copy_from_user(dphy_param, up, sizeof(*dphy_param)); + if (!ret) + ret = lt8668sx_ioctl(sd, cmd, dphy_param); + else + ret = -EFAULT; + kfree(dphy_param); + break; + case RKMODULE_GET_CSI_DPHY_PARAM: + dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL); + if (!dphy_param) { + ret = -ENOMEM; + return ret; + } + + ret = lt8668sx_ioctl(sd, cmd, dphy_param); + if (!ret) { + ret = copy_to_user(up, dphy_param, sizeof(*dphy_param)); + if (ret) + ret = -EFAULT; + } + kfree(dphy_param); + break; + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} +#endif + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API +static int lt8668sx_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + struct v4l2_mbus_framefmt *try_fmt = + v4l2_subdev_get_try_format(sd, fh->pad, 0); + const struct lt8668sx_mode *def_mode = <8668sx->support_modes[0]; + + mutex_lock(<8668sx->confctl_mutex); + /* Initialize try_fmt */ + try_fmt->width = def_mode->width; + try_fmt->height = def_mode->height; + try_fmt->code = lt8668sx->mbus_fmt_code; + try_fmt->field = V4L2_FIELD_NONE; + mutex_unlock(<8668sx->confctl_mutex); + + return 0; +} +#endif + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API +static const struct v4l2_subdev_internal_ops lt8668sx_internal_ops = { + .open = lt8668sx_open, +}; +#endif + +static const struct v4l2_subdev_core_ops lt8668sx_core_ops = { + .s_power = lt8668sx_s_power, + .interrupt_service_routine = lt8668sx_isr, + .subscribe_event = lt8668sx_subscribe_event, + .unsubscribe_event = v4l2_event_subdev_unsubscribe, + .ioctl = lt8668sx_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = lt8668sx_compat_ioctl32, +#endif +}; + +static const struct v4l2_subdev_video_ops lt8668sx_video_ops = { + .g_input_status = lt8668sx_g_input_status, + .s_dv_timings = lt8668sx_s_dv_timings, + .g_dv_timings = lt8668sx_g_dv_timings, + .query_dv_timings = lt8668sx_query_dv_timings, + .s_stream = lt8668sx_s_stream, + .g_frame_interval = lt8668sx_g_frame_interval, +}; + +static const struct v4l2_subdev_pad_ops lt8668sx_pad_ops = { + .enum_mbus_code = lt8668sx_enum_mbus_code, + .enum_frame_size = lt8668sx_enum_frame_sizes, + .enum_frame_interval = lt8668sx_enum_frame_interval, + .set_fmt = lt8668sx_set_fmt, + .get_fmt = lt8668sx_get_fmt, + .enum_dv_timings = lt8668sx_enum_dv_timings, + .dv_timings_cap = lt8668sx_dv_timings_cap, + .get_mbus_config = lt8668sx_g_mbus_config, +}; + +static const struct v4l2_subdev_ops lt8668sx_ops = { + .core = <8668sx_core_ops, + .video = <8668sx_video_ops, + .pad = <8668sx_pad_ops, +}; + +static const struct v4l2_ctrl_config lt8668sx_ctrl_audio_sampling_rate = { + .id = RK_V4L2_CID_AUDIO_SAMPLING_RATE, + .name = "Audio sampling rate", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = 768000, + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_READ_ONLY, +}; + +static const struct v4l2_ctrl_config lt8668sx_ctrl_audio_present = { + .id = RK_V4L2_CID_AUDIO_PRESENT, + .name = "Audio present", + .type = V4L2_CTRL_TYPE_BOOLEAN, + .min = 0, + .max = 1, + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_READ_ONLY, +}; + +static int lt8668sx_init_v4l2_ctrls(struct lt8668sx *lt8668sx) +{ + const struct lt8668sx_mode *mode; + struct v4l2_subdev *sd; + int ret; + + mode = lt8668sx->cur_mode; + sd = <8668sx->sd; + ret = v4l2_ctrl_handler_init(<8668sx->hdl, 5); + if (ret) + return ret; + if (lt8668sx->bus_cfg.bus_type == V4L2_MBUS_CSI2_DPHY && + lt8668sx->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_2X8) + lt8668sx->link_freq = v4l2_ctrl_new_int_menu(<8668sx->hdl, NULL, + V4L2_CID_LINK_FREQ, + ARRAY_SIZE(link_freq_dphy_menu_items) - 1, 0, + link_freq_dphy_menu_items); + else if (lt8668sx->bus_cfg.bus_type != V4L2_MBUS_CSI2_DPHY && + lt8668sx->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_2X8) + lt8668sx->link_freq = v4l2_ctrl_new_int_menu(<8668sx->hdl, NULL, + V4L2_CID_LINK_FREQ, + ARRAY_SIZE(link_freq_cphy_menu_items) - 1, 0, + link_freq_cphy_menu_items); + else + lt8668sx->link_freq = v4l2_ctrl_new_int_menu(<8668sx->hdl, NULL, + V4L2_CID_LINK_FREQ, + ARRAY_SIZE(link_freq_cphy_rgb_menu_items) - 1, 0, + link_freq_cphy_rgb_menu_items); + + lt8668sx->pixel_rate = v4l2_ctrl_new_std(<8668sx->hdl, NULL, + V4L2_CID_PIXEL_RATE, + 0, LT8668SX_PIXEL_RATE, 1, LT8668SX_PIXEL_RATE); + + lt8668sx->detect_tx_5v_ctrl = v4l2_ctrl_new_std(<8668sx->hdl, + NULL, V4L2_CID_DV_RX_POWER_PRESENT, + 0, 1, 0, 0); + + lt8668sx->audio_sampling_rate_ctrl = + v4l2_ctrl_new_custom(<8668sx->hdl, + <8668sx_ctrl_audio_sampling_rate, NULL); + lt8668sx->audio_present_ctrl = v4l2_ctrl_new_custom(<8668sx->hdl, + <8668sx_ctrl_audio_present, NULL); + + sd->ctrl_handler = <8668sx->hdl; + if (lt8668sx->hdl.error) { + ret = lt8668sx->hdl.error; + v4l2_err(sd, "cfg v4l2 ctrls failed! ret:%d\n", ret); + return ret; + } + + __v4l2_ctrl_s_ctrl(lt8668sx->link_freq, mode->mipi_freq_idx); + __v4l2_ctrl_s_ctrl_int64(lt8668sx->pixel_rate, LT8668SX_PIXEL_RATE); + + if (lt8668sx_update_controls(sd)) { + ret = -ENODEV; + v4l2_err(sd, "update v4l2 ctrls failed! ret:%d\n", ret); + return ret; + } + + return 0; +} + +#ifdef CONFIG_OF +static int lt8668sx_probe_of(struct lt8668sx *lt8668sx) +{ + struct device *dev = <8668sx->i2c_client->dev; + struct device_node *node = dev->of_node; + struct device_node *ep; + int ret; + + ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX, + <8668sx->module_index); + ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING, + <8668sx->module_facing); + ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME, + <8668sx->module_name); + ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME, + <8668sx->len_name); + if (ret) { + dev_err(dev, "could not get module information!\n"); + return -EINVAL; + } + + if (of_property_read_bool(dev->of_node, "output-rgb")) + lt8668sx->mbus_fmt_code = MEDIA_BUS_FMT_BGR888_1X24; + + lt8668sx->power_gpio = devm_gpiod_get_optional(dev, "power", + GPIOD_OUT_LOW); + if (IS_ERR(lt8668sx->power_gpio)) { + dev_err(dev, "failed to get power gpio\n"); + ret = PTR_ERR(lt8668sx->power_gpio); + return ret; + } + + lt8668sx->reset_gpio = devm_gpiod_get_optional(dev, "reset", + GPIOD_OUT_HIGH); + if (IS_ERR(lt8668sx->reset_gpio)) { + dev_err(dev, "failed to get reset gpio\n"); + ret = PTR_ERR(lt8668sx->reset_gpio); + return ret; + } + + lt8668sx->plugin_det_gpio = devm_gpiod_get_optional(dev, "plugin-det", + GPIOD_IN); + if (IS_ERR(lt8668sx->plugin_det_gpio)) { + dev_err(dev, "failed to get plugin det gpio\n"); + ret = PTR_ERR(lt8668sx->plugin_det_gpio); + return ret; + } + + ep = of_graph_get_next_endpoint(dev->of_node, NULL); + if (!ep) { + dev_err(dev, "missing endpoint node\n"); + return -EINVAL; + } + + ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), + <8668sx->bus_cfg); + if (ret) { + dev_err(dev, "failed to parse endpoint\n"); + goto put_node; + } + + if (lt8668sx->bus_cfg.bus_type == V4L2_MBUS_CSI2_DPHY) { + lt8668sx->support_modes = supported_modes_dphy; + lt8668sx->cfg_num = ARRAY_SIZE(supported_modes_dphy); + } else { + lt8668sx->support_modes = supported_modes_cphy; + lt8668sx->cfg_num = ARRAY_SIZE(supported_modes_cphy); + } + + lt8668sx->xvclk = devm_clk_get(dev, "xvclk"); + if (IS_ERR(lt8668sx->xvclk)) { + dev_err(dev, "failed to get xvclk\n"); + ret = -EINVAL; + goto put_node; + } + + ret = clk_prepare_enable(lt8668sx->xvclk); + if (ret) { + dev_err(dev, "Failed! to enable xvclk\n"); + goto put_node; + } + + lt8668sx->enable_hdcp = false; + + ret = 0; + +put_node: + of_node_put(ep); + return ret; +} +#else +static inline int lt8668sx_probe_of(struct lt8668sx *state) +{ + return -ENODEV; +} +#endif + +static int __lt8668sx_power_on(struct lt8668sx *lt8668sx) +{ + struct device *dev = <8668sx->i2c_client->dev; + + dev_info(dev, "lt8668sx power on\n"); + gpiod_set_value(lt8668sx->reset_gpio, 1); + usleep_range(20000, 25000); + gpiod_set_value(lt8668sx->power_gpio, 1); + //delay 20ms before reset + usleep_range(25000, 30000); + gpiod_set_value(lt8668sx->reset_gpio, 0); + usleep_range(25000, 30000); + + return 0; +} + +static void __lt8668sx_power_off(struct lt8668sx *lt8668sx) +{ + struct device *dev = <8668sx->i2c_client->dev; + + dev_info(dev, "lt8668sx power off\n"); + + if (!IS_ERR(lt8668sx->reset_gpio)) + gpiod_set_value(lt8668sx->reset_gpio, 1); + + if (!IS_ERR(lt8668sx->power_gpio)) + gpiod_set_value(lt8668sx->power_gpio, 0); +} + +static int lt8668sx_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + + return __lt8668sx_power_on(lt8668sx); +} + +static int lt8668sx_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + + __lt8668sx_power_off(lt8668sx); + + return 0; +} + +static const struct dev_pm_ops lt8668sx_pm_ops = { + .suspend = lt8668sx_suspend, + .resume = lt8668sx_resume, +}; + +static int lt8668sx_check_chip_id(struct lt8668sx *lt8668sx) +{ + struct device *dev = <8668sx->i2c_client->dev; + struct v4l2_subdev *sd = <8668sx->sd; + u8 id_h, id_l; + u32 chipid; + int ret = 0; + + lt8668sx_i2c_enable(sd); + id_l = i2c_rd8(sd, CHIPID_REGL); + id_h = i2c_rd8(sd, CHIPID_REGH); + lt8668sx_i2c_disable(sd); + + chipid = (id_h << 8) | id_l; + if (chipid != LT8668SX_CHIPID) { + dev_err(dev, "chipid err, read:%#x, expect:%#x\n", + chipid, LT8668SX_CHIPID); + return -EINVAL; + } + dev_info(dev, "check chipid ok, id:%#x", chipid); + + return ret; +} + +static int lt8668sx_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct v4l2_dv_timings default_timing = + V4L2_DV_BT_CEA_640X480P59_94; + struct lt8668sx *lt8668sx; + struct v4l2_subdev *sd; + struct device *dev = &client->dev; + char facing[2]; + int err; + + dev_info(dev, "driver version: %02x.%02x.%02x", + DRIVER_VERSION >> 16, + (DRIVER_VERSION & 0xff00) >> 8, + DRIVER_VERSION & 0x00ff); + + lt8668sx = devm_kzalloc(dev, sizeof(struct lt8668sx), GFP_KERNEL); + if (!lt8668sx) + return -ENOMEM; + + sd = <8668sx->sd; + lt8668sx->i2c_client = client; + lt8668sx->mbus_fmt_code = MEDIA_BUS_FMT_UYVY8_2X8; + + err = lt8668sx_probe_of(lt8668sx); + if (err) { + v4l2_err(sd, "lt8668sx_parse_of failed! err:%d\n", err); + return err; + } + + lt8668sx->timings = default_timing; + lt8668sx->cur_mode = <8668sx->support_modes[0]; + + __lt8668sx_power_on(lt8668sx); + err = lt8668sx_check_chip_id(lt8668sx); + if (err < 0) + return err; + + INIT_DELAYED_WORK(<8668sx->delayed_work_hotplug, + lt8668sx_delayed_work_hotplug); + INIT_DELAYED_WORK(<8668sx->delayed_work_res_change, + lt8668sx_delayed_work_res_change); + + if (lt8668sx->i2c_client->irq) { + v4l2_dbg(1, debug, sd, "cfg lt8668sx irq!\n"); + err = devm_request_threaded_irq(dev, + lt8668sx->i2c_client->irq, + NULL, lt8668sx_res_change_irq_handler, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + "lt8668sx", lt8668sx); + if (err) { + v4l2_err(sd, "request irq failed! err:%d\n", err); + goto err_work_queues; + } + } else { + v4l2_info(sd, "no irq, cfg poll!\n"); + INIT_WORK(<8668sx->work_i2c_poll, lt8668sx_work_i2c_poll); + timer_setup(<8668sx->timer, lt8668sx_irq_poll_timer, 0); + lt8668sx->timer.expires = jiffies + + msecs_to_jiffies(POLL_INTERVAL_MS); + add_timer(<8668sx->timer); + } + + lt8668sx->plugin_irq = gpiod_to_irq(lt8668sx->plugin_det_gpio); + if (lt8668sx->plugin_irq < 0) + dev_err(dev, "failed to get plugin det irq, maybe no use\n"); + + err = devm_request_threaded_irq(dev, lt8668sx->plugin_irq, NULL, + plugin_detect_irq_handler, IRQF_TRIGGER_FALLING | + IRQF_TRIGGER_RISING | IRQF_ONESHOT, "lt8668sx", + lt8668sx); + if (err) + dev_err(dev, "failed to register plugin det irq (%d), maybe no use\n", err); + + mutex_init(<8668sx->confctl_mutex); + err = lt8668sx_init_v4l2_ctrls(lt8668sx); + if (err) + goto err_free_hdl; + + client->flags |= I2C_CLIENT_SCCB; +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + v4l2_i2c_subdev_init(sd, client, <8668sx_ops); + sd->internal_ops = <8668sx_internal_ops; + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; +#endif + +#if defined(CONFIG_MEDIA_CONTROLLER) + lt8668sx->pad.flags = MEDIA_PAD_FL_SOURCE; + sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; + err = media_entity_pads_init(&sd->entity, 1, <8668sx->pad); + if (err < 0) { + v4l2_err(sd, "media entity init failed! err:%d\n", err); + goto err_free_hdl; + } +#endif + memset(facing, 0, sizeof(facing)); + if (strcmp(lt8668sx->module_facing, "back") == 0) + facing[0] = 'b'; + else + facing[0] = 'f'; + + snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s", + lt8668sx->module_index, facing, + LT8668SX_NAME, dev_name(sd->dev)); + err = v4l2_async_register_subdev_sensor_common(sd); + if (err < 0) { + v4l2_err(sd, "v4l2 register subdev failed! err:%d\n", err); + goto err_clean_entity; + } + + err = v4l2_ctrl_handler_setup(sd->ctrl_handler); + if (err) { + v4l2_err(sd, "v4l2 ctrl handler setup failed! err:%d\n", err); + goto err_clean_entity; + } + + schedule_delayed_work(<8668sx->delayed_work_res_change, 100); + + v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, + client->addr << 1, client->adapter->name); + + return 0; + +err_clean_entity: +#if defined(CONFIG_MEDIA_CONTROLLER) + media_entity_cleanup(&sd->entity); +#endif +err_free_hdl: + v4l2_ctrl_handler_free(<8668sx->hdl); + mutex_destroy(<8668sx->confctl_mutex); +err_work_queues: + if (!lt8668sx->i2c_client->irq) + flush_work(<8668sx->work_i2c_poll); + cancel_delayed_work(<8668sx->delayed_work_hotplug); + cancel_delayed_work(<8668sx->delayed_work_res_change); + + return err; +} + +static int lt8668sx_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct lt8668sx *lt8668sx = to_lt8668sx(sd); + + if (!lt8668sx->i2c_client->irq) { + del_timer_sync(<8668sx->timer); + flush_work(<8668sx->work_i2c_poll); + } + cancel_delayed_work_sync(<8668sx->delayed_work_hotplug); + cancel_delayed_work_sync(<8668sx->delayed_work_res_change); + v4l2_async_unregister_subdev(sd); + v4l2_device_unregister_subdev(sd); +#if defined(CONFIG_MEDIA_CONTROLLER) + media_entity_cleanup(&sd->entity); +#endif + v4l2_ctrl_handler_free(<8668sx->hdl); + mutex_destroy(<8668sx->confctl_mutex); + clk_disable_unprepare(lt8668sx->xvclk); + + return 0; +} + +#if IS_ENABLED(CONFIG_OF) +static const struct of_device_id lt8668sx_of_match[] = { + { .compatible = "lontium,lt8668sx" }, + {}, +}; +MODULE_DEVICE_TABLE(of, lt8668sx_of_match); +#endif + +static struct i2c_driver lt8668sx_driver = { + .driver = { + .name = LT8668SX_NAME, + .pm = <8668sx_pm_ops, + .of_match_table = of_match_ptr(lt8668sx_of_match), + }, + .probe = lt8668sx_probe, + .remove = lt8668sx_remove, +}; + +static int __init lt8668sx_driver_init(void) +{ + return i2c_add_driver(<8668sx_driver); +} + +static void __exit lt8668sx_driver_exit(void) +{ + i2c_del_driver(<8668sx_driver); +} + +device_initcall_sync(lt8668sx_driver_init); +module_exit(lt8668sx_driver_exit); + +MODULE_DESCRIPTION("Lontium lt8668sx HDMI to CSI-2 bridge driver"); +MODULE_AUTHOR("Jianwei Fan "); +MODULE_LICENSE("GPL"); From 14119c4f7f1f97c9c54d48aa86fad52e74b14c6f Mon Sep 17 00:00:00 2001 From: Jiahang Zheng Date: Fri, 29 Dec 2023 10:21:56 +0800 Subject: [PATCH 14/22] arm64: dts: rockchip: rk3562-amp: change mcu ram address Change-Id: If7311abee120fef2a0259845e202612f8c67372a Signed-off-by: Jiahang Zheng --- arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi index 0cf505c7ee30..e2872709e2b7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi @@ -29,7 +29,13 @@ /* remote amp core address */ amp_shmem_reserved: amp-shmem@7800000 { - reg = <0x0 0x7800000 0x0 0x400000>; + reg = <0x0 0x7800000 0x0 0x300000>; + no-map; + }; + + /* mcu address */ + mcu_reserved: mcu@7b00000 { + reg = <0x0 0x7b00000 0x0 0x100000>; no-map; }; @@ -43,13 +49,6 @@ reg = <0x0 0x08000000 0x0 0x100000>; no-map; }; - - /* mcu address */ - mcu_reserved: mcu@8200000 { - reg = <0x0 0x8200000 0x0 0x100000>; - no-map; - }; - }; rpmsg: rpmsg@7c00000 { From c08e952374eb2dcd2e6dc3b7d06cd3dfa80ccac7 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Thu, 21 Dec 2023 18:47:21 +0800 Subject: [PATCH 15/22] mtd: spinand: XINCUN: Support new device XCSP1AAPK Change-Id: Ia8de254547f40499a501e20421efb0f443842b87 Signed-off-by: Jon Lin --- drivers/mtd/nand/spi/xincun.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mtd/nand/spi/xincun.c b/drivers/mtd/nand/spi/xincun.c index 8920a5923f2c..ac4dd8dde2ca 100644 --- a/drivers/mtd/nand/spi/xincun.c +++ b/drivers/mtd/nand/spi/xincun.c @@ -92,6 +92,15 @@ static const struct spinand_info xincun_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&xcsp2aapk_ooblayout, xcsp2aapk_ecc_get_status)), + SPINAND_INFO("XCSP1AAPK", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x01), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&xcsp2aapk_ooblayout, xcsp2aapk_ecc_get_status)), }; static const struct spinand_manufacturer_ops xincun_spinand_manuf_ops = { From 1bbb5589669037fed2dee3bdc2ef346c74a4c69f Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Tue, 2 Jan 2024 15:09:57 +0800 Subject: [PATCH 16/22] dmaengine: pl330: Use tasklet_hi_schedule Use tasklet_hi_schedule for better audio performance, especially for LLA (Low Latency Audio) situation. Signed-off-by: Sugar Zhang Change-Id: Ic5a215a269e718b0e5613132cb9fe9b58940d0e1 --- drivers/dma/pl330.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c index 0d14147abd4c..37c288da94c3 100644 --- a/drivers/dma/pl330.c +++ b/drivers/dma/pl330.c @@ -1760,7 +1760,7 @@ static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err) spin_unlock_irqrestore(&pch->lock, flags); - tasklet_schedule(&pch->task); + tasklet_hi_schedule(&pch->task); } static void pl330_dotask(struct tasklet_struct *t) From 5e9dee2ebe5c633887ee7d8f695259a7b5445b71 Mon Sep 17 00:00:00 2001 From: LongChang Ma Date: Thu, 28 Dec 2023 09:42:41 +0800 Subject: [PATCH 17/22] media: i2c: add sc830ai sensor driver Signed-off-by: LongChang Ma Change-Id: Ib22fb1d354cbb3ee26f5a94c969675cbb28990ff --- drivers/media/i2c/Kconfig | 10 + drivers/media/i2c/Makefile | 1 + drivers/media/i2c/sc830ai.c | 1930 +++++++++++++++++++++++++++++++++++ 3 files changed, 1941 insertions(+) create mode 100644 drivers/media/i2c/sc830ai.c diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 6b79fa863217..9966255e68fa 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -2282,6 +2282,16 @@ config VIDEO_SC5336 This is a Video4Linux2 sensor driver for the SmartSens SC5336 camera. +config VIDEO_SC830AI + tristate "SmartSens SC830AI sensor support" + depends on I2C && VIDEO_V4L2 + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the SmartSens + SC830AI camera. + config VIDEO_SC850SL tristate "SmartSens SC850SL sensor support" depends on I2C && VIDEO_V4L2 diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index 9046d5331b77..68d2fbacfff9 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -159,6 +159,7 @@ obj-$(CONFIG_VIDEO_SC500AI) += sc500ai.o obj-$(CONFIG_VIDEO_SC501AI) += sc501ai.o obj-$(CONFIG_VIDEO_SC530AI) += sc530ai.o obj-$(CONFIG_VIDEO_SC5336) += sc5336.o +obj-$(CONFIG_VIDEO_SC830AI) += sc830ai.o obj-$(CONFIG_VIDEO_SC850SL) += sc850sl.o obj-$(CONFIG_VIDEO_SENSOR_ADAPTER) += sensor_adapter.o obj-$(CONFIG_VIDEO_SR030PC30) += sr030pc30.o diff --git a/drivers/media/i2c/sc830ai.c b/drivers/media/i2c/sc830ai.c new file mode 100644 index 000000000000..45ae86f1cbfd --- /dev/null +++ b/drivers/media/i2c/sc830ai.c @@ -0,0 +1,1930 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * sc830ai driver + * + * Copyright (C) 2023 Rockchip Electronics Co., Ltd. + * + * V0.0X01.0X01 first version + */ + +//#define DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../platform/rockchip/isp/rkisp_tb_helper.h" + +#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01) + +#ifndef V4L2_CID_DIGITAL_GAIN +#define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN +#endif + +#define MIPI_FREQ_405M 405000000 // 910Mbps + +#define SC830AI_MAX_PIXEL_RATE (MIPI_FREQ_405M / 10 * 2 * SC830AI_2LANES) +#define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode" + +#define SC830AI_XVCLK_FREQ 24000000 + +/* TODO: Get the real chip id from reg */ +#define CHIP_ID 0xC143 +#define SC830AI_REG_CHIP_ID 0x3107 + +#define SC830AI_REG_CTRL_MODE 0x0100 +#define SC830AI_MODE_SW_STANDBY 0x0 +#define SC830AI_MODE_STREAMING BIT(0) + +/*expo*/ +#define SC830AI_EXPOSURE_MIN 2 /*okay*/ +#define SC830AI_EXPOSURE_STEP 1 /*okay*/ +#define SC830AI_VTS_MAX 0xffff /*okay*/ + +//long exposure +#define SC830AI_REG_EXP_LONG_H 0x3e00 //[3:0] +#define SC830AI_REG_EXP_LONG_M 0x3e01 //[7:0] +#define SC830AI_REG_EXP_LONG_L 0x3e02 //[7:4] + +//short exposure //for hdr +#define SC830AI_REG_EXP_SF_H 0x3e22 +#define SC830AI_REG_EXP_SF_M 0x3e04 //[7:0] +#define SC830AI_REG_EXP_SF_L 0x3e05 //[7:4] + +#define SC830AI_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF) +#define SC830AI_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF) +#define SC830AI_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4) + +/*gain*/ +//long frame and normal gain reg +#define SC830AI_REG_DGAIN 0x3e06 +#define SC830AI_REG_DGAIN_FINE 0x3e07 +#define SC830AI_REG_AGAIN 0x3e09 + +//short frame gain reg +#define SC830AI_SF_REG_DGAIN 0x3e10 +#define SC830AI_SF_REG_DGAIN_FINE 0x3e11 +#define SC830AI_SF_REG_AGAIN 0x3e13 + +#define SC830AI_GAIN_MIN 0x20 //1.000 = 32 * 1/32 +#define SC830AI_GAIN_MAX (4032) /* need_view 3.938 * 32 * 32 = 4032.512 */ +#define SC830AI_GAIN_STEP 1 +#define SC830AI_GAIN_DEFAULT 0x20 + +#define SC830AI_REG_VTS 0x320e + +//group hold +#define SC830AI_GROUP_UPDATE_ADDRESS 0x3812 +#define SC830AI_GROUP_UPDATE_START_DATA 0x00 +#define SC830AI_GROUP_UPDATE_LAUNCH 0x30 +#define SC830AI_GROUP_DEALY_CTRL 0x3802 + +#define SC830AI_SOFTWARE_RESET_REG 0x0103 +#define SC830AI_REG_TEST_PATTERN 0x4501 +#define SC830AI_TEST_PATTERN_ENABLE 0x08 + +#define SC830AI_FLIP_REG 0x3221 +#define SC830AI_FLIP_MASK 0x60 +#define SC830AI_MIRROR_MASK 0x06 + +#define REG_NULL 0xFFFF + +#define SC830AI_REG_VALUE_08BIT 1 +#define SC830AI_REG_VALUE_16BIT 2 +#define SC830AI_REG_VALUE_24BIT 3 + +#define SC830AI_2LANES 2 +#define SC830AI_4LANES 4 + +#define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default" +#define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep" + +#define SC830AI_NAME "sc830ai" + +static const char * const sc830ai_supply_names[] = { + "dvdd", // Digital core power + "dovdd", // Digital I/O power + "avdd", // Analog power +}; +#define SC830AI_NUM_SUPPLIES ARRAY_SIZE(sc830ai_supply_names) + +struct regval { + u16 addr; + u8 val; +}; + +struct sc830ai_mode { + u32 bus_fmt; + u32 width; + u32 height; + struct v4l2_fract max_fps; + u32 hts_def; + u32 vts_def; + u32 exp_def; + u32 mipi_freq_idx; + u32 bpp; + const struct regval *reg_list; + u32 hdr_mode; + u32 vc[PAD_MAX]; +}; + +struct sc830ai { + struct i2c_client *client; + struct clk *xvclk; + struct gpio_desc *reset_gpio; + struct gpio_desc *pwdn_gpio; + struct regulator_bulk_data supplies[SC830AI_NUM_SUPPLIES]; + + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_sleep; + + struct v4l2_subdev subdev; + struct media_pad pad; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *exposure; + struct v4l2_ctrl *anal_a_gain; + struct v4l2_ctrl *digi_gain; + struct v4l2_ctrl *hblank; + struct v4l2_ctrl *vblank; + struct v4l2_ctrl *test_pattern; + struct v4l2_ctrl *pixel_rate; + struct v4l2_ctrl *link_freq; + struct mutex mutex; + struct v4l2_fract cur_fps; + bool streaming; + bool power_on; + bool is_first_streamoff; + const struct sc830ai_mode *cur_mode; + u32 module_index; + u32 cfg_num; + const char *module_facing; + const char *module_name; + const char *len_name; + u32 cur_vts; + bool has_init_exp; + struct preisp_hdrae_exp_s init_hdrae_exp; +}; + + +#define to_sc830ai(sd) container_of(sd, struct sc830ai, subdev) + +//cleaned_0x09_SC830AI_MIPI_24Minput_4lane_360Mbps_10bit_3840x2160_15fps.ini +static __maybe_unused const struct regval sc830ai_4lane_linear10bit_3840x2160_regs[] = { + {0x0103, 0x01}, + {0x0100, 0x00}, + {0x36e9, 0x80}, + {0x37f9, 0x80}, + {0x301f, 0x09}, + {0x320c, 0x08}, + {0x320d, 0x34}, + {0x320e, 0x08}, + {0x320f, 0xec}, + {0x3281, 0x80}, + {0x3301, 0x0e}, + {0x3303, 0x18}, + {0x3306, 0x50}, + {0x3308, 0x20}, + {0x330a, 0x00}, + {0x330b, 0xd8}, + {0x330c, 0x20}, + {0x330e, 0x40}, + {0x330f, 0x08}, + {0x3314, 0x16}, + {0x3317, 0x07}, + {0x3319, 0x0c}, + {0x3321, 0x0c}, + {0x3324, 0x09}, + {0x3325, 0x09}, + {0x3327, 0x16}, + {0x3328, 0x10}, + {0x3329, 0x1c}, + {0x332b, 0x0d}, + {0x3333, 0x10}, + {0x333e, 0x0e}, + {0x3352, 0x0c}, + {0x3353, 0x0c}, + {0x335e, 0x06}, + {0x335f, 0x08}, + {0x3364, 0x5e}, + {0x3366, 0x01}, + {0x337c, 0x02}, + {0x337d, 0x0a}, + {0x3390, 0x01}, + {0x3391, 0x0b}, + {0x3392, 0x1f}, + {0x3393, 0x0e}, + {0x3394, 0x30}, + {0x3395, 0x30}, + {0x3396, 0x01}, + {0x3397, 0x0b}, + {0x3398, 0x1f}, + {0x3399, 0x0e}, + {0x339a, 0x0e}, + {0x339b, 0x30}, + {0x339c, 0x30}, + {0x339f, 0x0e}, + {0x33a2, 0x04}, + {0x33ad, 0x3c}, + {0x33af, 0x68}, + {0x33b1, 0x80}, + {0x33b2, 0x58}, + {0x33b3, 0x40}, + {0x33ba, 0x0c}, + {0x33f9, 0x80}, + {0x33fb, 0xa0}, + {0x33fc, 0x4b}, + {0x33fd, 0x5f}, + {0x349f, 0x03}, + {0x34a0, 0x0e}, + {0x34a6, 0x4b}, + {0x34a7, 0x5f}, + {0x34a8, 0x20}, + {0x34a9, 0x10}, + {0x34aa, 0x01}, + {0x34ab, 0x10}, + {0x34ac, 0x01}, + {0x34ad, 0x28}, + {0x34f8, 0x5f}, + {0x34f9, 0x10}, + {0x3630, 0xc8}, + {0x3632, 0x46}, + {0x3633, 0x33}, + {0x3637, 0x24}, + {0x3638, 0xc3}, + {0x363c, 0x40}, + {0x363d, 0x40}, + {0x363e, 0x70}, + {0x3670, 0x01}, + {0x3674, 0xc6}, + {0x3675, 0x8c}, + {0x3676, 0x8c}, + {0x367c, 0x4b}, + {0x367d, 0x5f}, + {0x3698, 0x82}, + {0x3699, 0x8d}, + {0x369a, 0x9c}, + {0x369b, 0xba}, + {0x369e, 0xba}, + {0x369f, 0xba}, + {0x36a2, 0x49}, + {0x36a3, 0x4b}, + {0x36a4, 0x4f}, + {0x36a5, 0x5f}, + {0x36a6, 0x5f}, + {0x36d0, 0x01}, + {0x36ea, 0x08}, + {0x36eb, 0x14}, + {0x36ec, 0x03}, + {0x36ed, 0x22}, + {0x370f, 0x01}, + {0x3721, 0x9c}, + {0x3722, 0x03}, + {0x3724, 0x31}, + {0x37b0, 0x03}, + {0x37b1, 0x03}, + {0x37b2, 0x03}, + {0x37b3, 0x4b}, + {0x37b4, 0x4f}, + {0x37fa, 0x08}, + {0x37fb, 0x31}, + {0x37fc, 0x10}, + {0x37fd, 0x04}, + {0x3903, 0x40}, + {0x3905, 0x4c}, + {0x391e, 0x09}, + {0x3929, 0x18}, + {0x3933, 0x80}, + {0x3934, 0x03}, + {0x3935, 0x00}, + {0x3936, 0x34}, + {0x3937, 0x6a}, + {0x3938, 0x69}, + {0x3e00, 0x01}, + {0x3e01, 0x1c}, + {0x3e02, 0x60}, + {0x3e09, 0x40}, + {0x440e, 0x02}, + {0x4837, 0x2c}, + {0x5010, 0x01}, + {0x5799, 0x77}, + {0x57aa, 0xeb}, + {0x57d9, 0x00}, + {0x5ae0, 0xfe}, + {0x5ae1, 0x40}, + {0x5ae2, 0x38}, + {0x5ae3, 0x30}, + {0x5ae4, 0x28}, + {0x5ae5, 0x38}, + {0x5ae6, 0x30}, + {0x5ae7, 0x28}, + {0x5ae8, 0x3f}, + {0x5ae9, 0x34}, + {0x5aea, 0x2c}, + {0x5aeb, 0x3f}, + {0x5aec, 0x34}, + {0x5aed, 0x2c}, + {0x5aee, 0xfe}, + {0x5aef, 0x40}, + {0x5af4, 0x38}, + {0x5af5, 0x30}, + {0x5af6, 0x28}, + {0x5af7, 0x38}, + {0x5af8, 0x30}, + {0x5af9, 0x28}, + {0x5afa, 0x3f}, + {0x5afb, 0x34}, + {0x5afc, 0x2c}, + {0x5afd, 0x3f}, + {0x5afe, 0x34}, + {0x5aff, 0x2c}, + {0x5f00, 0x05}, + {0x36e9, 0x53}, + {0x37f9, 0x27}, + // {0x0100, 0x01}, + {REG_NULL, 0x00}, +}; + +//cleaned_0x09_SC830AI_MIPI_24Minput_2lane_360Mbps_10bit_3840x2160_15fps.ini +static __maybe_unused const struct regval sc830ai_2lane_linear10bit_3840x2160_regs[] = { + {0x0103, 0x01}, + {0x0100, 0x00}, + {0x36e9, 0x80}, + {0x37f9, 0x80}, + {0x3018, 0x32}, + {0x3019, 0x0c}, + {0x301f, 0x07}, + {0x320c, 0x09}, + {0x320d, 0x60}, + {0x3281, 0x80}, + {0x3301, 0x0e}, + {0x3303, 0x18}, + {0x3306, 0x50}, + {0x3308, 0x20}, + {0x330a, 0x00}, + {0x330b, 0xd8}, + {0x330c, 0x20}, + {0x330e, 0x40}, + {0x330f, 0x08}, + {0x3314, 0x16}, + {0x3317, 0x07}, + {0x3319, 0x0c}, + {0x3321, 0x0c}, + {0x3324, 0x09}, + {0x3325, 0x09}, + {0x3327, 0x16}, + {0x3328, 0x10}, + {0x3329, 0x1c}, + {0x332b, 0x0d}, + {0x3333, 0x10}, + {0x333e, 0x0e}, + {0x3352, 0x0c}, + {0x3353, 0x0c}, + {0x335e, 0x06}, + {0x335f, 0x08}, + {0x3364, 0x5e}, + {0x3366, 0x01}, + {0x337c, 0x02}, + {0x337d, 0x0a}, + {0x3390, 0x01}, + {0x3391, 0x0b}, + {0x3392, 0x1f}, + {0x3393, 0x0e}, + {0x3394, 0x30}, + {0x3395, 0x30}, + {0x3396, 0x01}, + {0x3397, 0x0b}, + {0x3398, 0x1f}, + {0x3399, 0x0e}, + {0x339a, 0x0e}, + {0x339b, 0x30}, + {0x339c, 0x30}, + {0x339f, 0x0e}, + {0x33a2, 0x04}, + {0x33ad, 0x3c}, + {0x33af, 0x68}, + {0x33b1, 0x80}, + {0x33b2, 0x58}, + {0x33b3, 0x40}, + {0x33ba, 0x0c}, + {0x33f9, 0x80}, + {0x33fb, 0xa0}, + {0x33fc, 0x4b}, + {0x33fd, 0x5f}, + {0x349f, 0x03}, + {0x34a0, 0x0e}, + {0x34a6, 0x4b}, + {0x34a7, 0x5f}, + {0x34a8, 0x20}, + {0x34a9, 0x10}, + {0x34aa, 0x01}, + {0x34ab, 0x10}, + {0x34ac, 0x01}, + {0x34ad, 0x28}, + {0x34f8, 0x5f}, + {0x34f9, 0x10}, + {0x3630, 0xc8}, + {0x3632, 0x46}, + {0x3633, 0x33}, + {0x3637, 0x24}, + {0x3638, 0xc3}, + {0x363c, 0x40}, + {0x363d, 0x40}, + {0x363e, 0x70}, + {0x3670, 0x01}, + {0x3674, 0xc6}, + {0x3675, 0x8c}, + {0x3676, 0x8c}, + {0x367c, 0x4b}, + {0x367d, 0x5f}, + {0x3698, 0x82}, + {0x3699, 0x8d}, + {0x369a, 0x9c}, + {0x369b, 0xba}, + {0x369e, 0xba}, + {0x369f, 0xba}, + {0x36a2, 0x49}, + {0x36a3, 0x4b}, + {0x36a4, 0x4f}, + {0x36a5, 0x5f}, + {0x36a6, 0x5f}, + {0x36d0, 0x01}, + {0x36ea, 0x09}, + {0x36eb, 0x04}, + {0x36ec, 0x03}, + {0x36ed, 0x22}, + {0x370f, 0x01}, + {0x3721, 0x9c}, + {0x3722, 0x03}, + {0x3724, 0x31}, + {0x37b0, 0x03}, + {0x37b1, 0x03}, + {0x37b2, 0x03}, + {0x37b3, 0x4b}, + {0x37b4, 0x4f}, + {0x37fa, 0x09}, + {0x37fb, 0x31}, + {0x37fc, 0x10}, + {0x37fd, 0x14}, + {0x3903, 0x40}, + {0x3905, 0x4c}, + {0x391e, 0x09}, + {0x3929, 0x18}, + {0x3933, 0x80}, + {0x3934, 0x03}, + {0x3935, 0x00}, + {0x3936, 0x34}, + {0x3937, 0x6a}, + {0x3938, 0x69}, + {0x3e00, 0x01}, + {0x3e01, 0x18}, + {0x3e09, 0x40}, + {0x440e, 0x02}, + {0x4837, 0x14}, + {0x5010, 0x01}, + {0x5799, 0x77}, + {0x57aa, 0xeb}, + {0x57d9, 0x00}, + {0x5ae0, 0xfe}, + {0x5ae1, 0x40}, + {0x5ae2, 0x38}, + {0x5ae3, 0x30}, + {0x5ae4, 0x28}, + {0x5ae5, 0x38}, + {0x5ae6, 0x30}, + {0x5ae7, 0x28}, + {0x5ae8, 0x3f}, + {0x5ae9, 0x34}, + {0x5aea, 0x2c}, + {0x5aeb, 0x3f}, + {0x5aec, 0x34}, + {0x5aed, 0x2c}, + {0x5aee, 0xfe}, + {0x5aef, 0x40}, + {0x5af4, 0x38}, + {0x5af5, 0x30}, + {0x5af6, 0x28}, + {0x5af7, 0x38}, + {0x5af8, 0x30}, + {0x5af9, 0x28}, + {0x5afa, 0x3f}, + {0x5afb, 0x34}, + {0x5afc, 0x2c}, + {0x5afd, 0x3f}, + {0x5afe, 0x34}, + {0x5aff, 0x2c}, + {0x5f00, 0x05}, + {0x36e9, 0x53}, + {0x37f9, 0x53}, + // {0x0100, 0x01}, + {REG_NULL, 0x00}, +}; + +/* + * The width and height must be configured to be + * the same as the current output resolution of the sensor. + * The input width of the isp needs to be 16 aligned. + * The input height of the isp needs to be 8 aligned. + * If the width or height does not meet the alignment rules, + * you can configure the cropping parameters with the following function to + * crop out the appropriate resolution. + * struct v4l2_subdev_pad_ops { + * .get_selection + * } + */ +static const struct sc830ai_mode supported_modes[] = { + { + .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10, + .width = 3840, + .height = 2160, + .max_fps = { + .numerator = 10000, + .denominator = 150000, + }, + .exp_def = 0x08c0, + .hts_def = 0x0226*5-0x180, + .vts_def = 0x08ca, + .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10, + .reg_list = sc830ai_2lane_linear10bit_3840x2160_regs, + .hdr_mode = NO_HDR, + .mipi_freq_idx = 0, + .bpp = 10, + .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0, + }, +}; + +static const char * const sc830ai_test_pattern_menu[] = { + "Disabled", + "Vertical Color Bar Type 1", + "Vertical Color Bar Type 2", + "Vertical Color Bar Type 3", + "Vertical Color Bar Type 4" +}; + +static const s64 link_freq_items[] = { + MIPI_FREQ_405M, +}; + +/* Write registers up to 4 at a time */ +static int sc830ai_write_reg(struct i2c_client *client, u16 reg, + u32 len, u32 val) +{ + u32 buf_i, val_i; + u8 buf[6]; + u8 *val_p; + __be32 val_be; + + if (len > 4) + return -EINVAL; + + buf[0] = reg >> 8; + buf[1] = reg & 0xff; + + val_be = cpu_to_be32(val); + val_p = (u8 *)&val_be; + buf_i = 2; + val_i = 4 - len; + + while (val_i < 4) + buf[buf_i++] = val_p[val_i++]; + + if (i2c_master_send(client, buf, len + 2) != len + 2) + return -EIO; + + return 0; +} + +static int sc830ai_write_array(struct i2c_client *client, + const struct regval *regs) +{ + u32 i; + int ret = 0; + + for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) { + ret = sc830ai_write_reg(client, regs[i].addr, + SC830AI_REG_VALUE_08BIT, regs[i].val); + } + return ret; +} + +/* Read registers up to 4 at a time */ +static int sc830ai_read_reg(struct i2c_client *client, u16 reg, unsigned int len, + u32 *val) +{ + struct i2c_msg msgs[2]; + u8 *data_be_p; + __be32 data_be = 0; + __be16 reg_addr_be = cpu_to_be16(reg); + int ret; + + if (len > 4 || !len) + return -EINVAL; + + data_be_p = (u8 *)&data_be; + /* Write register address */ + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = 2; + msgs[0].buf = (u8 *)®_addr_be; + + /* Read data from register */ + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = len; + msgs[1].buf = &data_be_p[4 - len]; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) + return -EIO; + + *val = be32_to_cpu(data_be); + + return 0; +} + +static int sc830ai_get_reso_dist(const struct sc830ai_mode *mode, + struct v4l2_mbus_framefmt *framefmt) +{ + return abs(mode->width - framefmt->width) + + abs(mode->height - framefmt->height); +} + +static const struct sc830ai_mode * +sc830ai_find_best_fit(struct sc830ai *sc830ai, struct v4l2_subdev_format *fmt) +{ + struct v4l2_mbus_framefmt *framefmt = &fmt->format; + int dist; + int cur_best_fit = 0; + int cur_best_fit_dist = -1; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + dist = sc830ai_get_reso_dist(&supported_modes[i], framefmt); + if ((cur_best_fit_dist == -1 || dist < cur_best_fit_dist) && + supported_modes[i].bus_fmt == framefmt->code) { + cur_best_fit_dist = dist; + cur_best_fit = i; + } + } + dev_info(&sc830ai->client->dev, "%s: cur_best_fit(%d)", + __func__, cur_best_fit); + + return &supported_modes[cur_best_fit]; +} + +static void sc830ai_change_mode(struct sc830ai *sc830ai, const struct sc830ai_mode *mode) +{ + sc830ai->cur_mode = mode; + sc830ai->cur_vts = sc830ai->cur_mode->vts_def; + dev_info(&sc830ai->client->dev, "set fmt: cur_mode: %dx%d, hdr: %d\n", + mode->width, mode->height, mode->hdr_mode); +} + +static int sc830ai_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct sc830ai *sc830ai = to_sc830ai(sd); + const struct sc830ai_mode *mode; + s64 h_blank, vblank_def; + u64 pixel_rate = 0; + + mutex_lock(&sc830ai->mutex); + + mode = sc830ai_find_best_fit(sc830ai, fmt); + fmt->format.code = mode->bus_fmt; + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.field = V4L2_FIELD_NONE; + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format; +#else + mutex_unlock(&sc830ai->mutex); + return -ENOTTY; +#endif + } else { + sc830ai_change_mode(sc830ai, mode); + h_blank = mode->hts_def - mode->width; + __v4l2_ctrl_modify_range(sc830ai->hblank, h_blank, + h_blank, 1, h_blank); + vblank_def = mode->vts_def - mode->height; + __v4l2_ctrl_modify_range(sc830ai->vblank, vblank_def, + SC830AI_VTS_MAX - mode->height, + 1, vblank_def); + __v4l2_ctrl_s_ctrl(sc830ai->link_freq, mode->mipi_freq_idx); + pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / + mode->bpp * 2 * SC830AI_2LANES; + __v4l2_ctrl_s_ctrl_int64(sc830ai->pixel_rate, pixel_rate); + sc830ai->cur_fps = mode->max_fps; + sc830ai->cur_vts = mode->vts_def; + } + + mutex_unlock(&sc830ai->mutex); + + return 0; +} + +static int sc830ai_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct sc830ai *sc830ai = to_sc830ai(sd); + const struct sc830ai_mode *mode = sc830ai->cur_mode; + + mutex_lock(&sc830ai->mutex); + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad); +#else + mutex_unlock(&sc830ai->mutex); + return -ENOTTY; +#endif + } else { + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.code = mode->bus_fmt; + fmt->format.field = V4L2_FIELD_NONE; + if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR) + fmt->reserved[0] = mode->vc[fmt->pad]; + else + fmt->reserved[0] = mode->vc[PAD0]; + } + mutex_unlock(&sc830ai->mutex); + + return 0; +} + +static int sc830ai_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct sc830ai *sc830ai = to_sc830ai(sd); + + if (code->index != 0) + return -EINVAL; + code->code = sc830ai->cur_mode->bus_fmt; + + return 0; +} + +static int sc830ai_enum_frame_sizes(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct sc830ai *sc830ai = to_sc830ai(sd); + + if (fse->index >= sc830ai->cfg_num) + return -EINVAL; + + if (fse->code != supported_modes[fse->index].bus_fmt) + return -EINVAL; + + fse->min_width = supported_modes[fse->index].width; + fse->max_width = supported_modes[fse->index].width; + fse->max_height = supported_modes[fse->index].height; + fse->min_height = supported_modes[fse->index].height; + + return 0; +} + +static int sc830ai_enable_test_pattern(struct sc830ai *sc830ai, u32 pattern) +{ + u32 val = 0; + int ret = 0; + + ret = sc830ai_read_reg(sc830ai->client, SC830AI_REG_TEST_PATTERN, + SC830AI_REG_VALUE_08BIT, &val); + if (pattern) + val |= SC830AI_TEST_PATTERN_ENABLE; + else + val &= ~SC830AI_TEST_PATTERN_ENABLE; + ret |= sc830ai_write_reg(sc830ai->client, SC830AI_REG_TEST_PATTERN, + SC830AI_REG_VALUE_08BIT, val); + return ret; +} + +static int sc830ai_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *fi) +{ + struct sc830ai *sc830ai = to_sc830ai(sd); + const struct sc830ai_mode *mode = sc830ai->cur_mode; + + if (sc830ai->streaming) + fi->interval = sc830ai->cur_fps; + else + fi->interval = mode->max_fps; + + return 0; +} + +static int sc830ai_g_mbus_config(struct v4l2_subdev *sd, + unsigned int pad_id, + struct v4l2_mbus_config *config) +{ + struct sc830ai *sc830ai = to_sc830ai(sd); + const struct sc830ai_mode *mode = sc830ai->cur_mode; + u32 val = 0; + + if (mode->hdr_mode == NO_HDR) + val = 1 << (SC830AI_2LANES - 1) | + V4L2_MBUS_CSI2_CHANNEL_0 | + V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; + if (mode->hdr_mode == HDR_X2) + val = 1 << (SC830AI_2LANES - 1) | + V4L2_MBUS_CSI2_CHANNEL_0 | + V4L2_MBUS_CSI2_CONTINUOUS_CLOCK | + V4L2_MBUS_CSI2_CHANNEL_1; + + config->type = V4L2_MBUS_CSI2_DPHY; + config->flags = val; + + return 0; +} + +static void sc830ai_get_module_inf(struct sc830ai *sc830ai, + struct rkmodule_inf *inf) +{ + memset(inf, 0, sizeof(*inf)); + strscpy(inf->base.sensor, SC830AI_NAME, sizeof(inf->base.sensor)); + strscpy(inf->base.module, sc830ai->module_name, + sizeof(inf->base.module)); + strscpy(inf->base.lens, sc830ai->len_name, sizeof(inf->base.lens)); +} + +static void sc830ai_get_gain_reg(u32 val, u32 *again_reg, u32 *dgain_reg, + u32 *dgain_fine_reg) +{ + u32 total_gain; + + total_gain = val; + if (total_gain < 0x20) + total_gain = 0x20; + else if (total_gain > SC830AI_GAIN_MAX) + total_gain = SC830AI_GAIN_MAX; + + if (total_gain < 0x40) { /* 1 - 2x gain */ + *again_reg = 0x40; + *dgain_reg = 0x00; + *dgain_fine_reg = total_gain << 2; + } else if (total_gain < 0x80) { /* 2x - 4x gain */ + *again_reg = 0x48; + *dgain_reg = 0x00; + *dgain_fine_reg = (total_gain << 2) >> 1; + } else if (total_gain < 0x100) { /* 4x - 8x gain */ + *again_reg = 0x49; + *dgain_reg = 0x00; + *dgain_fine_reg = (total_gain << 2) >> 2; + } else if (total_gain < 0x200) { /* 8x - 16x gain */ + *again_reg = 0x4B; + *dgain_reg = 0x00; + *dgain_fine_reg = (total_gain << 2) >> 3; + } else if (total_gain < 0x400) { /* 16x - 32x gain */ + *again_reg = 0x4F; + *dgain_reg = 0x00; + *dgain_fine_reg = (total_gain << 2) >> 4; + } else if (total_gain < 0x800) { /* 32x - 64x gain */ + *again_reg = 0x5F; + *dgain_reg = 0x00; + *dgain_fine_reg = (total_gain << 2) >> 5; + } else { // (total_gain < 0x1000) /* 64x gain */ + *again_reg = 0x5F; + *dgain_reg = 0x01; + *dgain_fine_reg = (total_gain << 2) >> 6; + } + + *dgain_fine_reg = *dgain_fine_reg / 4 * 4; +} + +static int sc830ai_get_channel_info(struct sc830ai *sc830ai, struct rkmodule_channel_info *ch_info) +{ + if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX) + return -EINVAL; + ch_info->vc = sc830ai->cur_mode->vc[ch_info->index]; + ch_info->width = sc830ai->cur_mode->width; + ch_info->height = sc830ai->cur_mode->height; + ch_info->bus_fmt = sc830ai->cur_mode->bus_fmt; + return 0; +} + +static long sc830ai_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct sc830ai *sc830ai = to_sc830ai(sd); + struct rkmodule_hdr_cfg *hdr_cfg; + const struct sc830ai_mode *mode; + struct rkmodule_channel_info *ch_info; + long ret = 0; + u64 pixel_rate = 0; + u32 i, h, w, stream; + + switch (cmd) { + case PREISP_CMD_SET_HDRAE_EXP: + /* + * ret = sc830ai_set_hdrae(sc830ai, arg); + */ + break; + + case RKMODULE_SET_HDR_CFG: + hdr_cfg = (struct rkmodule_hdr_cfg *)arg; + if (sc830ai->streaming) { + ret = sc830ai_write_array(sc830ai->client, sc830ai->cur_mode->reg_list); + if (ret) + return ret; + } + w = sc830ai->cur_mode->width; + h = sc830ai->cur_mode->height; + for (i = 0; i < sc830ai->cfg_num; i++) { + if (w == supported_modes[i].width && + h == supported_modes[i].height && + supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) { + sc830ai_change_mode(sc830ai, &supported_modes[i]); + break; + } + } + if (i == sc830ai->cfg_num) { + dev_err(&sc830ai->client->dev, + "not find hdr mode:%d %dx%d config\n", + hdr_cfg->hdr_mode, w, h); + ret = -EINVAL; + } else { + mode = sc830ai->cur_mode; + w = mode->hts_def - mode->width; + h = mode->vts_def - mode->height; + __v4l2_ctrl_modify_range(sc830ai->hblank, w, w, 1, w); + __v4l2_ctrl_modify_range(sc830ai->vblank, h, + SC830AI_VTS_MAX - mode->height, + 1, h); + __v4l2_ctrl_s_ctrl(sc830ai->link_freq, mode->mipi_freq_idx); + pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / + mode->bpp * 2 * SC830AI_2LANES; + __v4l2_ctrl_s_ctrl_int64(sc830ai->pixel_rate, + pixel_rate); + sc830ai->cur_fps = mode->max_fps; + sc830ai->cur_vts = mode->vts_def; + dev_info(&sc830ai->client->dev, + "sensor mode: %d\n", mode->hdr_mode); + } + break; + case RKMODULE_GET_MODULE_INFO: + sc830ai_get_module_inf(sc830ai, (struct rkmodule_inf *)arg); + break; + + case RKMODULE_GET_HDR_CFG: + hdr_cfg = (struct rkmodule_hdr_cfg *)arg; + hdr_cfg->esp.mode = HDR_NORMAL_VC; + hdr_cfg->hdr_mode = sc830ai->cur_mode->hdr_mode; + break; + + case RKMODULE_SET_QUICK_STREAM: + stream = *((u32 *)arg); + if (stream) + ret = sc830ai_write_reg(sc830ai->client, SC830AI_REG_CTRL_MODE, + SC830AI_REG_VALUE_08BIT, SC830AI_MODE_STREAMING); + else + ret = sc830ai_write_reg(sc830ai->client, SC830AI_REG_CTRL_MODE, + SC830AI_REG_VALUE_08BIT, SC830AI_MODE_SW_STANDBY); + break; + + case RKMODULE_GET_CHANNEL_INFO: + ch_info = (struct rkmodule_channel_info *)arg; + ret = sc830ai_get_channel_info(sc830ai, ch_info); + break; + + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} + +#ifdef CONFIG_COMPAT +static long sc830ai_compat_ioctl32(struct v4l2_subdev *sd, + unsigned int cmd, unsigned long arg) +{ + void __user *up = compat_ptr(arg); + struct rkmodule_inf *inf; + struct rkmodule_awb_cfg *cfg; + struct rkmodule_hdr_cfg *hdr; + struct preisp_hdrae_exp_s *hdrae; + struct rkmodule_channel_info *ch_info; + long ret; + u32 stream; + u32 brl = 0; + struct rkmodule_csi_dphy_param *dphy_param; + + switch (cmd) { + case RKMODULE_GET_MODULE_INFO: + inf = kzalloc(sizeof(*inf), GFP_KERNEL); + if (!inf) { + ret = -ENOMEM; + return ret; + } + + ret = sc830ai_ioctl(sd, cmd, inf); + if (!ret) { + if (copy_to_user(up, inf, sizeof(*inf))) { + kfree(inf); + return -EFAULT; + } + } + kfree(inf); + break; + case RKMODULE_AWB_CFG: + cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); + if (!cfg) { + ret = -ENOMEM; + return ret; + } + + if (copy_from_user(cfg, up, sizeof(*cfg))) { + kfree(cfg); + return -EFAULT; + } + ret = sc830ai_ioctl(sd, cmd, cfg); + kfree(cfg); + break; + case RKMODULE_GET_HDR_CFG: + hdr = kzalloc(sizeof(*hdr), GFP_KERNEL); + if (!hdr) { + ret = -ENOMEM; + return ret; + } + + ret = sc830ai_ioctl(sd, cmd, hdr); + if (!ret) { + if (copy_to_user(up, hdr, sizeof(*hdr))) { + kfree(hdr); + return -EFAULT; + } + } + kfree(hdr); + break; + case RKMODULE_SET_HDR_CFG: + hdr = kzalloc(sizeof(*hdr), GFP_KERNEL); + if (!hdr) { + ret = -ENOMEM; + return ret; + } + + if (copy_from_user(hdr, up, sizeof(*hdr))) { + kfree(hdr); + return -EFAULT; + } + ret = sc830ai_ioctl(sd, cmd, hdr); + kfree(hdr); + break; + case PREISP_CMD_SET_HDRAE_EXP: + hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL); + if (!hdrae) { + ret = -ENOMEM; + return ret; + } + + if (copy_from_user(hdrae, up, sizeof(*hdrae))) { + kfree(hdrae); + return -EFAULT; + } + ret = sc830ai_ioctl(sd, cmd, hdrae); + kfree(hdrae); + break; + case RKMODULE_SET_QUICK_STREAM: + if (copy_from_user(&stream, up, sizeof(u32))) + return -EFAULT; + ret = sc830ai_ioctl(sd, cmd, &stream); + break; + case RKMODULE_GET_SONY_BRL: + ret = sc830ai_ioctl(sd, cmd, &brl); + if (!ret) { + if (copy_to_user(up, &brl, sizeof(u32))) + return -EFAULT; + } + break; + case RKMODULE_GET_CHANNEL_INFO: + ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL); + if (!ch_info) { + ret = -ENOMEM; + return ret; + } + + ret = sc830ai_ioctl(sd, cmd, ch_info); + if (!ret) { + ret = copy_to_user(up, ch_info, sizeof(*ch_info)); + if (ret) + ret = -EFAULT; + } + kfree(ch_info); + break; + case RKMODULE_GET_CSI_DPHY_PARAM: + dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL); + if (!dphy_param) { + ret = -ENOMEM; + return ret; + } + + ret = sc830ai_ioctl(sd, cmd, dphy_param); + if (!ret) { + ret = copy_to_user(up, dphy_param, sizeof(*dphy_param)); + if (ret) + ret = -EFAULT; + } + kfree(dphy_param); + break; + + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} +#endif + + +static int __sc830ai_start_stream(struct sc830ai *sc830ai) +{ + int ret; + + ret = sc830ai_write_array(sc830ai->client, sc830ai->cur_mode->reg_list); + if (ret) + return ret; + + ret = __v4l2_ctrl_handler_setup(&sc830ai->ctrl_handler); + if (ret) + return ret; + /* In case these controls are set before streaming */ + if (sc830ai->has_init_exp && sc830ai->cur_mode->hdr_mode != NO_HDR) { + ret = sc830ai_ioctl(&sc830ai->subdev, PREISP_CMD_SET_HDRAE_EXP, + &sc830ai->init_hdrae_exp); + if (ret) { + dev_err(&sc830ai->client->dev, + "init exp fail in hdr mode\n"); + return ret; + } + } + return sc830ai_write_reg(sc830ai->client, SC830AI_REG_CTRL_MODE, + SC830AI_REG_VALUE_08BIT, SC830AI_MODE_STREAMING); +} + +static int __sc830ai_stop_stream(struct sc830ai *sc830ai) +{ + sc830ai->has_init_exp = false; + return sc830ai_write_reg(sc830ai->client, SC830AI_REG_CTRL_MODE, + SC830AI_REG_VALUE_08BIT, SC830AI_MODE_SW_STANDBY); +} + +static int sc830ai_s_stream(struct v4l2_subdev *sd, int on) +{ + struct sc830ai *sc830ai = to_sc830ai(sd); + struct i2c_client *client = sc830ai->client; + int ret = 0; + + dev_info(&sc830ai->client->dev, "s_stream: %d. %dx%d, hdr: %d, bpp: %d\n", + on, sc830ai->cur_mode->width, sc830ai->cur_mode->height, + sc830ai->cur_mode->hdr_mode, sc830ai->cur_mode->bpp); + + mutex_lock(&sc830ai->mutex); + on = !!on; + if (on == sc830ai->streaming) + goto unlock_and_return; + + if (on) { + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + ret = __sc830ai_start_stream(sc830ai); + if (ret) { + v4l2_err(sd, "start stream failed while write regs\n"); + pm_runtime_put(&client->dev); + goto unlock_and_return; + } + } else { + __sc830ai_stop_stream(sc830ai); + pm_runtime_put(&client->dev); + } + + sc830ai->streaming = on; + +unlock_and_return: + mutex_unlock(&sc830ai->mutex); + return ret; +} + +static int sc830ai_s_power(struct v4l2_subdev *sd, int on) +{ + struct sc830ai *sc830ai = to_sc830ai(sd); + struct i2c_client *client = sc830ai->client; + int ret = 0; + + mutex_lock(&sc830ai->mutex); + + /* If the power state is not modified - no work to do. */ + if (sc830ai->power_on == !!on) + goto unlock_and_return; + + if (on) { + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + + ret |= sc830ai_write_reg(sc830ai->client, + SC830AI_SOFTWARE_RESET_REG, + SC830AI_REG_VALUE_08BIT, + 0x01); + /* + * usleep_range(100, 200); + * ret |= sc830ai_write_reg(sc2310->client, + * 0x303f, + * SC830AI_REG_VALUE_08BIT, + * 0x01); + */ + sc830ai->power_on = true; + } else { + pm_runtime_put(&client->dev); + sc830ai->power_on = false; + } + +unlock_and_return: + mutex_unlock(&sc830ai->mutex); + + return ret; +} + +/* Calculate the delay in us by clock rate and clock cycles */ +static inline u32 sc830ai_cal_delay(u32 cycles) +{ + return DIV_ROUND_UP(cycles, SC830AI_XVCLK_FREQ / 1000 / 1000); +} + +static int __sc830ai_power_on(struct sc830ai *sc830ai) +{ + int ret; + u32 delay_us; + struct device *dev = &sc830ai->client->dev; + + if (!IS_ERR_OR_NULL(sc830ai->pins_default)) { + ret = pinctrl_select_state(sc830ai->pinctrl, sc830ai->pins_default); + if (ret < 0) + dev_err(dev, "could not set pins\n"); + } + + ret = clk_set_rate(sc830ai->xvclk, SC830AI_XVCLK_FREQ); + if (ret < 0) + dev_warn(dev, "Failed to set xvclk rate 24MHz\n"); + if (clk_get_rate(sc830ai->xvclk) != SC830AI_XVCLK_FREQ) + dev_warn(dev, "xvclk mismatched\n"); + ret = clk_prepare_enable(sc830ai->xvclk); + if (ret < 0) { + dev_err(dev, "Failed to enable xvclk\n"); + goto err_clk; + } + if (!IS_ERR(sc830ai->reset_gpio)) + gpiod_direction_output(sc830ai->reset_gpio, 0); + + ret = regulator_bulk_enable(SC830AI_NUM_SUPPLIES, sc830ai->supplies); + if (ret < 0) { + dev_err(dev, "Failed to enable regulators\n"); + goto disable_clk; + } + + if (!IS_ERR(sc830ai->reset_gpio)) + gpiod_direction_output(sc830ai->reset_gpio, 1); + + usleep_range(5000, 10000); + if (!IS_ERR(sc830ai->pwdn_gpio)) + gpiod_direction_output(sc830ai->pwdn_gpio, 1); + + if (!IS_ERR(sc830ai->reset_gpio)) + usleep_range(6000, 8000); + else + usleep_range(12000, 16000); + + /* 8192 cycles prior to first SCCB transaction */ + delay_us = sc830ai_cal_delay(8192); + usleep_range(delay_us, delay_us * 2); + return 0; +err_clk: + if (!IS_ERR(sc830ai->reset_gpio)) + gpiod_direction_output(sc830ai->reset_gpio, 0); +disable_clk: + clk_disable_unprepare(sc830ai->xvclk); + + return ret; +} + +static void __sc830ai_power_off(struct sc830ai *sc830ai) +{ + int ret; + struct device *dev = &sc830ai->client->dev; + + if (!IS_ERR(sc830ai->pwdn_gpio)) + gpiod_direction_output(sc830ai->pwdn_gpio, 0); + + clk_disable_unprepare(sc830ai->xvclk); + + if (!IS_ERR(sc830ai->reset_gpio)) + gpiod_direction_output(sc830ai->reset_gpio, 0); + + if (!IS_ERR_OR_NULL(sc830ai->pins_sleep)) { + ret = pinctrl_select_state(sc830ai->pinctrl, + sc830ai->pins_sleep); + if (ret < 0) + dev_dbg(dev, "could not set pins\n"); + } + regulator_bulk_disable(SC830AI_NUM_SUPPLIES, sc830ai->supplies); +} + +static int sc830ai_runtime_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct sc830ai *sc830ai = to_sc830ai(sd); + + return __sc830ai_power_on(sc830ai); +} + +static int sc830ai_runtime_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct sc830ai *sc830ai = to_sc830ai(sd); + + __sc830ai_power_off(sc830ai); + + return 0; +} + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API +static int sc830ai_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct sc830ai *sc830ai = to_sc830ai(sd); + struct v4l2_mbus_framefmt *try_fmt = + v4l2_subdev_get_try_format(sd, fh->pad, 0); + const struct sc830ai_mode *def_mode = &supported_modes[0]; + + mutex_lock(&sc830ai->mutex); + /* Initialize try_fmt */ + try_fmt->width = def_mode->width; + try_fmt->height = def_mode->height; + try_fmt->code = def_mode->bus_fmt; + try_fmt->field = V4L2_FIELD_NONE; + + mutex_unlock(&sc830ai->mutex); + /* No crop or compose */ + + return 0; +} +#endif + +static int sc830ai_enum_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum *fie) +{ + struct sc830ai *sc830ai = to_sc830ai(sd); + + if (fie->index >= sc830ai->cfg_num) + return -EINVAL; + + fie->code = supported_modes[fie->index].bus_fmt; + fie->width = supported_modes[fie->index].width; + fie->height = supported_modes[fie->index].height; + fie->interval = supported_modes[fie->index].max_fps; + fie->reserved[0] = supported_modes[fie->index].hdr_mode; + return 0; +} + +#define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4) +#define DST_WIDTH_3840 3840 +#define DST_HEIGHT_2160 2160 +#define DST_WIDTH_1920 1920 +#define DST_HEIGHT_1080 1080 + +static int sc830ai_get_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_selection *sel) +{ + struct sc830ai *sc830ai = to_sc830ai(sd); + + if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) { + if (sc830ai->cur_mode->width == 3856) { + sel->r.left = CROP_START(sc830ai->cur_mode->width, DST_WIDTH_3840); + sel->r.width = DST_WIDTH_3840; + sel->r.top = CROP_START(sc830ai->cur_mode->height, DST_HEIGHT_2160); + sel->r.height = DST_HEIGHT_2160; + } else if (sc830ai->cur_mode->width == 1944) { + sel->r.left = CROP_START(sc830ai->cur_mode->width, DST_WIDTH_1920); + sel->r.width = DST_WIDTH_1920; + sel->r.top = CROP_START(sc830ai->cur_mode->height, DST_HEIGHT_1080); + sel->r.height = DST_HEIGHT_1080; + } else { + sel->r.left = CROP_START(sc830ai->cur_mode->width, + sc830ai->cur_mode->width); + sel->r.width = sc830ai->cur_mode->width; + sel->r.top = CROP_START(sc830ai->cur_mode->height, + sc830ai->cur_mode->height); + sel->r.height = sc830ai->cur_mode->height; + } + return 0; + } + return -EINVAL; +} + +static const struct dev_pm_ops sc830ai_pm_ops = { + SET_RUNTIME_PM_OPS(sc830ai_runtime_suspend, + sc830ai_runtime_resume, NULL) +}; + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API +static const struct v4l2_subdev_internal_ops sc830ai_internal_ops = { + .open = sc830ai_open, +}; +#endif + +static const struct v4l2_subdev_core_ops sc830ai_core_ops = { + .s_power = sc830ai_s_power, + .ioctl = sc830ai_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = sc830ai_compat_ioctl32, +#endif +}; + +static const struct v4l2_subdev_video_ops sc830ai_video_ops = { + .s_stream = sc830ai_s_stream, + .g_frame_interval = sc830ai_g_frame_interval, +}; + +static const struct v4l2_subdev_pad_ops sc830ai_pad_ops = { + .enum_mbus_code = sc830ai_enum_mbus_code, + .enum_frame_size = sc830ai_enum_frame_sizes, + .enum_frame_interval = sc830ai_enum_frame_interval, + .get_fmt = sc830ai_get_fmt, + .set_fmt = sc830ai_set_fmt, + .get_selection = sc830ai_get_selection, + .get_mbus_config = sc830ai_g_mbus_config, +}; + +static const struct v4l2_subdev_ops sc830ai_subdev_ops = { + .core = &sc830ai_core_ops, + .video = &sc830ai_video_ops, + .pad = &sc830ai_pad_ops, +}; + +static void sc830ai_modify_fps_info(struct sc830ai *sc830ai) +{ + const struct sc830ai_mode *mode = sc830ai->cur_mode; + + sc830ai->cur_fps.denominator = mode->max_fps.denominator * sc830ai->cur_vts / + mode->vts_def; +} + +static int sc830ai_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct sc830ai *sc830ai = container_of(ctrl->handler, + struct sc830ai, ctrl_handler); + struct i2c_client *client = sc830ai->client; + s64 max; + u32 again, dgain, dgain_fine; + int ret = 0; + u32 val; + + /* Propagate change of current control to all related controls */ + switch (ctrl->id) { + case V4L2_CID_VBLANK: + /* Update max exposure while meeting expected vblanking */ + max = sc830ai->cur_mode->height + ctrl->val - 8; + __v4l2_ctrl_modify_range(sc830ai->exposure, + sc830ai->exposure->minimum, max, + sc830ai->exposure->step, + sc830ai->exposure->default_value); + break; + } + + if (!pm_runtime_get_if_in_use(&client->dev)) + return 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE: + if (sc830ai->cur_mode->hdr_mode != NO_HDR) + goto out_ctrl; + ret = sc830ai_write_reg(sc830ai->client, + SC830AI_REG_EXP_LONG_H, + SC830AI_REG_VALUE_08BIT, + SC830AI_FETCH_EXP_H(ctrl->val)); + ret |= sc830ai_write_reg(sc830ai->client, + SC830AI_REG_EXP_LONG_M, + SC830AI_REG_VALUE_08BIT, + SC830AI_FETCH_EXP_M(ctrl->val)); + ret |= sc830ai_write_reg(sc830ai->client, + SC830AI_REG_EXP_LONG_L, + SC830AI_REG_VALUE_08BIT, + SC830AI_FETCH_EXP_L(ctrl->val)); + + dev_dbg(&client->dev, "set exposure 0x%x\n", + ctrl->val); + break; + case V4L2_CID_ANALOGUE_GAIN: + if (sc830ai->cur_mode->hdr_mode != NO_HDR) + goto out_ctrl; + sc830ai_get_gain_reg(ctrl->val, &again, &dgain, &dgain_fine); + dev_dbg(&client->dev, "recv_gain:%d set again 0x%x, set dgain 0x%x, dgain_fine 0x%x\n", + ctrl->val, again, dgain, dgain_fine); + + ret |= sc830ai_write_reg(sc830ai->client, + SC830AI_REG_AGAIN, + SC830AI_REG_VALUE_08BIT, + again); + ret |= sc830ai_write_reg(sc830ai->client, + SC830AI_REG_DGAIN, + SC830AI_REG_VALUE_08BIT, + dgain); + ret |= sc830ai_write_reg(sc830ai->client, + SC830AI_REG_DGAIN_FINE, + SC830AI_REG_VALUE_08BIT, + dgain_fine); + break; + case V4L2_CID_VBLANK: + ret = sc830ai_write_reg(sc830ai->client, SC830AI_REG_VTS, + SC830AI_REG_VALUE_16BIT, + ctrl->val + sc830ai->cur_mode->height); + if (!ret) + sc830ai->cur_vts = ctrl->val + sc830ai->cur_mode->height; + sc830ai_modify_fps_info(sc830ai); + dev_dbg(&client->dev, "set vblank 0x%x\n", + ctrl->val); + break; + case V4L2_CID_TEST_PATTERN: + ret = sc830ai_enable_test_pattern(sc830ai, ctrl->val); + break; + case V4L2_CID_HFLIP: + ret = sc830ai_read_reg(sc830ai->client, SC830AI_FLIP_REG, + SC830AI_REG_VALUE_08BIT, &val); + if (ret) + break; + if (ctrl->val) + val |= SC830AI_MIRROR_MASK; + else + val &= ~SC830AI_MIRROR_MASK; + ret |= sc830ai_write_reg(sc830ai->client, SC830AI_FLIP_REG, + SC830AI_REG_VALUE_08BIT, val); + break; + case V4L2_CID_VFLIP: + ret = sc830ai_read_reg(sc830ai->client, SC830AI_FLIP_REG, + SC830AI_REG_VALUE_08BIT, &val); + if (ret) + break; + if (ctrl->val) + val |= SC830AI_FLIP_MASK; + else + val &= ~SC830AI_FLIP_MASK; + ret |= sc830ai_write_reg(sc830ai->client, SC830AI_FLIP_REG, + SC830AI_REG_VALUE_08BIT, val); + break; + default: + dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n", + __func__, ctrl->id, ctrl->val); + break; + } + +out_ctrl: + pm_runtime_put(&client->dev); + + return ret; +} + +static const struct v4l2_ctrl_ops sc830ai_ctrl_ops = { + .s_ctrl = sc830ai_set_ctrl, +}; + +static int sc830ai_initialize_controls(struct sc830ai *sc830ai) +{ + const struct sc830ai_mode *mode; + struct v4l2_ctrl_handler *handler; + s64 exposure_max, vblank_def; + u64 pixel_rate = 0; + u32 h_blank; + int ret; + + handler = &sc830ai->ctrl_handler; + mode = sc830ai->cur_mode; + ret = v4l2_ctrl_handler_init(handler, 9); + if (ret) + return ret; + handler->lock = &sc830ai->mutex; + + sc830ai->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, + V4L2_CID_LINK_FREQ, 0, 0, link_freq_items); + v4l2_ctrl_s_ctrl(sc830ai->link_freq, mode->mipi_freq_idx); + + /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */ + pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * SC830AI_2LANES; + sc830ai->pixel_rate = v4l2_ctrl_new_std(handler, NULL, + V4L2_CID_PIXEL_RATE, 0, SC830AI_MAX_PIXEL_RATE, + 1, pixel_rate); + + h_blank = mode->hts_def - mode->width; + sc830ai->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK, + h_blank, h_blank, 1, h_blank); + if (sc830ai->hblank) + sc830ai->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + vblank_def = mode->vts_def - mode->height; + sc830ai->vblank = v4l2_ctrl_new_std(handler, &sc830ai_ctrl_ops, + V4L2_CID_VBLANK, vblank_def, + SC830AI_VTS_MAX - mode->height, + 1, vblank_def); + + exposure_max = mode->vts_def - 4; /*vts_def 0x08ca=2250*/ + sc830ai->exposure = v4l2_ctrl_new_std(handler, &sc830ai_ctrl_ops, + V4L2_CID_EXPOSURE, SC830AI_EXPOSURE_MIN, + exposure_max, SC830AI_EXPOSURE_STEP, + mode->exp_def); /*exp_def 0x08c0=2240*/ + + sc830ai->anal_a_gain = v4l2_ctrl_new_std(handler, &sc830ai_ctrl_ops, + V4L2_CID_ANALOGUE_GAIN, SC830AI_GAIN_MIN, + SC830AI_GAIN_MAX, SC830AI_GAIN_STEP, + SC830AI_GAIN_DEFAULT); + + sc830ai->test_pattern = v4l2_ctrl_new_std_menu_items(handler, + &sc830ai_ctrl_ops, V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(sc830ai_test_pattern_menu) - 1, + 0, 0, sc830ai_test_pattern_menu); + + v4l2_ctrl_new_std(handler, &sc830ai_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0); + v4l2_ctrl_new_std(handler, &sc830ai_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0); + + if (handler->error) { + ret = handler->error; + dev_err(&sc830ai->client->dev, + "Failed to init controls(%d)\n", ret); + goto err_free_handler; + } + + sc830ai->subdev.ctrl_handler = handler; + sc830ai->has_init_exp = false; + sc830ai->cur_fps = mode->max_fps; + sc830ai->cur_vts = mode->vts_def; + + return 0; + +err_free_handler: + v4l2_ctrl_handler_free(handler); + + return ret; +} + +static int sc830ai_check_sensor_id(struct sc830ai *sc830ai, + struct i2c_client *client) +{ + struct device *dev = &sc830ai->client->dev; + u32 id = 0; + int ret; + + ret = sc830ai_read_reg(client, SC830AI_REG_CHIP_ID, + SC830AI_REG_VALUE_16BIT, &id); + if (id != CHIP_ID) { + dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret); + return -ENODEV; + } + + dev_info(dev, "Detected sc830ai id %06x\n", CHIP_ID); + + return 0; +} + +static int sc830ai_configure_regulators(struct sc830ai *sc830ai) +{ + unsigned int i; + + for (i = 0; i < SC830AI_NUM_SUPPLIES; i++) + sc830ai->supplies[i].supply = sc830ai_supply_names[i]; + + return devm_regulator_bulk_get(&sc830ai->client->dev, + SC830AI_NUM_SUPPLIES, + sc830ai->supplies); +} + +static int sc830ai_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct device_node *node = dev->of_node; + struct sc830ai *sc830ai; + struct v4l2_subdev *sd; + char facing[2]; + int ret; + u32 i, hdr_mode = 0; + + dev_info(dev, "driver version: %02x.%02x.%02x", + DRIVER_VERSION >> 16, + (DRIVER_VERSION & 0xff00) >> 8, + DRIVER_VERSION & 0x00ff); + + sc830ai = devm_kzalloc(dev, sizeof(*sc830ai), GFP_KERNEL); + if (!sc830ai) + return -ENOMEM; + + ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX, + &sc830ai->module_index); + ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING, + &sc830ai->module_facing); + ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME, + &sc830ai->module_name); + ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME, + &sc830ai->len_name); + if (ret) { + dev_err(dev, "could not get module information!\n"); + return -EINVAL; + } + + ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode); + if (ret) { + hdr_mode = NO_HDR; + dev_warn(dev, " Get hdr mode failed! no hdr default\n"); + } + + sc830ai->client = client; + sc830ai->cfg_num = ARRAY_SIZE(supported_modes); + for (i = 0; i < sc830ai->cfg_num; i++) { + if (hdr_mode == supported_modes[i].hdr_mode) { + sc830ai->cur_mode = &supported_modes[i]; + break; + } + } + if (i == ARRAY_SIZE(supported_modes)) + sc830ai->cur_mode = &supported_modes[0]; + + sc830ai->xvclk = devm_clk_get(dev, "xvclk"); + if (IS_ERR(sc830ai->xvclk)) { + dev_err(dev, "Failed to get xvclk\n"); + return -EINVAL; + } + + sc830ai->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS); + if (IS_ERR(sc830ai->reset_gpio)) + dev_warn(dev, "Failed to get reset-gpios\n"); + sc830ai->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS); + if (IS_ERR(sc830ai->pwdn_gpio)) + dev_warn(dev, "Failed to get pwdn_gpios\n"); + + sc830ai->pinctrl = devm_pinctrl_get(dev); + if (!IS_ERR(sc830ai->pinctrl)) { + sc830ai->pins_default = + pinctrl_lookup_state(sc830ai->pinctrl, + OF_CAMERA_PINCTRL_STATE_DEFAULT); + if (IS_ERR(sc830ai->pins_default)) + dev_info(dev, "could not get default pinstate\n"); + + sc830ai->pins_sleep = + pinctrl_lookup_state(sc830ai->pinctrl, + OF_CAMERA_PINCTRL_STATE_SLEEP); + if (IS_ERR(sc830ai->pins_sleep)) + dev_info(dev, "could not get sleep pinstate\n"); + } else { + dev_info(dev, "no pinctrl\n"); + } + + ret = sc830ai_configure_regulators(sc830ai); + if (ret) { + dev_err(dev, "Failed to get power regulators\n"); + return ret; + } + + mutex_init(&sc830ai->mutex); + + sd = &sc830ai->subdev; + v4l2_i2c_subdev_init(sd, client, &sc830ai_subdev_ops); + ret = sc830ai_initialize_controls(sc830ai); + if (ret) + goto err_destroy_mutex; + + ret = __sc830ai_power_on(sc830ai); + if (ret) + goto err_free_handler; + + ret = sc830ai_check_sensor_id(sc830ai, client); + if (ret) + goto err_power_off; +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + sd->internal_ops = &sc830ai_internal_ops; + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | + V4L2_SUBDEV_FL_HAS_EVENTS; +#endif +#if defined(CONFIG_MEDIA_CONTROLLER) + sc830ai->pad.flags = MEDIA_PAD_FL_SOURCE; + sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = media_entity_pads_init(&sd->entity, 1, &sc830ai->pad); + if (ret < 0) + goto err_power_off; +#endif + + memset(facing, 0, sizeof(facing)); + if (strcmp(sc830ai->module_facing, "back") == 0) + facing[0] = 'b'; + else + facing[0] = 'f'; + snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s", + sc830ai->module_index, facing, + SC830AI_NAME, dev_name(sd->dev)); + + ret = v4l2_async_register_subdev_sensor_common(sd); + if (ret) { + dev_err(dev, "v4l2 async register subdev failed\n"); + goto err_clean_entity; + } + + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + pm_runtime_idle(dev); + + return 0; + +err_clean_entity: +#if defined(CONFIG_MEDIA_CONTROLLER) + media_entity_cleanup(&sd->entity); +#endif +err_power_off: + __sc830ai_power_off(sc830ai); +err_free_handler: + v4l2_ctrl_handler_free(&sc830ai->ctrl_handler); +err_destroy_mutex: + mutex_destroy(&sc830ai->mutex); + + return ret; +} + +static int sc830ai_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct sc830ai *sc830ai = to_sc830ai(sd); + + v4l2_async_unregister_subdev(sd); +#if defined(CONFIG_MEDIA_CONTROLLER) + media_entity_cleanup(&sd->entity); +#endif + v4l2_ctrl_handler_free(&sc830ai->ctrl_handler); + mutex_destroy(&sc830ai->mutex); + + pm_runtime_disable(&client->dev); + if (!pm_runtime_status_suspended(&client->dev)) + __sc830ai_power_off(sc830ai); + pm_runtime_set_suspended(&client->dev); + + return 0; +} + +#if IS_ENABLED(CONFIG_OF) +static const struct of_device_id sc830ai_of_match[] = { + { .compatible = "smartsens,sc830ai" }, + {}, +}; +MODULE_DEVICE_TABLE(of, sc830ai_of_match); +#endif + +static const struct i2c_device_id sc830ai_match_id[] = { + { "smartsens,sc830ai", 0 }, + { }, +}; + +static struct i2c_driver sc830ai_i2c_driver = { + .driver = { + .name = SC830AI_NAME, + .pm = &sc830ai_pm_ops, + .of_match_table = of_match_ptr(sc830ai_of_match), + }, + .probe = &sc830ai_probe, + .remove = &sc830ai_remove, + .id_table = sc830ai_match_id, +}; + +static int __init sensor_mod_init(void) +{ + return i2c_add_driver(&sc830ai_i2c_driver); +} + +static void __exit sensor_mod_exit(void) +{ + i2c_del_driver(&sc830ai_i2c_driver); +} + +device_initcall_sync(sensor_mod_init); +module_exit(sensor_mod_exit); + +MODULE_DESCRIPTION("smartsens,sc830ai sensor driver"); +MODULE_LICENSE("GPL"); From ff902937c029245f0e8672fbc7a3a24d45476942 Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Wed, 3 Jan 2024 09:20:32 +0800 Subject: [PATCH 18/22] arm64: dts: rockchip: rk3562: adjust low-temp-min-volt for cpu/dmc Raise voltage of cpu/dmc when low temperature to improve stability. Signed-off-by: Liang Chen Change-Id: I80321c0454c98c62a237192b46fa00da1b48d336 --- arch/arm64/boot/dts/rockchip/rk3562-dictpen-test3-v20.dts | 2 ++ arch/arm64/boot/dts/rockchip/rk3562.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-dictpen-test3-v20.dts b/arch/arm64/boot/dts/rockchip/rk3562-dictpen-test3-v20.dts index f2198a8b3e8d..c75f6293a1f4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-dictpen-test3-v20.dts +++ b/arch/arm64/boot/dts/rockchip/rk3562-dictpen-test3-v20.dts @@ -167,6 +167,8 @@ }; &cpu0_opp_table { + rockchip,low-temp-min-volt = <1000000>; + opp-408000000 { /delete-property/ opp-suspend; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index 7c15aba1fd87..7ccf7e2f2ec7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -273,7 +273,7 @@ rockchip,grf = <&sys_grf>; rockchip,temp-hysteresis = <5000>; rockchip,low-temp = <10000>; - rockchip,low-temp-min-volt = <925000>; + rockchip,low-temp-min-volt = <1050000>; opp-408000000 { opp-hz = /bits/ 64 <408000000>; @@ -501,7 +501,7 @@ rockchip,temp-hysteresis = <5000>; rockchip,low-temp = <10000>; - rockchip,low-temp-min-volt = <900000>; + rockchip,low-temp-min-volt = <950000>; rockchip,leakage-voltage-sel = < 1 15 0 From 801e11b222f961e397abac55c37e3222e442fcdd Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Wed, 3 Jan 2024 09:22:01 +0800 Subject: [PATCH 19/22] arm64: dts: rockchip: rk3562: adjust regulator-init-microvolt of vdd_cpu/vdd_logic for rk3562 boards Raise initial voltage of vdd_cpu/vdd_logic when startup to improve stability. Signed-off-by: Liang Chen Change-Id: I223a21351424cb3fb47e5b3cae4f8e0324bd9a25 --- arch/arm64/boot/dts/rockchip/rk3562-dictpen-test3-v20.dts | 4 ++-- arch/arm64/boot/dts/rockchip/rk3562-rk809.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts | 4 ++-- arch/arm64/boot/dts/rockchip/rk3562-rk817.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3562j-core-ddr4-v10.dts | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-dictpen-test3-v20.dts b/arch/arm64/boot/dts/rockchip/rk3562-dictpen-test3-v20.dts index c75f6293a1f4..0123146714bb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-dictpen-test3-v20.dts +++ b/arch/arm64/boot/dts/rockchip/rk3562-dictpen-test3-v20.dts @@ -682,7 +682,7 @@ regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; + regulator-init-microvolt = <950000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-name = "vdd_logic"; @@ -697,7 +697,7 @@ regulator-boot-on; regulator-min-microvolt = <825000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; + regulator-init-microvolt = <1000000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-name = "vdd_cpu"; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-rk809.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-rk809.dtsi index 02f91919b705..1bf64d327fdd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-rk809.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-rk809.dtsi @@ -76,7 +76,7 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; + regulator-init-microvolt = <950000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-name = "vdd_logic"; @@ -90,7 +90,7 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; + regulator-init-microvolt = <1050000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-name = "vdd_cpu"; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts index 4f9edc072df7..5dd4cc96f112 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts @@ -601,7 +601,7 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; + regulator-init-microvolt = <950000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-name = "vdd_logic"; @@ -616,7 +616,7 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; + regulator-init-microvolt = <1050000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-name = "vdd_cpu"; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-rk817.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-rk817.dtsi index 8bfd2466c232..25c8c62e077e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-rk817.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-rk817.dtsi @@ -72,7 +72,7 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; + regulator-init-microvolt = <950000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-name = "vdd_logic"; @@ -87,7 +87,7 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; + regulator-init-microvolt = <1050000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-name = "vdd_cpu"; diff --git a/arch/arm64/boot/dts/rockchip/rk3562j-core-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562j-core-ddr4-v10.dts index bdd68af31952..c98056c4517f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562j-core-ddr4-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3562j-core-ddr4-v10.dts @@ -180,7 +180,7 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; + regulator-init-microvolt = <950000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-name = "vdd_logic"; @@ -194,7 +194,7 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; + regulator-init-microvolt = <1050000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-name = "vdd_cpu"; From eaa1941ab724b04cdd577b429d64ec6ffe762229 Mon Sep 17 00:00:00 2001 From: Zhang Yubing Date: Wed, 6 Dec 2023 11:17:27 +0800 Subject: [PATCH 20/22] mfd: rkx110_x120: cru: fix to get a avialble pll rate In some case, the pll rate will be change to get a target rate for it's child. we want set the pll rate closest to the max pll rate. However, It's not all the rate can get a set of legal paramters to config the pll. So when this case happen, we try a lower rate as the target pll rate. Change-Id: I45abec2114f74634904cf3c34655d8df331d171b Signed-off-by: Zhang Yubing --- drivers/mfd/rkx110_x120/hal/cru_rkx110.c | 22 ++++++++++++++++------ drivers/mfd/rkx110_x120/hal/cru_rkx111.c | 22 ++++++++++++++++------ drivers/mfd/rkx110_x120/hal/cru_rkx120.c | 22 ++++++++++++++++------ drivers/mfd/rkx110_x120/hal/cru_rkx121.c | 22 ++++++++++++++++------ 4 files changed, 64 insertions(+), 24 deletions(-) diff --git a/drivers/mfd/rkx110_x120/hal/cru_rkx110.c b/drivers/mfd/rkx110_x120/hal/cru_rkx110.c index 5d53ec33dd60..4e1533fe1b31 100644 --- a/drivers/mfd/rkx110_x120/hal/cru_rkx110.c +++ b/drivers/mfd/rkx110_x120/hal/cru_rkx110.c @@ -263,6 +263,7 @@ static HAL_Status RKX11x_HAL_CRU_ClkSetFreq(struct hwclk *hw, uint32_t clockName uint32_t pll; uint8_t overMax = 0; HAL_Status ret = HAL_OK; + int i; if (clockName == RKX110_CLK_D_DSI_0_PATTERN_GEN || clockName == RKX110_CLK_D_DSI_1_PATTERN_GEN) { @@ -326,12 +327,21 @@ static HAL_Status RKX11x_HAL_CRU_ClkSetFreq(struct hwclk *hw, uint32_t clockName /* PLL change closest new rate <= 1200M if need */ if (!pRate) { - pRate = (_MHZ(1200) / rate) * rate; - } - - ret = RKX11x_HAL_CRU_ClkSetFreq(hw, pll, pRate); - if (ret != HAL_OK) { - return ret; + if (!rate || rate > _MHZ(1200)) + return HAL_ERROR; + for (i = _MHZ(1200) / rate; i > _MHZ(24) / rate; i--) { + pRate = i * rate; + ret = RKX11x_HAL_CRU_ClkSetFreq(hw, pll, pRate); + if (ret == HAL_OK) + break; + } + if (ret != HAL_OK) + return ret; + } else { + ret = RKX11x_HAL_CRU_ClkSetFreq(hw, pll, pRate); + if (ret != HAL_OK) { + return ret; + } } /* if success, continue to set divider */ diff --git a/drivers/mfd/rkx110_x120/hal/cru_rkx111.c b/drivers/mfd/rkx110_x120/hal/cru_rkx111.c index 41da74fb027b..1f22f406ffce 100644 --- a/drivers/mfd/rkx110_x120/hal/cru_rkx111.c +++ b/drivers/mfd/rkx110_x120/hal/cru_rkx111.c @@ -304,6 +304,7 @@ static HAL_Status RKX11x_HAL_CRU_ClkSetFreq(struct hwclk *hw, uint32_t clockName uint32_t pll; uint8_t overMax = 0; HAL_Status ret = HAL_OK; + int i; if (clockName == RKX110_CLK_D_DSI_0_PATTERN_GEN) { clockName = RKX111_CPS_DCLK_D_DSI_0_REC; @@ -371,12 +372,21 @@ static HAL_Status RKX11x_HAL_CRU_ClkSetFreq(struct hwclk *hw, uint32_t clockName /* PLL change closest new rate <= 1200M if need */ if (!pRate) { - pRate = (_MHZ(1200) / rate) * rate; - } - - ret = RKX11x_HAL_CRU_ClkSetFreq(hw, pll, pRate); - if (ret != HAL_OK) { - return ret; + if (!rate || rate > _MHZ(1200)) + return HAL_ERROR; + for (i = _MHZ(1200) / rate; i > _MHZ(24) / rate; i--) { + pRate = i * rate; + ret = RKX11x_HAL_CRU_ClkSetFreq(hw, pll, pRate); + if (ret == HAL_OK) + break; + } + if (ret != HAL_OK) + return ret; + } else { + ret = RKX11x_HAL_CRU_ClkSetFreq(hw, pll, pRate); + if (ret != HAL_OK) { + return ret; + } } /* if success, continue to set divider */ diff --git a/drivers/mfd/rkx110_x120/hal/cru_rkx120.c b/drivers/mfd/rkx110_x120/hal/cru_rkx120.c index 07da30ba0fd4..025a913626f8 100644 --- a/drivers/mfd/rkx110_x120/hal/cru_rkx120.c +++ b/drivers/mfd/rkx110_x120/hal/cru_rkx120.c @@ -252,6 +252,7 @@ static HAL_Status RKX12x_HAL_CRU_ClkSetFreq(struct hwclk *hw, uint32_t clockName uint32_t pll; uint8_t overMax; HAL_Status ret = HAL_OK; + int i; switch (clockName) { case RKX120_CPS_PLL_TXPLL: @@ -298,12 +299,21 @@ static HAL_Status RKX12x_HAL_CRU_ClkSetFreq(struct hwclk *hw, uint32_t clockName /* PLL change closest new rate <= 1200M if need */ if (!pRate) { - pRate = (_MHZ(1200) / rate) * rate; - } - - ret = RKX12x_HAL_CRU_ClkSetFreq(hw, pll, pRate); - if (ret != HAL_OK) { - return ret; + if (!rate || rate > _MHZ(1200)) + return HAL_ERROR; + for (i = _MHZ(1200) / rate; i > _MHZ(24) / rate; i--) { + pRate = i * rate; + ret = RKX12x_HAL_CRU_ClkSetFreq(hw, pll, pRate); + if (ret == HAL_OK) + break; + } + if (ret != HAL_OK) + return ret; + } else { + ret = RKX12x_HAL_CRU_ClkSetFreq(hw, pll, pRate); + if (ret != HAL_OK) { + return ret; + } } /* if success, continue to set divider */ diff --git a/drivers/mfd/rkx110_x120/hal/cru_rkx121.c b/drivers/mfd/rkx110_x120/hal/cru_rkx121.c index 350ce6c47f48..dfa1c62a30bd 100644 --- a/drivers/mfd/rkx110_x120/hal/cru_rkx121.c +++ b/drivers/mfd/rkx110_x120/hal/cru_rkx121.c @@ -263,6 +263,7 @@ static HAL_Status RKX12x_HAL_CRU_ClkSetFreq(struct hwclk *hw, uint32_t clockName uint32_t pll; uint8_t overMax; HAL_Status ret = HAL_OK; + int i; switch (clockName) { case RKX120_CPS_PLL_TXPLL: @@ -309,12 +310,21 @@ static HAL_Status RKX12x_HAL_CRU_ClkSetFreq(struct hwclk *hw, uint32_t clockName /* PLL change closest new rate <= 1200M if need */ if (!pRate) { - pRate = (_MHZ(1200) / rate) * rate; - } - - ret = RKX12x_HAL_CRU_ClkSetFreq(hw, pll, pRate); - if (ret != HAL_OK) { - return ret; + if (!rate || rate > _MHZ(1200)) + return HAL_ERROR; + for (i = _MHZ(1200) / rate; i > _MHZ(24) / rate; i--) { + pRate = i * rate; + ret = RKX12x_HAL_CRU_ClkSetFreq(hw, pll, pRate); + if (ret == HAL_OK) + break; + } + if (ret != HAL_OK) + return ret; + } else { + ret = RKX12x_HAL_CRU_ClkSetFreq(hw, pll, pRate); + if (ret != HAL_OK) { + return ret; + } } /* if success, continue to set divider */ From 08c66b08ce17798f3bbdcdee5b247628817f91d3 Mon Sep 17 00:00:00 2001 From: Cai YiWei Date: Wed, 3 Jan 2024 12:01:02 +0800 Subject: [PATCH 21/22] media: rockchip: isp: sync irq_ends irqs in different cpu will change irq_ends flag, lock to sync. Change-Id: Ie5467825173a16c796c7ab84c15286af44edc5d9 Signed-off-by: Cai YiWei --- drivers/media/platform/rockchip/isp/rkisp.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/rockchip/isp/rkisp.c b/drivers/media/platform/rockchip/isp/rkisp.c index c9ffd1ed9094..c3eda3fa3fec 100644 --- a/drivers/media/platform/rockchip/isp/rkisp.c +++ b/drivers/media/platform/rockchip/isp/rkisp.c @@ -1072,8 +1072,10 @@ static void rkisp_rdbk_work(struct work_struct *work) void rkisp_check_idle(struct rkisp_device *dev, u32 irq) { + unsigned long lock_flags = 0; u32 val = 0; + spin_lock_irqsave(&dev->hw_dev->rdbk_lock, lock_flags); dev->irq_ends |= (irq & dev->irq_ends_mask); v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev, "%s irq:0x%x ends:0x%x mask:0x%x\n", @@ -1085,8 +1087,11 @@ void rkisp_check_idle(struct rkisp_device *dev, u32 irq) complete(&dev->hw_dev->monitor.cmpl); } if ((dev->irq_ends & dev->irq_ends_mask) != dev->irq_ends_mask || - !IS_HDR_RDBK(dev->rd_mode)) + !IS_HDR_RDBK(dev->rd_mode)) { + spin_unlock_irqrestore(&dev->hw_dev->rdbk_lock, lock_flags); return; + } + spin_unlock_irqrestore(&dev->hw_dev->rdbk_lock, lock_flags); if (dev->sw_rd_cnt) goto end; From b0b2892b93ae8223f3cbef733c497029a449cd50 Mon Sep 17 00:00:00 2001 From: Hisping Lin Date: Thu, 11 Jan 2024 17:33:30 +0800 Subject: [PATCH 22/22] tee: optee: interrupt an RPC depend on shutdown flag Change-Id: I33f33af02afb75bda5d68c9731fe636bb97132fe Signed-off-by: Hisping Lin --- drivers/tee/optee/optee_private.h | 1 + drivers/tee/optee/smc_abi.c | 6 ++++++ drivers/tee/optee/supp.c | 13 +++++-------- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/tee/optee/optee_private.h b/drivers/tee/optee/optee_private.h index 04ae58892608..c2a9c987092c 100644 --- a/drivers/tee/optee/optee_private.h +++ b/drivers/tee/optee/optee_private.h @@ -92,6 +92,7 @@ struct optee_supp { struct list_head reqs; struct idr idr; struct completion reqs_c; + bool shutdown; }; struct optee_smc { diff --git a/drivers/tee/optee/smc_abi.c b/drivers/tee/optee/smc_abi.c index e6e0428f8e7b..fd082216f0eb 100644 --- a/drivers/tee/optee/smc_abi.c +++ b/drivers/tee/optee/smc_abi.c @@ -7,6 +7,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include +#include #include #include #include @@ -1352,6 +1353,11 @@ static void optee_shutdown(struct platform_device *pdev) { struct optee *optee = platform_get_drvdata(pdev); + /* Tell requesting thread to interrupt an RPC */ + smp_store_mb(optee->supp.shutdown, true); + /* Wait requesting thread to release resources */ + mdelay(200); + if (!optee->rpc_param_count) optee_disable_shm_cache(optee); } diff --git a/drivers/tee/optee/supp.c b/drivers/tee/optee/supp.c index 2d556b79a67e..a8656a72d83a 100644 --- a/drivers/tee/optee/supp.c +++ b/drivers/tee/optee/supp.c @@ -82,7 +82,6 @@ u32 optee_supp_thrd_req(struct tee_context *ctx, u32 func, size_t num_params, struct optee_supp_req *req; bool interruptable; u32 ret; - unsigned long timeleft; int id; struct optee_supp_req *get_req; @@ -117,14 +116,12 @@ u32 optee_supp_thrd_req(struct tee_context *ctx, u32 func, size_t num_params, * exclusive access again. */ while (wait_for_completion_interruptible(&req->c)) { - pr_err("Warning, Interrupting an RPC to supplicant!\n"); - timeleft = wait_for_completion_timeout(&req->c, msecs_to_jiffies(2000)); - if (timeleft) { - /* get completion, it means tee-supplicant is alive. */ - break; - } else { - /* timeout, it means tee-supplicant is dead, interrupting an RPC. */ + if (supp->shutdown) { + /* Reboot happen, tee-supplicant is dead, interrupt an RPC */ interruptable = true; + } else { + /* Deep sleep, tee-supplicant is freeze, wait tee-supplicant */ + continue; } mutex_lock(&supp->mutex);