From 11162a3487bdb8d69b5e2572d10ef1aceccf9947 Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Wed, 7 Sep 2022 15:46:08 +0800 Subject: [PATCH] clk: rockchip: rk3588: Add CLK_SET_RATE_PARENT for i2s5/6 frac clk The flag was missing which makes i2s5/6 src clock rate can't be changed. Change-Id: I3ad5f39e8a2826d0b18d554c3a53b55f219028d8 Signed-off-by: Joseph Chen --- drivers/clk/rockchip/clk-rk3588.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index 10e9b8d915e2..99bb5111d695 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -1996,7 +1996,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(CLK_I2S5_8CH_TX_SRC, "clk_i2s5_8ch_tx_src", gpll_aupll_p, 0, RK3588_CLKSEL_CON(140), 10, 1, MFLAGS, 5, 5, DFLAGS, RK3588_CLKGATE_CON(62), 6, GFLAGS), - COMPOSITE_FRACMUX(CLK_I2S5_8CH_TX_FRAC, "clk_i2s5_8ch_tx_frac", "clk_i2s5_8ch_tx_src", 0, + COMPOSITE_FRACMUX(CLK_I2S5_8CH_TX_FRAC, "clk_i2s5_8ch_tx_frac", "clk_i2s5_8ch_tx_src", CLK_SET_RATE_PARENT, RK3588_CLKSEL_CON(141), 0, RK3588_CLKGATE_CON(62), 7, GFLAGS, &rk3588_i2s5_8ch_tx_fracmux), @@ -2014,7 +2014,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(CLK_I2S6_8CH_RX_SRC, "clk_i2s6_8ch_rx_src", gpll_aupll_p, 0, RK3588_CLKSEL_CON(146), 7, 1, MFLAGS, 2, 5, DFLAGS, RK3588_CLKGATE_CON(63), 0, GFLAGS), - COMPOSITE_FRACMUX(CLK_I2S6_8CH_RX_FRAC, "clk_i2s6_8ch_rx_frac", "clk_i2s6_8ch_rx_src", 0, + COMPOSITE_FRACMUX(CLK_I2S6_8CH_RX_FRAC, "clk_i2s6_8ch_rx_frac", "clk_i2s6_8ch_rx_src", CLK_SET_RATE_PARENT, RK3588_CLKSEL_CON(147), 0, RK3588_CLKGATE_CON(63), 1, GFLAGS, &rk3588_i2s6_8ch_rx_fracmux),