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dv: The first frame is abnormal when play video [1/1]
PD#SWPL-6480 Problem: core1 reg is set wrong for g12 and tm2 Solution: correct core1 reg for g12 and tm2 Verify: verified by u212 Change-Id: Ie9de107fce6f23ded1397827ebe95a00939df8c1 Signed-off-by: yao liu <yao.liu@amlogic.com>
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@@ -2002,7 +2002,7 @@ static int dolby_core1_set(
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}
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if (dolby_vision_on_count
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<= dolby_vision_run_mode_delay) {
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< dolby_vision_run_mode_delay) {
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VSYNC_WR_DV_REG(
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VPP_VD1_CLIP_MISC0,
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(0x200 << 10) | 0x200);
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@@ -3228,18 +3228,30 @@ void enable_dolby_vision(int enable)
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if (!dolby_vision_core1_on
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&& (dolby_vision_mask & 1)
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&& dovi_setting_video_flag) {
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VSYNC_WR_DV_REG_BITS(
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VIU_MISC_CTRL1,
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0,
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16, 1); /* core1 */
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if (is_meson_g12() || is_meson_tm2_stbmode())
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VSYNC_WR_DV_REG_BITS(
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DOLBY_PATH_CTRL,
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/* enable core1 */
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0, 0, 1);
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else
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VSYNC_WR_DV_REG_BITS(
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VIU_MISC_CTRL1,
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0,
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16, 1); /* core1 */
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dolby_vision_core1_on = true;
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} else if (dolby_vision_core1_on
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&& (!(dolby_vision_mask & 1)
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|| !dovi_setting_video_flag)){
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VSYNC_WR_DV_REG_BITS(
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VIU_MISC_CTRL1,
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1,
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16, 1); /* core1 */
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|| !dovi_setting_video_flag)) {
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if (is_meson_g12() || is_meson_tm2_stbmode())
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VSYNC_WR_DV_REG_BITS(
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DOLBY_PATH_CTRL,
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/* disable core1 */
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1, 0, 1);
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else
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VSYNC_WR_DV_REG_BITS(
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VIU_MISC_CTRL1,
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1,
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16, 1); /* core1 */
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dolby_vision_core1_on = false;
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}
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}
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