diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index ccce7a928fc8..4f24351c5cef 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -3168,10 +3168,11 @@ static void vop_mcu_mode_setup(struct drm_crtc *crtc)
 	VOP_CTRL_SET(vop, mcu_rw_pend, vop->mcu_timing.mcu_rw_pend);
 }
 
-static void vop_crtc_send_mcu_cmd(struct drm_crtc *crtc,  u32 type, u32 value)
+static void vop_crtc_send_mcu_cmd(struct drm_crtc *crtc, u32 type, u32 value)
 {
 	struct drm_display_mode *adjusted_mode;
 	struct vop *vop = NULL;
+	uint32_t val = 0;
 
 	if (!crtc)
 		return;
@@ -3200,6 +3201,11 @@ static void vop_crtc_send_mcu_cmd(struct drm_crtc *crtc,  u32 type, u32 value)
 			VOP_CTRL_SET(vop, mcu_rs, 1);
 			VOP_CTRL_SET(vop, mcu_rw_bypass_port, value);
 			break;
+		case MCU_RDDATA:
+			VOP_CTRL_SET(vop, mcu_rs, 1);
+			val = VOP_CTRL_GET(vop, mcu_rw_bypass_port);
+			DRM_DEBUG_DRIVER("mcu read reg[0x%02x] = 0x%02x", value, val);
+			break;
 		case MCU_SETBYPASS:
 			VOP_CTRL_SET(vop, mcu_bypass, value ? 1 : 0);
 			break;
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index aa84d7619eeb..ee86f0184afa 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -694,6 +694,7 @@ enum _vop_rgb2rgb_conv_mode {
 enum _MCU_IOCTL {
 	MCU_WRCMD = 0,
 	MCU_WRDATA,
+	MCU_RDDATA,
 	MCU_SETBYPASS,
 };