From 118ff760f97a8995bb7ce33de40af50b746a018e Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 20 Jun 2018 14:37:55 +0800 Subject: [PATCH] clk: rockchip: Fix rk3036 pll rate overflow calculation on 32-bit Change-Id: I4e367893e97828b01b3e6ec457714c722d2c0af6 Signed-off-by: Finley Xiao Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-pll.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index a04b1b61e5a2..ca56cb69d17d 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -374,7 +374,7 @@ static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw, { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); struct rockchip_pll_rate_table cur; - u64 rate64 = prate; + u64 rate64 = prate, frac_rate64 = prate; if (pll->sel && pll->scaling) return pll->scaling; @@ -386,7 +386,7 @@ static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw, if (cur.dsmpd == 0) { /* fractional mode */ - u64 frac_rate64 = prate * cur.frac; + frac_rate64 *= cur.frac; do_div(frac_rate64, cur.refdiv); rate64 += frac_rate64 >> 24;