diff --git a/drivers/media/platform/rockchip/isp/capture.c b/drivers/media/platform/rockchip/isp/capture.c index af9eecf50b9a..b40f65d785b4 100644 --- a/drivers/media/platform/rockchip/isp/capture.c +++ b/drivers/media/platform/rockchip/isp/capture.c @@ -657,6 +657,7 @@ static struct stream_config rkisp2_dmatx0_stream_config = { .y_size_init = MI_RAW0_WR_SIZE, .y_base_ad_init = MI_RAW0_WR_BASE, .y_base_ad_shd = MI_RAW0_WR_BASE_SHD, + .length = MI_RAW0_WR_LENGTH, }, .dma = { .ctrl = CSI2RX_RAW0_WR_CTRL, @@ -673,6 +674,7 @@ static struct stream_config rkisp2_dmatx1_stream_config = { .y_size_init = MI_RAW1_WR_SIZE, .y_base_ad_init = MI_RAW1_WR_BASE, .y_base_ad_shd = MI_RAW1_WR_BASE_SHD, + .length = MI_RAW1_WR_LENGTH, }, .dma = { .ctrl = CSI2RX_RAW1_WR_CTRL, @@ -689,6 +691,7 @@ static struct stream_config rkisp2_dmatx2_stream_config = { .y_size_init = MI_RAW2_WR_SIZE, .y_base_ad_init = MI_RAW2_WR_BASE, .y_base_ad_shd = MI_RAW2_WR_BASE_SHD, + .length = MI_RAW2_WR_LENGTH, }, .dma = { .ctrl = CSI2RX_RAW2_WR_CTRL, @@ -705,6 +708,7 @@ static struct stream_config rkisp2_dmatx3_stream_config = { .y_size_init = MI_RAW3_WR_SIZE, .y_base_ad_init = MI_RAW3_WR_BASE, .y_base_ad_shd = MI_RAW3_WR_BASE_SHD, + .length = MI_RAW3_WR_LENGTH, }, .dma = { .ctrl = CSI2RX_RAW3_WR_CTRL, @@ -1058,7 +1062,7 @@ static int dmatx3_config_mi(struct rkisp_stream *stream) mi_frame_end(stream); mi_frame_end_int_enable(stream); mi_wr_ctrl2(base, SW_RAW3_WR_AUTOUPD); - + mi_raw_length(stream); v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev, "rawwr3 %dx%d ctrl:0x%x\n", stream->out_fmt.width, @@ -1105,6 +1109,7 @@ static int dmatx2_config_mi(struct rkisp_stream *stream) mi_frame_end(stream); mi_frame_end_int_enable(stream); mi_wr_ctrl2(base, SW_RAW2_WR_AUTOUPD); + mi_raw_length(stream); stream->u.dmatx.is_config = true; } return 0; @@ -1148,6 +1153,7 @@ static int dmatx1_config_mi(struct rkisp_stream *stream) mi_frame_end(stream); mi_frame_end_int_enable(stream); mi_wr_ctrl2(base, SW_RAW1_WR_AUTOUPD); + mi_raw_length(stream); stream->u.dmatx.is_config = true; } return 0; @@ -1196,6 +1202,7 @@ static int dmatx0_config_mi(struct rkisp_stream *stream) mi_frame_end(dmatx); mi_frame_end_int_enable(dmatx); mi_wr_ctrl2(base, SW_RAW0_WR_AUTOUPD); + mi_raw_length(stream); dmatx->u.dmatx.is_config = true; } else { dmatx0_set_pic_size(base, @@ -1900,8 +1907,15 @@ int hdr_config_dmatx(struct rkisp_device *dev) dev->hdr.op_mode == HDR_RDBK_FRAME3) dmatx2_config_mi(&dev->cap_dev.stream[RKISP_STREAM_DMATX2]); - if (IS_HDR_RDBK(dev->hdr.op_mode)) + if (IS_HDR_RDBK(dev->hdr.op_mode) && !dev->dmarx_dev.trigger) { raw_rd_ctrl(dev->base_addr, dev->csi_dev.memory << 2); + mi_raw_length(&dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2]); + if (dev->hdr.op_mode == HDR_RDBK_FRAME3) + mi_raw_length(&dev->dmarx_dev.stream[RKISP_STREAM_RAWRD1]); + if (dev->hdr.op_mode == HDR_RDBK_FRAME3 || + dev->hdr.op_mode == HDR_RDBK_FRAME2) + mi_raw_length(&dev->dmarx_dev.stream[RKISP_STREAM_RAWRD0]); + } return 0; } @@ -2547,10 +2561,9 @@ static int rkisp_set_fmt(struct rkisp_stream *stream, stream->id != RKISP_STREAM_MP && stream->id != RKISP_STREAM_SP) /* compact mode need bytesperline 4byte align */ - bytesperline = ALIGN(width * fmt->bpp[i] / 8, 4); + bytesperline = ALIGN(width * fmt->bpp[i] / 8, 256); else bytesperline = width * DIV_ROUND_UP(fmt->bpp[i], 8); - /* stride is only available for sp stream and y plane */ if (stream->id != RKISP_STREAM_SP || i != 0 || plane_fmt->bytesperline < bytesperline) diff --git a/drivers/media/platform/rockchip/isp/capture.h b/drivers/media/platform/rockchip/isp/capture.h index 55bd86b0ee90..455d2754c5fb 100644 --- a/drivers/media/platform/rockchip/isp/capture.h +++ b/drivers/media/platform/rockchip/isp/capture.h @@ -157,6 +157,7 @@ struct stream_config { u32 cb_offs_cnt_init; u32 cr_offs_cnt_init; u32 y_base_ad_shd; + u32 length; } mi; struct { u32 ctrl; diff --git a/drivers/media/platform/rockchip/isp/dmarx.c b/drivers/media/platform/rockchip/isp/dmarx.c index 2ce6c11f383a..1b2b0eabab4d 100644 --- a/drivers/media/platform/rockchip/isp/dmarx.c +++ b/drivers/media/platform/rockchip/isp/dmarx.c @@ -197,6 +197,7 @@ static struct stream_config rkisp2_dmarx0_stream_config = { .mi = { .y_base_ad_init = MI_RAW0_RD_BASE, .y_base_ad_shd = MI_RAW0_RD_BASE_SHD, + .length = MI_RAW0_RD_LENGTH, }, }; @@ -207,6 +208,7 @@ static struct stream_config rkisp2_dmarx1_stream_config = { .mi = { .y_base_ad_init = MI_RAW1_RD_BASE, .y_base_ad_shd = MI_RAW1_RD_BASE_SHD, + .length = MI_RAW1_RD_LENGTH, }, }; @@ -217,6 +219,7 @@ static struct stream_config rkisp2_dmarx2_stream_config = { .mi = { .y_base_ad_init = MI_RAW2_RD_BASE, .y_base_ad_shd = MI_RAW2_RD_BASE_SHD, + .length = MI_RAW2_RD_LENGTH, }, }; @@ -321,7 +324,7 @@ static int rawrd_config_mi(struct rkisp_stream *stream) rkisp_set_bits(dev, CSI2RX_RAW_RD_CTRL, 0, dev->csi_dev.memory << 2 | 1 << (stream->id - 1), true); - + mi_raw_length(stream); v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev, "%s id:%d 0x%x %dx%d\n", __func__, stream->id, val, @@ -656,7 +659,7 @@ static int rkisp_set_fmt(struct rkisp_stream *stream, if (stream->ispdev->isp_ver == ISP_V20 && !stream->ispdev->csi_dev.memory && stream->id != RKISP_STREAM_DMARX) - bytesperline = width * fmt->bpp[i] / 8; + bytesperline = ALIGN(width * fmt->bpp[i] / 8, 256); else bytesperline = width * DIV_ROUND_UP(fmt->bpp[i], 8); /* stride is only available for sp stream and y plane */ diff --git a/drivers/media/platform/rockchip/isp/regs_v2x.h b/drivers/media/platform/rockchip/isp/regs_v2x.h index 44bb83f1f7f0..647683a80cf8 100644 --- a/drivers/media/platform/rockchip/isp/regs_v2x.h +++ b/drivers/media/platform/rockchip/isp/regs_v2x.h @@ -2132,4 +2132,16 @@ static inline void raw_rd_ctrl(void __iomem *base, u32 val) writel(val, base + CSI2RX_RAW_RD_CTRL); } +static inline void mi_raw_length(struct rkisp_stream *stream) +{ + bool is_direct = true; + + if (stream->config->mi.length == MI_RAW0_RD_LENGTH || + stream->config->mi.length == MI_RAW1_RD_LENGTH || + stream->config->mi.length == MI_RAW2_RD_LENGTH) + is_direct = false; + rkisp_write(stream->ispdev, stream->config->mi.length, + stream->out_fmt.plane_fmt[0].bytesperline, is_direct); +} + #endif /* _RKISP_REGS_V2X_H */