From 11ee607656e7f163bd313cc6eea63fa05baf3f53 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Fri, 27 May 2022 11:14:19 +0800 Subject: [PATCH] media: rockchip: vicap optimize print of csi2 Signed-off-by: Zefa Chen Change-Id: I95e4b2d7a65f25074ee196af6cada345b7462ba3 --- .../media/platform/rockchip/cif/mipi-csi2.c | 90 ++++++++++++------- .../media/platform/rockchip/cif/mipi-csi2.h | 7 +- 2 files changed, 62 insertions(+), 35 deletions(-) diff --git a/drivers/media/platform/rockchip/cif/mipi-csi2.c b/drivers/media/platform/rockchip/cif/mipi-csi2.c index b7fd62452bcb..70bbc18517f4 100644 --- a/drivers/media/platform/rockchip/cif/mipi-csi2.c +++ b/drivers/media/platform/rockchip/cif/mipi-csi2.c @@ -625,6 +625,17 @@ v4l2_async_notifier_operations csi2_async_ops = { .unbind = csi2_notifier_unbind, }; +static void csi2_find_err_vc(int val, char *vc_info) +{ + int i; + + memset(vc_info, 0, sizeof(*vc_info)); + for (i = 0; i < 4; i++) { + if ((val >> i) & 0x1) + snprintf(vc_info, CSI_VCINFO_LEN, "%s %d", vc_info, i); + } +} + static irqreturn_t rk_csirx_irq1_handler(int irq, void *ctx) { struct device *dev = ctx; @@ -632,63 +643,67 @@ static irqreturn_t rk_csirx_irq1_handler(int irq, void *ctx) struct csi2_err_stats *err_list = NULL; unsigned long err_stat = 0; u32 val; + char err_str[CSI_ERRSTR_LEN] = {0}; + char vc_info[CSI_VCINFO_LEN] = {0}; val = read_csihost_reg(csi2->base, CSIHOST_ERR1); if (val) { - write_csihost_reg(csi2->base, - CSIHOST_ERR1, 0x0); if (val & CSIHOST_ERR1_PHYERR_SPTSYNCHS) { err_list = &csi2->err_list[RK_CSI2_ERR_SOTSYN]; err_list->cnt++; if (csi2->match_data->chip_id == CHIP_RK3588_CSI2) { if (csi2->err_list[RK_CSI2_ERR_ALL].cnt > err_list->cnt) { - dev_err(csi2->dev, - "ERR1: start of transmission error(no synchronization achieved), reg: 0x%x,cnt:%d\n", - val, err_list->cnt); + csi2_find_err_vc(val & 0xf, vc_info); + snprintf(err_str, CSI_ERRSTR_LEN, "%s(sot sync,lane:%s) ", err_str, vc_info); } else { if (csi2->is_check_sot_sync) { + csi2_find_err_vc(val & 0xf, vc_info); + snprintf(err_str, CSI_ERRSTR_LEN, "%s(sot sync,lane:%s) ", err_str, vc_info); write_csihost_reg(csi2->base, CSIHOST_MSK1, 0xf); csi2->is_check_sot_sync = false; } } } else { - dev_err(csi2->dev, - "ERR1: start of transmission error(no synchronization achieved), reg: 0x%x,cnt:%d\n", - val, err_list->cnt); + csi2_find_err_vc(val & 0xf, vc_info); + snprintf(err_str, CSI_ERRSTR_LEN, "%s(sot sync,lane:%s) ", err_str, vc_info); } } if (val & CSIHOST_ERR1_ERR_BNDRY_MATCH) { err_list = &csi2->err_list[RK_CSI2_ERR_FS_FE_MIS]; err_list->cnt++; - dev_err(csi2->dev, - "ERR1: error matching frame start with frame end, reg: 0x%x,cnt:%d\n", - val, err_list->cnt); + csi2_find_err_vc((val >> 4) & 0xf, vc_info); + snprintf(err_str, CSI_ERRSTR_LEN, "%s(fs/fe mis,vc:%s) ", err_str, vc_info); } if (val & CSIHOST_ERR1_ERR_SEQ) { err_list = &csi2->err_list[RK_CSI2_ERR_FRM_SEQ_ERR]; err_list->cnt++; - dev_err(csi2->dev, - "ERR1: incorrect frame sequence detected, reg: 0x%x,cnt:%d\n", - val, err_list->cnt); + csi2_find_err_vc((val >> 8) & 0xf, vc_info); + snprintf(err_str, CSI_ERRSTR_LEN, "%s(f_seq,vc:%s) ", err_str, vc_info); } if (val & CSIHOST_ERR1_ERR_FRM_DATA) { err_list = &csi2->err_list[RK_CSI2_ERR_CRC_ONCE]; err_list->cnt++; - v4l2_dbg(1, csi2_debug, &csi2->sd, - "ERR1: at least one crc error, reg: 0x%x\n,cnt:%d", val, err_list->cnt); + csi2_find_err_vc((val >> 12) & 0xf, vc_info); + snprintf(err_str, CSI_ERRSTR_LEN, "%s(err_data,vc:%s) ", err_str, vc_info); } if (val & CSIHOST_ERR1_ERR_CRC) { err_list = &csi2->err_list[RK_CSI2_ERR_CRC]; err_list->cnt++; - dev_err(csi2->dev, - "ERR1: crc errors, reg: 0x%x, cnt:%d\n", - val, err_list->cnt); + csi2_find_err_vc((val >> 24) & 0xf, vc_info); + snprintf(err_str, CSI_ERRSTR_LEN, "%s(crc,vc:%s) ", err_str, vc_info); } + if (val & CSIHOST_ERR1_ERR_ECC2) { + err_list = &csi2->err_list[RK_CSI2_ERR_CRC]; + err_list->cnt++; + snprintf(err_str, CSI_ERRSTR_LEN, "%s(ecc2)", err_str); + } + + pr_err("%s ERR1:0x%x %s\n", csi2->dev_name, val, err_str); csi2->err_list[RK_CSI2_ERR_ALL].cnt++; err_stat = ((csi2->err_list[RK_CSI2_ERR_FS_FE_MIS].cnt & 0xff) << 8) | ((csi2->err_list[RK_CSI2_ERR_ALL].cnt) & 0xff); @@ -707,25 +722,31 @@ static irqreturn_t rk_csirx_irq2_handler(int irq, void *ctx) struct device *dev = ctx; struct csi2_dev *csi2 = sd_to_dev(dev_get_drvdata(dev)); u32 val; + char err_str[CSI_ERRSTR_LEN] = {0}; + char vc_info[CSI_VCINFO_LEN] = {0}; val = read_csihost_reg(csi2->base, CSIHOST_ERR2); if (val) { - if (val & CSIHOST_ERR2_PHYERR_ESC) - dev_err(csi2->dev, "ERR2: escape entry error(ULPM), reg: 0x%x\n", val); - if (val & CSIHOST_ERR2_PHYERR_SOTHS) - dev_err(csi2->dev, - "ERR2: start of transmission error(synchronization can still be achieved), reg: 0x%x\n", - val); - if (val & CSIHOST_ERR2_ECC_CORRECTED) - v4l2_dbg(1, csi2_debug, &csi2->sd, - "ERR2: header error detected and corrected, reg: 0x%x\n", - val); - if (val & CSIHOST_ERR2_ERR_ID) - dev_err(csi2->dev, - "ERR2: unrecognized or unimplemented data type detected, reg: 0x%x\n", - val); + if (val & CSIHOST_ERR2_PHYERR_ESC) { + csi2_find_err_vc(val & 0xf, vc_info); + snprintf(err_str, CSI_ERRSTR_LEN, "%s(ULPM,lane:%s) ", err_str, vc_info); + } + if (val & CSIHOST_ERR2_PHYERR_SOTHS) { + csi2_find_err_vc((val >> 4) & 0xf, vc_info); + snprintf(err_str, CSI_ERRSTR_LEN, "%s(sot,lane:%s) ", err_str, vc_info); + } + if (val & CSIHOST_ERR2_ECC_CORRECTED) { + csi2_find_err_vc((val >> 8) & 0xf, vc_info); + snprintf(err_str, CSI_ERRSTR_LEN, "%s(ecc,vc:%s) ", err_str, vc_info); + } + if (val & CSIHOST_ERR2_ERR_ID) { + csi2_find_err_vc((val >> 12) & 0xf, vc_info); + snprintf(err_str, CSI_ERRSTR_LEN, "%s(err id,vc:%s) ", err_str, vc_info); + } if (val & CSIHOST_ERR2_PHYERR_CODEHS) - dev_err(csi2->dev, "ERR2: receiv error code, reg: 0x%x\n", val); + snprintf(err_str, CSI_ERRSTR_LEN, "%s(err code) ", err_str); + + pr_err("%s ERR2:0x%x %s\n", csi2->dev_name, val, err_str); } return IRQ_HANDLED; @@ -833,6 +854,7 @@ static int csi2_probe(struct platform_device *pdev) csi2->dev = &pdev->dev; csi2->match_data = data; + csi2->dev_name = node->name; v4l2_subdev_init(&csi2->sd, &csi2_subdev_ops); v4l2_set_subdevdata(&csi2->sd, &pdev->dev); csi2->sd.entity.ops = &csi2_entity_ops; diff --git a/drivers/media/platform/rockchip/cif/mipi-csi2.h b/drivers/media/platform/rockchip/cif/mipi-csi2.h index eb64659a7770..fa4ff8fc2df2 100644 --- a/drivers/media/platform/rockchip/cif/mipi-csi2.h +++ b/drivers/media/platform/rockchip/cif/mipi-csi2.h @@ -29,6 +29,9 @@ #define RKCIF_DEFAULT_WIDTH 640 #define RKCIF_DEFAULT_HEIGHT 480 +#define CSI_ERRSTR_LEN (128) +#define CSI_VCINFO_LEN (12) + /* * The default maximum bit-rate per lane in Mbps, if the * source subdev does not provide V4L2_CID_LINK_FREQ. @@ -56,7 +59,8 @@ #define CSIHOST_ERR1_ERR_BNDRY_MATCH 0x000000f0 #define CSIHOST_ERR1_ERR_SEQ 0x00000f00 #define CSIHOST_ERR1_ERR_FRM_DATA 0x0000f000 -#define CSIHOST_ERR1_ERR_CRC 0x1f000000 +#define CSIHOST_ERR1_ERR_CRC 0x0f000000 +#define CSIHOST_ERR1_ERR_ECC2 0x10000000 #define CSIHOST_ERR2_PHYERR_ESC 0x0000000f #define CSIHOST_ERR2_PHYERR_SOTHS 0x000000f0 @@ -151,6 +155,7 @@ struct csi2_dev { int irq1; int irq2; bool is_check_sot_sync; + const char *dev_name; }; u32 rkcif_csi2_get_sof(struct csi2_dev *csi2_dev);