shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-03-25 12:00:22 +09:00
Code Issues Packages Projects Releases Wiki Activity

clk: qcom: gcc-qcs404: fix names of the DSI clocks used as parents

Browse Source 
[ Upstream commit 47d94d30cd ]

The QCS404 uses 28nm LPM DSI PHY, which registers dsi0pll and
dsi0pllbyte clocks. Fix all DSI PHY clock names used as parents inside
the GCC driver.

Fixes: 652f1813c1 ("clk: qcom: gcc: Add global clock controller driver for QCS404")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221226042154.2666748-7-dmitry.baryshkov@linaro.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Dmitry Baryshkov
2022-12-26 06:21:44 +02:00
committed by Greg Kroah-Hartman
parent 9fcba5e7bb
commit 11fcd28df8
1 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/clk/qcom/gcc-qcs404.c
View File

@@ -112,7 +112,7 @@ static const struct parent_map gcc_parent_map_5[] = {
static const char * const gcc_parent_names_5[] = {
"cxo",
"dsi0pll_byteclk_src",
"dsi0pllbyte",
"core_bi_pll_test_se",
};
@@ -124,7 +124,7 @@ static const struct parent_map gcc_parent_map_6[] = {
static const char * const gcc_parent_names_6[] = {
"cxo",
"dsi0_phy_pll_out_byteclk",
"dsi0pllbyte",
"core_bi_pll_test_se",
};
@@ -167,7 +167,7 @@ static const struct parent_map gcc_parent_map_9[] = {
static const char * const gcc_parent_names_9[] = {
"cxo",
"gpll0_out_main",
"dsi0_phy_pll_out_dsiclk",
"dsi0pll",
"gpll6_out_aux",
"core_bi_pll_test_se",
};
@@ -204,7 +204,7 @@ static const struct parent_map gcc_parent_map_12[] = {
static const char * const gcc_parent_names_12[] = {
"cxo",
"dsi0pll_pclk_src",
"dsi0pll",
"core_bi_pll_test_se",
};