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clk: rockchip: add some clock IDs for reference

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Change-Id: I8ce291b7145a56aea9d8f5b5742506a581f26912
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This commit is contained in:
Xing Zheng
2016-03-23 11:01:02 +08:00
committed by Huang, Tao
parent 6d3b3d984d
commit 120126f7d1
2 changed files with 12 additions and 6 deletions
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12
drivers/clk/rockchip/clk-rk3399.c
View File

@@ -948,7 +948,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKGATE_CON(7), 6, GFLAGS),
GATE(0, "gpll_fclk_cm0s_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(7), 5, GFLAGS),
COMPOSITE(0, "fclk_cm0s", mux_fclk_cm0s_p, CLK_IGNORE_UNUSED,
COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(7), 9, GFLAGS),
@@ -1182,7 +1182,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(11), 4, GFLAGS),
COMPOSITE(SCLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(12), 10, GFLAGS),
COMPOSITE_NOMUX(0, "hclk_isp1", "aclk_isp1", 0,
@@ -1220,7 +1220,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKSEL_CON(56), 5, 1, MFLAGS),
/* gic */
COMPOSITE(0, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(12), 12, GFLAGS),
@@ -1233,7 +1233,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
/* alive */
/* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */
DIV(0, "pclk_alive", "gpll", 0,
DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,
RK3399_CLKSEL_CON(57), 0, 5, DFLAGS),
GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS),
@@ -1345,7 +1345,7 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(0), 1, GFLAGS),
COMPOSITE_NOGATE(0, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, CLK_IGNORE_UNUSED,
COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, CLK_IGNORE_UNUSED,
@@ -1389,7 +1389,7 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
RK3399_CLKGATE_CON(0), 6, GFLAGS,
&rk3399_uart4_pmu_fracmux),
DIV(0, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED,
DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(0), 0, 5, DFLAGS),
/* pmu clock gates */

6
include/dt-bindings/clock/rk3399-cru.h
View File

@@ -135,6 +135,8 @@
#define DCLK_VOP1 181
#define DCLK_M0_PERILP 182
#define FCLK_CM0S 190
/* aclk gates */
#define ACLK_PERIHP 192
#define ACLK_PERIHP_NOC 193
@@ -206,6 +208,7 @@
#define ACLK_ADB400M_PD_CORE_B 259
#define ACLK_PERF_CORE_L 260
#define ACLK_PERF_CORE_B 261
#define ACLK_GIC_PRE 262
/* pclk gates */
#define PCLK_PERIHP 320
@@ -278,6 +281,7 @@
#define PCLK_UPHY0_TCPD_G 387
#define PCLK_UPHY1_TCPHY_G 388
#define PCLK_UPHY1_TCPD_G 389
#define PCLK_ALIVE 390
/* hclk gates */
#define HCLK_PERIHP 448
@@ -344,6 +348,7 @@
#define SCLK_I2C4_PMU 8
#define SCLK_I2C8_PMU 9
#define PCLK_SRC_PMU 19
#define PCLK_PMU 20
#define PCLK_PMUGRF_PMU 21
#define PCLK_INTMEM1_PMU 22
@@ -361,6 +366,7 @@
#define PCLK_UART4_PMU 34
#define PCLK_WDT_M0_PMU 35
#define FCLK_CM0S_SRC_PMU 44
#define FCLK_CM0S_PMU 45
#define SCLK_CM0S_PMU 46
#define HCLK_CM0S_PMU 47