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synced 2026-06-09 20:32:04 +09:00
modify fpga's gpio name
This commit is contained in:
root
@@ -169,115 +169,116 @@ struct rk2818_gpio_bank {
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#define RK2818_PIN_PH7 (PIN_BASE + 7*NUM_GROUP + 7)
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/***********************define extern gpio pin num******************************/
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#if defined(CONFIG_SPI_GPIO)
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#define FPGA_PIN_PA0 (GPIOS_EXPANDER_BASE + 0*NUM_GROUP + 0)
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#define FPGA_PIN_PA1 (GPIOS_EXPANDER_BASE + 0*NUM_GROUP + 1)
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#define FPGA_PIN_PA2 (GPIOS_EXPANDER_BASE + 0*NUM_GROUP + 2)
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#define FPGA_PIN_PA3 (GPIOS_EXPANDER_BASE + 0*NUM_GROUP + 3)
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#define FPGA_PIN_PA4 (GPIOS_EXPANDER_BASE + 0*NUM_GROUP + 4)
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#define FPGA_PIN_PA5 (GPIOS_EXPANDER_BASE + 0*NUM_GROUP + 5)
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#define FPGA_PIN_PA6 (GPIOS_EXPANDER_BASE + 0*NUM_GROUP + 6)
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#define FPGA_PIN_PA7 (GPIOS_EXPANDER_BASE + 0*NUM_GROUP + 7)
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#define FPGA_PIO0_00 (GPIOS_EXPANDER_BASE + 0*NUM_GROUP + 0)
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#define FPGA_PIO0_01 (GPIOS_EXPANDER_BASE + 0*NUM_GROUP + 1)
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#define FPGA_PIO0_02 (GPIOS_EXPANDER_BASE + 0*NUM_GROUP + 2)
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#define FPGA_PIO0_03 (GPIOS_EXPANDER_BASE + 0*NUM_GROUP + 3)
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#define FPGA_PIO0_04 (GPIOS_EXPANDER_BASE + 0*NUM_GROUP + 4)
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#define FPGA_PIO0_05 (GPIOS_EXPANDER_BASE + 0*NUM_GROUP + 5)
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#define FPGA_PIO0_06 (GPIOS_EXPANDER_BASE + 0*NUM_GROUP + 6)
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#define FPGA_PIO0_07 (GPIOS_EXPANDER_BASE + 0*NUM_GROUP + 7)
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#define FPGA_PIN_PB0 (GPIOS_EXPANDER_BASE + 1*NUM_GROUP + 0)
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#define FPGA_PIN_PB1 (GPIOS_EXPANDER_BASE + 1*NUM_GROUP + 1)
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#define FPGA_PIN_PB2 (GPIOS_EXPANDER_BASE + 1*NUM_GROUP + 2)
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#define FPGA_PIN_PB3 (GPIOS_EXPANDER_BASE + 1*NUM_GROUP + 3)
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#define FPGA_PIN_PB4 (GPIOS_EXPANDER_BASE + 1*NUM_GROUP + 4)
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#define FPGA_PIN_PB5 (GPIOS_EXPANDER_BASE + 1*NUM_GROUP + 5)
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#define FPGA_PIN_PB6 (GPIOS_EXPANDER_BASE + 1*NUM_GROUP + 6)
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#define FPGA_PIN_PB7 (GPIOS_EXPANDER_BASE + 1*NUM_GROUP + 7)
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#define FPGA_PIO0_08 (GPIOS_EXPANDER_BASE + 1*NUM_GROUP + 0)
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#define FPGA_PIO0_09 (GPIOS_EXPANDER_BASE + 1*NUM_GROUP + 1)
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#define FPGA_PIO0_10 (GPIOS_EXPANDER_BASE + 1*NUM_GROUP + 2)
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#define FPGA_PIO0_11 (GPIOS_EXPANDER_BASE + 1*NUM_GROUP + 3)
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#define FPGA_PIO0_12 (GPIOS_EXPANDER_BASE + 1*NUM_GROUP + 4)
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#define FPGA_PIO0_13 (GPIOS_EXPANDER_BASE + 1*NUM_GROUP + 5)
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#define FPGA_PIO0_14 (GPIOS_EXPANDER_BASE + 1*NUM_GROUP + 6)
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#define FPGA_PIO0_15 (GPIOS_EXPANDER_BASE + 1*NUM_GROUP + 7)
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#define FPGA_PIN_PC0 (GPIOS_EXPANDER_BASE + 2*NUM_GROUP + 0)
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#define FPGA_PIN_PC1 (GPIOS_EXPANDER_BASE + 2*NUM_GROUP + 1)
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#define FPGA_PIN_PC2 (GPIOS_EXPANDER_BASE + 2*NUM_GROUP + 2)
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#define FPGA_PIN_PC3 (GPIOS_EXPANDER_BASE + 2*NUM_GROUP + 3)
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#define FPGA_PIN_PC4 (GPIOS_EXPANDER_BASE + 2*NUM_GROUP + 4)
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#define FPGA_PIN_PC5 (GPIOS_EXPANDER_BASE + 2*NUM_GROUP + 5)
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#define FPGA_PIN_PC6 (GPIOS_EXPANDER_BASE + 2*NUM_GROUP + 6)
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#define FPGA_PIN_PC7 (GPIOS_EXPANDER_BASE + 2*NUM_GROUP + 7)
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#define FPGA_PIO1_00 (GPIOS_EXPANDER_BASE + 2*NUM_GROUP + 0)
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#define FPGA_PIO1_01 (GPIOS_EXPANDER_BASE + 2*NUM_GROUP + 1)
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#define FPGA_PIO1_02 (GPIOS_EXPANDER_BASE + 2*NUM_GROUP + 2)
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#define FPGA_PIO1_03 (GPIOS_EXPANDER_BASE + 2*NUM_GROUP + 3)
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#define FPGA_PIO1_04 (GPIOS_EXPANDER_BASE + 2*NUM_GROUP + 4)
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#define FPGA_PIO1_05 (GPIOS_EXPANDER_BASE + 2*NUM_GROUP + 5)
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#define FPGA_PIO1_06 (GPIOS_EXPANDER_BASE + 2*NUM_GROUP + 6)
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#define FPGA_PIO1_07 (GPIOS_EXPANDER_BASE + 2*NUM_GROUP + 7)
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#define FPGA_PIN_PD0 (GPIOS_EXPANDER_BASE + 3*NUM_GROUP + 0)
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#define FPGA_PIN_PD1 (GPIOS_EXPANDER_BASE + 3*NUM_GROUP + 1)
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#define FPGA_PIN_PD2 (GPIOS_EXPANDER_BASE + 3*NUM_GROUP + 2)
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#define FPGA_PIN_PD3 (GPIOS_EXPANDER_BASE + 3*NUM_GROUP + 3)
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#define FPGA_PIN_PD4 (GPIOS_EXPANDER_BASE + 3*NUM_GROUP + 4)
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#define FPGA_PIN_PD5 (GPIOS_EXPANDER_BASE + 3*NUM_GROUP + 5)
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#define FPGA_PIN_PD6 (GPIOS_EXPANDER_BASE + 3*NUM_GROUP + 6)
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#define FPGA_PIN_PD7 (GPIOS_EXPANDER_BASE + 3*NUM_GROUP + 7)
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#define FPGA_PIO1_08 (GPIOS_EXPANDER_BASE + 3*NUM_GROUP + 0)
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#define FPGA_PIO1_09 (GPIOS_EXPANDER_BASE + 3*NUM_GROUP + 1)
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#define FPGA_PIO1_10 (GPIOS_EXPANDER_BASE + 3*NUM_GROUP + 2)
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#define FPGA_PIO1_11 (GPIOS_EXPANDER_BASE + 3*NUM_GROUP + 3)
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#define FPGA_PIO1_12 (GPIOS_EXPANDER_BASE + 3*NUM_GROUP + 4)
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#define FPGA_PIO1_13 (GPIOS_EXPANDER_BASE + 3*NUM_GROUP + 5)
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#define FPGA_PIO1_14 (GPIOS_EXPANDER_BASE + 3*NUM_GROUP + 6)
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#define FPGA_PIO1_15 (GPIOS_EXPANDER_BASE + 3*NUM_GROUP + 7)
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#define FPGA_PIN_PE0 (GPIOS_EXPANDER_BASE + 4*NUM_GROUP + 0)
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#define FPGA_PIN_PE1 (GPIOS_EXPANDER_BASE + 4*NUM_GROUP + 1)
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#define FPGA_PIN_PE2 (GPIOS_EXPANDER_BASE + 4*NUM_GROUP + 2)
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#define FPGA_PIN_PE3 (GPIOS_EXPANDER_BASE + 4*NUM_GROUP + 3)
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#define FPGA_PIN_PE4 (GPIOS_EXPANDER_BASE + 4*NUM_GROUP + 4)
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#define FPGA_PIN_PE5 (GPIOS_EXPANDER_BASE + 4*NUM_GROUP + 5)
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#define FPGA_PIN_PE6 (GPIOS_EXPANDER_BASE + 4*NUM_GROUP + 6)
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#define FPGA_PIN_PE7 (GPIOS_EXPANDER_BASE + 4*NUM_GROUP + 7)
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#define FPGA_PIO2_00 (GPIOS_EXPANDER_BASE + 4*NUM_GROUP + 0)
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#define FPGA_PIO2_01 (GPIOS_EXPANDER_BASE + 4*NUM_GROUP + 1)
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#define FPGA_PIO2_02 (GPIOS_EXPANDER_BASE + 4*NUM_GROUP + 2)
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#define FPGA_PIO2_03 (GPIOS_EXPANDER_BASE + 4*NUM_GROUP + 3)
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#define FPGA_PIO2_04 (GPIOS_EXPANDER_BASE + 4*NUM_GROUP + 4)
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#define FPGA_PIO2_05 (GPIOS_EXPANDER_BASE + 4*NUM_GROUP + 5)
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#define FPGA_PIO2_06 (GPIOS_EXPANDER_BASE + 4*NUM_GROUP + 6)
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#define FPGA_PIO2_07 (GPIOS_EXPANDER_BASE + 4*NUM_GROUP + 7)
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#define FPGA_PIN_PF0 (GPIOS_EXPANDER_BASE + 5*NUM_GROUP + 0)
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#define FPGA_PIN_PF1 (GPIOS_EXPANDER_BASE + 5*NUM_GROUP + 1)
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#define FPGA_PIN_PF2 (GPIOS_EXPANDER_BASE + 5*NUM_GROUP + 2)
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#define FPGA_PIN_PF3 (GPIOS_EXPANDER_BASE + 5*NUM_GROUP + 3)
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#define FPGA_PIN_PF4 (GPIOS_EXPANDER_BASE + 5*NUM_GROUP + 4)
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#define FPGA_PIN_PF5 (GPIOS_EXPANDER_BASE + 5*NUM_GROUP + 5)
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#define FPGA_PIN_PF6 (GPIOS_EXPANDER_BASE + 5*NUM_GROUP + 6)
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#define FPGA_PIN_PF7 (GPIOS_EXPANDER_BASE + 5*NUM_GROUP + 7)
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#define FPGA_PIO2_08 (GPIOS_EXPANDER_BASE + 5*NUM_GROUP + 0)
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#define FPGA_PIO2_09 (GPIOS_EXPANDER_BASE + 5*NUM_GROUP + 1)
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#define FPGA_PIO2_10 (GPIOS_EXPANDER_BASE + 5*NUM_GROUP + 2)
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#define FPGA_PIO2_11 (GPIOS_EXPANDER_BASE + 5*NUM_GROUP + 3)
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#define FPGA_PIO2_12 (GPIOS_EXPANDER_BASE + 5*NUM_GROUP + 4)
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#define FPGA_PIO2_13 (GPIOS_EXPANDER_BASE + 5*NUM_GROUP + 5)
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#define FPGA_PIO2_14 (GPIOS_EXPANDER_BASE + 5*NUM_GROUP + 6)
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#define FPGA_PIO2_15 (GPIOS_EXPANDER_BASE + 5*NUM_GROUP + 7)
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#define FPGA_PIN_PG0 (GPIOS_EXPANDER_BASE + 6*NUM_GROUP + 0)
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#define FPGA_PIN_PG1 (GPIOS_EXPANDER_BASE + 6*NUM_GROUP + 1)
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#define FPGA_PIN_PG2 (GPIOS_EXPANDER_BASE + 6*NUM_GROUP + 2)
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#define FPGA_PIN_PG3 (GPIOS_EXPANDER_BASE + 6*NUM_GROUP + 3)
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#define FPGA_PIN_PG4 (GPIOS_EXPANDER_BASE + 6*NUM_GROUP + 4)
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#define FPGA_PIN_PG5 (GPIOS_EXPANDER_BASE + 6*NUM_GROUP + 5)
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#define FPGA_PIN_PG6 (GPIOS_EXPANDER_BASE + 6*NUM_GROUP + 6)
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#define FPGA_PIN_PG7 (GPIOS_EXPANDER_BASE + 6*NUM_GROUP + 7)
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#define FPGA_PIO3_00 (GPIOS_EXPANDER_BASE + 6*NUM_GROUP + 0)
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#define FPGA_PIO3_01 (GPIOS_EXPANDER_BASE + 6*NUM_GROUP + 1)
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#define FPGA_PIO3_02 (GPIOS_EXPANDER_BASE + 6*NUM_GROUP + 2)
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#define FPGA_PIO3_03 (GPIOS_EXPANDER_BASE + 6*NUM_GROUP + 3)
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#define FPGA_PIO3_04 (GPIOS_EXPANDER_BASE + 6*NUM_GROUP + 4)
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#define FPGA_PIO3_05 (GPIOS_EXPANDER_BASE + 6*NUM_GROUP + 5)
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#define FPGA_PIO3_06 (GPIOS_EXPANDER_BASE + 6*NUM_GROUP + 6)
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#define FPGA_PIO3_07 (GPIOS_EXPANDER_BASE + 6*NUM_GROUP + 7)
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#define FPGA_PIN_PH0 (GPIOS_EXPANDER_BASE + 7*NUM_GROUP + 0)
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#define FPGA_PIN_PH1 (GPIOS_EXPANDER_BASE + 7*NUM_GROUP + 1)
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#define FPGA_PIN_PH2 (GPIOS_EXPANDER_BASE + 7*NUM_GROUP + 2)
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#define FPGA_PIN_PH3 (GPIOS_EXPANDER_BASE + 7*NUM_GROUP + 3)
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#define FPGA_PIN_PH4 (GPIOS_EXPANDER_BASE + 7*NUM_GROUP + 4)
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#define FPGA_PIN_PH5 (GPIOS_EXPANDER_BASE + 7*NUM_GROUP + 5)
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#define FPGA_PIN_PH6 (GPIOS_EXPANDER_BASE + 7*NUM_GROUP + 6)
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#define FPGA_PIN_PH7 (GPIOS_EXPANDER_BASE + 7*NUM_GROUP + 7)
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#define FPGA_PIO3_08 (GPIOS_EXPANDER_BASE + 7*NUM_GROUP + 0)
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#define FPGA_PIO3_09 (GPIOS_EXPANDER_BASE + 7*NUM_GROUP + 1)
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#define FPGA_PIO3_10 (GPIOS_EXPANDER_BASE + 7*NUM_GROUP + 2)
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#define FPGA_PIO3_11 (GPIOS_EXPANDER_BASE + 7*NUM_GROUP + 3)
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#define FPGA_PIO3_12 (GPIOS_EXPANDER_BASE + 7*NUM_GROUP + 4)
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#define FPGA_PIO3_13 (GPIOS_EXPANDER_BASE + 7*NUM_GROUP + 5)
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#define FPGA_PIO3_14 (GPIOS_EXPANDER_BASE + 7*NUM_GROUP + 6)
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#define FPGA_PIO3_15 (GPIOS_EXPANDER_BASE + 7*NUM_GROUP + 7)
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#define FPGA_PIN_PI0 (GPIOS_EXPANDER_BASE + 8*NUM_GROUP + 0)
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#define FPGA_PIN_PI1 (GPIOS_EXPANDER_BASE + 8*NUM_GROUP + 1)
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#define FPGA_PIN_PI2 (GPIOS_EXPANDER_BASE + 8*NUM_GROUP + 2)
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#define FPGA_PIN_PI3 (GPIOS_EXPANDER_BASE + 8*NUM_GROUP + 3)
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#define FPGA_PIN_PI4 (GPIOS_EXPANDER_BASE + 8*NUM_GROUP + 4)
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#define FPGA_PIN_PI5 (GPIOS_EXPANDER_BASE + 8*NUM_GROUP + 5)
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#define FPGA_PIN_PI6 (GPIOS_EXPANDER_BASE + 8*NUM_GROUP + 6)
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#define FPGA_PIN_PI7 (GPIOS_EXPANDER_BASE + 8*NUM_GROUP + 7)
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#define FPGA_PIO4_00 (GPIOS_EXPANDER_BASE + 8*NUM_GROUP + 0)
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#define FPGA_PIO4_01 (GPIOS_EXPANDER_BASE + 8*NUM_GROUP + 1)
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#define FPGA_PIO4_02 (GPIOS_EXPANDER_BASE + 8*NUM_GROUP + 2)
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#define FPGA_PIO4_03 (GPIOS_EXPANDER_BASE + 8*NUM_GROUP + 3)
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#define FPGA_PIO4_04 (GPIOS_EXPANDER_BASE + 8*NUM_GROUP + 4)
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#define FPGA_PIO4_05 (GPIOS_EXPANDER_BASE + 8*NUM_GROUP + 5)
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#define FPGA_PIO4_06 (GPIOS_EXPANDER_BASE + 8*NUM_GROUP + 6)
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#define FPGA_PIO4_07 (GPIOS_EXPANDER_BASE + 8*NUM_GROUP + 7)
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#define FPGA_PIN_PJ0 (GPIOS_EXPANDER_BASE + 9*NUM_GROUP + 0)
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#define FPGA_PIN_PJ1 (GPIOS_EXPANDER_BASE + 9*NUM_GROUP + 1)
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#define FPGA_PIN_PJ2 (GPIOS_EXPANDER_BASE + 9*NUM_GROUP + 2)
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#define FPGA_PIN_PJ3 (GPIOS_EXPANDER_BASE + 9*NUM_GROUP + 3)
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#define FPGA_PIN_PJ4 (GPIOS_EXPANDER_BASE + 9*NUM_GROUP + 4)
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#define FPGA_PIN_PJ5 (GPIOS_EXPANDER_BASE + 9*NUM_GROUP + 5)
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#define FPGA_PIN_PJ6 (GPIOS_EXPANDER_BASE + 9*NUM_GROUP + 6)
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#define FPGA_PIN_PJ7 (GPIOS_EXPANDER_BASE + 9*NUM_GROUP + 7)
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#define FPGA_PIO4_08 (GPIOS_EXPANDER_BASE + 9*NUM_GROUP + 0)
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#define FPGA_PIO4_09 (GPIOS_EXPANDER_BASE + 9*NUM_GROUP + 1)
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#define FPGA_PIO4_10 (GPIOS_EXPANDER_BASE + 9*NUM_GROUP + 2)
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#define FPGA_PIO4_11 (GPIOS_EXPANDER_BASE + 9*NUM_GROUP + 3)
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#define FPGA_PIO4_12 (GPIOS_EXPANDER_BASE + 9*NUM_GROUP + 4)
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#define FPGA_PIO4_13 (GPIOS_EXPANDER_BASE + 9*NUM_GROUP + 5)
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#define FPGA_PIO4_14 (GPIOS_EXPANDER_BASE + 9*NUM_GROUP + 6)
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#define FPGA_PIO4_15 (GPIOS_EXPANDER_BASE + 9*NUM_GROUP + 7)
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#define FPGA_PIN_PK0 (GPIOS_EXPANDER_BASE + 10*NUM_GROUP + 0)
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#define FPGA_PIN_PK1 (GPIOS_EXPANDER_BASE + 10*NUM_GROUP + 1)
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#define FPGA_PIN_PK2 (GPIOS_EXPANDER_BASE + 10*NUM_GROUP + 2)
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#define FPGA_PIN_PK3 (GPIOS_EXPANDER_BASE + 10*NUM_GROUP + 3)
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#define FPGA_PIN_PK4 (GPIOS_EXPANDER_BASE + 10*NUM_GROUP + 4)
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#define FPGA_PIN_PK5 (GPIOS_EXPANDER_BASE + 10*NUM_GROUP + 5)
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#define FPGA_PIN_PK6 (GPIOS_EXPANDER_BASE + 10*NUM_GROUP + 6)
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#define FPGA_PIN_PK7 (GPIOS_EXPANDER_BASE + 10*NUM_GROUP + 7)
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#define FPGA_PIO5_00 (GPIOS_EXPANDER_BASE + 10*NUM_GROUP + 0)
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#define FPGA_PIO5_01 (GPIOS_EXPANDER_BASE + 10*NUM_GROUP + 1)
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#define FPGA_PIO5_02 (GPIOS_EXPANDER_BASE + 10*NUM_GROUP + 2)
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#define FPGA_PIO5_03 (GPIOS_EXPANDER_BASE + 10*NUM_GROUP + 3)
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#define FPGA_PIO5_04 (GPIOS_EXPANDER_BASE + 10*NUM_GROUP + 4)
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#define FPGA_PIO5_05 (GPIOS_EXPANDER_BASE + 10*NUM_GROUP + 5)
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#define FPGA_PIO5_06 (GPIOS_EXPANDER_BASE + 10*NUM_GROUP + 6)
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#define FPGA_PIO5_07 (GPIOS_EXPANDER_BASE + 10*NUM_GROUP + 7)
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#define FPGA_PIN_PL0 (GPIOS_EXPANDER_BASE + 11*NUM_GROUP + 0)
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#define FPGA_PIN_PL1 (GPIOS_EXPANDER_BASE + 11*NUM_GROUP + 1)
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#define FPGA_PIN_PL2 (GPIOS_EXPANDER_BASE + 11*NUM_GROUP + 2)
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#define FPGA_PIN_PL3 (GPIOS_EXPANDER_BASE + 11*NUM_GROUP + 3)
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#define FPGA_PIN_PL4 (GPIOS_EXPANDER_BASE + 11*NUM_GROUP + 4)
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#define FPGA_PIN_PL5 (GPIOS_EXPANDER_BASE + 11*NUM_GROUP + 5)
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#define FPGA_PIN_PL6 (GPIOS_EXPANDER_BASE + 11*NUM_GROUP + 6)
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#define FPGA_PIN_PL7 (GPIOS_EXPANDER_BASE + 11*NUM_GROUP + 7)
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#define FPGA_PIO5_08 (GPIOS_EXPANDER_BASE + 11*NUM_GROUP + 0)
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#define FPGA_PIO5_09 (GPIOS_EXPANDER_BASE + 11*NUM_GROUP + 1)
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#define FPGA_PIO5_10 (GPIOS_EXPANDER_BASE + 11*NUM_GROUP + 2)
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#define FPGA_PIO5_11 (GPIOS_EXPANDER_BASE + 11*NUM_GROUP + 3)
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#define FPGA_PIO5_12 (GPIOS_EXPANDER_BASE + 11*NUM_GROUP + 4)
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#define FPGA_PIO5_13 (GPIOS_EXPANDER_BASE + 11*NUM_GROUP + 5)
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#define FPGA_PIO5_14 (GPIOS_EXPANDER_BASE + 11*NUM_GROUP + 6)
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#define FPGA_PIO5_15 (GPIOS_EXPANDER_BASE + 11*NUM_GROUP + 7)
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#endif
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#ifndef __ASSEMBLY__
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extern void __init rk2818_gpio_init(struct rk2818_gpio_bank *data, int nr_banks);
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extern void __init rk2818_gpio_irq_setup(void);
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@@ -314,9 +315,9 @@ static inline int irq_to_gpio(unsigned irq)
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return (RK2818_PIN_PE0 + (irq - __gpio_to_irq(RK2818_PIN_PE0)));
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}
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#if defined(CONFIG_SPI_GPIO)
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else if((irq - __gpio_to_irq(FPGA_PIN_PA0)) <2*NUM_GROUP)
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else if((irq - __gpio_to_irq(FPGA_PIO0_00)) <2*NUM_GROUP)
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{
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return (FPGA_PIN_PA0 + (irq - __gpio_to_irq(FPGA_PIN_PA0)));
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return (FPGA_PIO0_00 + (irq - __gpio_to_irq(FPGA_PIO0_00)));
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}
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#endif
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else
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@@ -36,7 +36,7 @@
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#define DBG(x...)
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#endif
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#define SPI_GPIO_TEST 0
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#define SPI_GPIO_TEST 1
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#define HIGH_SPI_TEST 1
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spinlock_t gpio_lock;
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spinlock_t gpio_state_lock;
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@@ -489,6 +489,7 @@ int spi_gpio_handle_irq(struct spi_device *spi)
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int gpio_iir, i;
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int state;
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int irq;
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struct irq_desc *desc;
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spin_lock(&gpio_state_lock);
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state = gGpio0State;
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spin_unlock(&gpio_state_lock);
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@@ -497,13 +498,15 @@ int spi_gpio_handle_irq(struct spi_device *spi)
|
||||
if(gpio_iir == 0xffff)
|
||||
return -1;
|
||||
|
||||
DBG("gpio_iir=0x%x\n",gpio_iir);
|
||||
printk("%s:gpio_iir=%d\n",__FUNCTION__,gpio_iir);
|
||||
for(i=0; i<SPI_GPIO_IRQ_NUM; i++)
|
||||
{
|
||||
if(((gpio_iir & (1 << i)) == 0) && ((state & (1 << i)) != 0))
|
||||
{
|
||||
irq = gpio_to_irq(i);
|
||||
generic_handle_irq(irq);
|
||||
irq = i + GPIOS_EXPANDER_BASE;
|
||||
desc = irq_to_desc(irq);
|
||||
if(desc->action->handler)
|
||||
desc->action->handler(irq,desc->action->dev_id);
|
||||
printk("%s:pin=%d,irq=%d\n",__FUNCTION__,i,irq);
|
||||
}
|
||||
}
|
||||
@@ -583,12 +586,13 @@ void spi_gpio_work_handler(struct work_struct *work)
|
||||
#else
|
||||
for(i=4;i<81;i++)
|
||||
{
|
||||
gpio_direction_output(FPGA_PIN_PA0+i,TestGpioPinLevel);
|
||||
ret = gpio_direction_input(FPGA_PIN_PA0+i);
|
||||
gpio_direction_output(GPIOS_EXPANDER_BASE+i,TestGpioPinLevel);
|
||||
ret = gpio_direction_input(GPIOS_EXPANDER_BASE+i);
|
||||
if (ret) {
|
||||
printk("%s:failed to set GPIO[%d] input\n",__FUNCTION__,FPGA_PIN_PA0+i);
|
||||
printk("%s:failed to set GPIO[%d] input\n",__FUNCTION__,GPIOS_EXPANDER_BASE+i);
|
||||
}
|
||||
ret = gpio_get_value (FPGA_PIN_PA0+i);
|
||||
udelay(1);
|
||||
ret = gpio_get_value (GPIOS_EXPANDER_BASE+i);
|
||||
if(ret != TestGpioPinLevel)
|
||||
{
|
||||
#if SPI_FPGA_TEST_DEBUG
|
||||
@@ -610,7 +614,7 @@ void spi_gpio_work_handler(struct work_struct *work)
|
||||
static void spi_testgpio_timer(unsigned long data)
|
||||
{
|
||||
struct spi_fpga_port *port = (struct spi_fpga_port *)data;
|
||||
port->gpio.gpio_timer.expires = jiffies + msecs_to_jiffies(2000);
|
||||
port->gpio.gpio_timer.expires = jiffies + msecs_to_jiffies(1000);
|
||||
add_timer(&port->gpio.gpio_timer);
|
||||
//schedule_work(&port->gpio.spi_gpio_work);
|
||||
queue_work(port->gpio.spi_gpio_workqueue, &port->gpio.spi_gpio_work);
|
||||
@@ -752,7 +756,7 @@ int spi_gpio_init_first(void)
|
||||
spi_gpio_set_pindirection(SPI_GPIO_P1_08, SPI_GPIO_OUT);
|
||||
spi_gpio_set_pinlevel(SPI_GPIO_P1_09, SPI_GPIO_LOW); //LCD_DISP_ON output
|
||||
spi_gpio_set_pindirection(SPI_GPIO_P1_09, SPI_GPIO_OUT);
|
||||
spi_gpio_set_pinlevel(SPI_GPIO_P1_10, SPI_GPIO_LOW); //WM_PWR_EN output
|
||||
spi_gpio_set_pinlevel(SPI_GPIO_P1_10, SPI_GPIO_HIGH); //WM_PWR_EN output
|
||||
spi_gpio_set_pindirection(SPI_GPIO_P1_10, SPI_GPIO_OUT);
|
||||
spi_gpio_set_pindirection(SPI_GPIO_P1_11, SPI_GPIO_IN); //HARD1,input
|
||||
|
||||
@@ -971,25 +975,19 @@ struct fpga_gpio_chip {
|
||||
}
|
||||
|
||||
static struct fpga_gpio_chip spi_gpio_chip[] = {
|
||||
SPI_GPIO_CHIP_DEF("PIO0", GPIOS_EXPANDER_BASE+0*NUM_GROUP, NUM_GROUP),
|
||||
SPI_GPIO_CHIP_DEF("PIO0", GPIOS_EXPANDER_BASE+1*NUM_GROUP, NUM_GROUP),
|
||||
SPI_GPIO_CHIP_DEF("PIO1", GPIOS_EXPANDER_BASE+2*NUM_GROUP, NUM_GROUP),
|
||||
SPI_GPIO_CHIP_DEF("PIO1", GPIOS_EXPANDER_BASE+3*NUM_GROUP, NUM_GROUP),
|
||||
SPI_GPIO_CHIP_DEF("PIO2", GPIOS_EXPANDER_BASE+4*NUM_GROUP, NUM_GROUP),
|
||||
SPI_GPIO_CHIP_DEF("PIO2", GPIOS_EXPANDER_BASE+5*NUM_GROUP, NUM_GROUP),
|
||||
SPI_GPIO_CHIP_DEF("PIO3", GPIOS_EXPANDER_BASE+6*NUM_GROUP, NUM_GROUP),
|
||||
SPI_GPIO_CHIP_DEF("PIO3", GPIOS_EXPANDER_BASE+7*NUM_GROUP, NUM_GROUP),
|
||||
SPI_GPIO_CHIP_DEF("PIO4", GPIOS_EXPANDER_BASE+8*NUM_GROUP, NUM_GROUP),
|
||||
SPI_GPIO_CHIP_DEF("PIO4", GPIOS_EXPANDER_BASE+9*NUM_GROUP, NUM_GROUP),
|
||||
SPI_GPIO_CHIP_DEF("PIO5", GPIOS_EXPANDER_BASE+10*NUM_GROUP, NUM_GROUP),
|
||||
SPI_GPIO_CHIP_DEF("PIO5", GPIOS_EXPANDER_BASE+11*NUM_GROUP, NUM_GROUP),
|
||||
SPI_GPIO_CHIP_DEF("PIO0", GPIOS_EXPANDER_BASE+0*NUM_GROUP*2, NUM_GROUP<<1),
|
||||
SPI_GPIO_CHIP_DEF("PIO1", GPIOS_EXPANDER_BASE+1*NUM_GROUP*2, NUM_GROUP<<1),
|
||||
SPI_GPIO_CHIP_DEF("PIO2", GPIOS_EXPANDER_BASE+2*NUM_GROUP*2, NUM_GROUP<<1),
|
||||
SPI_GPIO_CHIP_DEF("PIO3", GPIOS_EXPANDER_BASE+3*NUM_GROUP*2, NUM_GROUP<<1),
|
||||
SPI_GPIO_CHIP_DEF("PIO4", GPIOS_EXPANDER_BASE+4*NUM_GROUP*2, NUM_GROUP<<1),
|
||||
SPI_GPIO_CHIP_DEF("PIO5", GPIOS_EXPANDER_BASE+5*NUM_GROUP*2, NUM_GROUP<<1),
|
||||
};
|
||||
|
||||
|
||||
static void spi_gpio_irq_enable(unsigned irq)
|
||||
{
|
||||
int gpio = irq_to_gpio(irq) - GPIOS_EXPANDER_BASE;
|
||||
DBG("%s:line=%d,gpio=%d\n",__FUNCTION__,__LINE__,gpio);
|
||||
printk("%s:line=%d,irq=%d,gpio=%d\n",__FUNCTION__,__LINE__,irq,gpio);
|
||||
if(gpio < 16)
|
||||
spi_gpio_int_sel(gpio,SPI_GPIO0_IS_INT);
|
||||
else
|
||||
@@ -1003,7 +1001,7 @@ static void spi_gpio_irq_enable(unsigned irq)
|
||||
static void spi_gpio_irq_disable(unsigned irq)
|
||||
{
|
||||
int gpio = irq_to_gpio(irq) - GPIOS_EXPANDER_BASE;
|
||||
DBG("%s:line=%d,gpio=%d\n",__FUNCTION__,__LINE__,gpio);
|
||||
printk("%s:line=%d,irq=%d,gpio=%d\n",__FUNCTION__,__LINE__,irq,gpio);
|
||||
if(gpio < 16)
|
||||
spi_gpio_int_sel(gpio,SPI_GPIO0_IS_INT);
|
||||
else
|
||||
@@ -1030,7 +1028,7 @@ static int spi_gpio_irq_set_type(unsigned int irq, unsigned int type)
|
||||
{
|
||||
int gpio = irq_to_gpio(irq) - GPIOS_EXPANDER_BASE;
|
||||
int int_type = 0;
|
||||
DBG("%s:line=%d,type=%d\n",__FUNCTION__,__LINE__,type);
|
||||
printk("%s:line=%d,irq=%d,type=%d,gpio=%d\n",__FUNCTION__,__LINE__,irq,type,gpio);
|
||||
if(gpio < 16)
|
||||
spi_gpio_int_sel(gpio,SPI_GPIO0_IS_INT);
|
||||
else
|
||||
@@ -1075,11 +1073,11 @@ void spi_gpio_test_gpio_irq_init(void)
|
||||
{
|
||||
#if SPI_GPIO_TEST
|
||||
struct spi_fpga_port *port = pFpgaPort;
|
||||
int i,gpio,ret;
|
||||
int i,gpio,ret,irq;
|
||||
|
||||
for(i=0;i<81;i++)
|
||||
{
|
||||
gpio = FPGA_PIN_PA0+i;
|
||||
gpio = GPIOS_EXPANDER_BASE+i;
|
||||
ret = gpio_request(gpio, NULL);
|
||||
if (ret) {
|
||||
printk("%s:failed to request GPIO[%d]\n",__FUNCTION__,gpio);
|
||||
@@ -1088,42 +1086,43 @@ void spi_gpio_test_gpio_irq_init(void)
|
||||
#if 1
|
||||
for(i=0;i<4;i++)
|
||||
{
|
||||
gpio = FPGA_PIN_PA0+i;
|
||||
|
||||
gpio = GPIOS_EXPANDER_BASE+i;
|
||||
irq = gpio_to_irq(gpio);
|
||||
printk("%s:line=%d,irq=%d,gpio=%d\n",__FUNCTION__,__LINE__,irq,gpio);
|
||||
switch(i)
|
||||
{
|
||||
case 0:
|
||||
ret = request_irq(gpio_to_irq(gpio),spi_gpio_int_test_0,IRQF_TRIGGER_FALLING,NULL,port);
|
||||
ret = request_irq(irq ,spi_gpio_int_test_0,IRQF_TRIGGER_FALLING,NULL,port);
|
||||
if(ret)
|
||||
{
|
||||
printk("unable to request GPIO[%d] irq\n",gpio);
|
||||
printk("%s:unable to request GPIO[%d] irq\n",__FUNCTION__,gpio);
|
||||
gpio_free(gpio);
|
||||
}
|
||||
break;
|
||||
|
||||
case 1:
|
||||
ret = request_irq(gpio_to_irq(gpio),spi_gpio_int_test_1,IRQF_TRIGGER_FALLING,NULL,port);
|
||||
ret = request_irq(irq ,spi_gpio_int_test_1,IRQF_TRIGGER_FALLING,NULL,port);
|
||||
if(ret)
|
||||
{
|
||||
printk("unable to request GPIO[%d] irq\n",gpio);
|
||||
printk("%s:unable to request GPIO[%d] irq\n",__FUNCTION__,gpio);
|
||||
gpio_free(gpio);
|
||||
}
|
||||
break;
|
||||
|
||||
case 2:
|
||||
ret = request_irq(gpio_to_irq(gpio),spi_gpio_int_test_2,IRQF_TRIGGER_FALLING,NULL,port);
|
||||
ret = request_irq(irq ,spi_gpio_int_test_2,IRQF_TRIGGER_FALLING,NULL,port);
|
||||
if(ret)
|
||||
{
|
||||
printk("unable to request GPIO[%d] irq\n",gpio);
|
||||
printk("%s:unable to request GPIO[%d] irq\n",__FUNCTION__,gpio);
|
||||
gpio_free(gpio);
|
||||
}
|
||||
break;
|
||||
|
||||
case 3:
|
||||
ret = request_irq(gpio_to_irq(gpio),spi_gpio_int_test_3,IRQF_TRIGGER_FALLING,NULL,port);
|
||||
case 9:
|
||||
ret = request_irq(irq ,spi_gpio_int_test_3,IRQF_TRIGGER_FALLING,NULL,port);
|
||||
if(ret)
|
||||
{
|
||||
printk("unable to request GPIO[%d] irq\n",gpio);
|
||||
printk("%s:unable to request GPIO[%d] irq\n",__FUNCTION__,gpio);
|
||||
gpio_free(gpio);
|
||||
}
|
||||
break;
|
||||
@@ -1141,56 +1140,57 @@ void spi_gpio_test_gpio_irq_init(void)
|
||||
|
||||
int spi_gpio_banks;
|
||||
static struct lock_class_key gpio_lock_class;
|
||||
int spi_gpio_init(void)
|
||||
{
|
||||
unsigned i;
|
||||
struct fpga_gpio_chip *fpga_gpio_chip;
|
||||
spi_gpio_banks = 12;
|
||||
spi_gpio_init_first();
|
||||
for (i = 0; i < 12; i++)
|
||||
{
|
||||
fpga_gpio_chip = &spi_gpio_chip[i];
|
||||
gpiochip_add(&fpga_gpio_chip->chip);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Called from the processor-specific init to enable GPIO interrupt support.
|
||||
*/
|
||||
void spi_gpio_irq_setup(void)
|
||||
{
|
||||
unsigned int i,j, pin;
|
||||
unsigned int j, pin;
|
||||
struct fpga_gpio_chip *this;
|
||||
|
||||
this = spi_gpio_chip;
|
||||
pin = NR_AIC_IRQS + CONFIG_RK28_GPIO_IRQ;
|
||||
|
||||
for(i=0;i<2;i++)
|
||||
for (j = 0; j < 16; j++)
|
||||
{
|
||||
for (j = 0; j < 8; j++)
|
||||
{
|
||||
lockdep_set_class(&irq_desc[pin+j].lock, &gpio_lock_class);
|
||||
/*
|
||||
* Can use the "simple" and not "edge" handler since it's
|
||||
* shorter, and the AIC handles interrupts sanely.
|
||||
*/
|
||||
set_irq_chip(pin+j, &spi_gpio_irq_chip);
|
||||
set_irq_handler(pin+j, handle_simple_irq);
|
||||
set_irq_flags(pin+j, IRQF_VALID);
|
||||
//set_irq_chip_data(pin+j, this);
|
||||
//set_irq_chained_handler(pin+j, spi_fpga_irq);
|
||||
}
|
||||
|
||||
this += 4;
|
||||
pin += 8;
|
||||
lockdep_set_class(&irq_desc[pin+j].lock, &gpio_lock_class);
|
||||
/*
|
||||
* Can use the "simple" and not "edge" handler since it's
|
||||
* shorter, and the AIC handles interrupts sanely.
|
||||
*/
|
||||
set_irq_chip(pin+j, &spi_gpio_irq_chip);
|
||||
//set_irq_handler(pin+j, handle_simple_irq);
|
||||
set_irq_flags(pin+j, IRQF_VALID);
|
||||
}
|
||||
|
||||
//set_irq_chip_data(pin+j, this);
|
||||
//set_irq_chained_handler(pin+j, spi_fpga_irq);
|
||||
|
||||
printk("%s: %d gpio irqs in %d banks\n", __FUNCTION__, pin-GPIOS_EXPANDER_BASE, spi_gpio_banks);
|
||||
#if SPI_GPIO_TEST
|
||||
spi_gpio_test_gpio_irq_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
int spi_gpio_init(void)
|
||||
{
|
||||
unsigned i;
|
||||
struct fpga_gpio_chip *fpga_gpio_chip;
|
||||
spi_gpio_banks = 6;
|
||||
spi_gpio_init_first();
|
||||
for (i = 0; i < 6; i++)
|
||||
{
|
||||
fpga_gpio_chip = &spi_gpio_chip[i];
|
||||
gpiochip_add(&fpga_gpio_chip->chip);
|
||||
}
|
||||
|
||||
spi_gpio_irq_setup();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
MODULE_DESCRIPTION("Driver for spi2gpio.");
|
||||
|
||||
Reference in New Issue
Block a user