From 13639746faf395861e0a1f27bae82cc5388a2251 Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Tue, 23 May 2023 20:04:57 +0800
Subject: [PATCH] phy: rockchip: naneng-combphy: Fix swing to 650mv under 100M
 refclk for rk3562

Change-Id: Ia71ec0851c1d1bc686277a49af70488f413f423c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index 5b8ca4686fb4..42ef316599fa 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -684,6 +684,12 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
 
 			writel(0x32, priv->mmio + (0x11 << 2));
 			writel(0xf0, priv->mmio + (0xa << 2));
+
+			/* CKDRV output swing adjust to 650mv */
+			val = readl(priv->mmio + (0xd << 2));
+			val &= ~(0xf << 1);
+			val |= 0xb;
+			writel(val, priv->mmio + (0xd << 2));
 		}
 		break;
 	default: