From 13ddb9150c94d80f580729bb87ca4af2e2e296ba Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 13 May 2022 17:08:37 +0800 Subject: [PATCH] phy: rockchip: naneng-combophy: Add pcie ext clk support Modify the dts for the combophy: 1. assign clock to 100MHz 2. add "rockchip,ext-refclk" Signed-off-by: Kever Yang Change-Id: I72c125ac6aa42dcf00761f32e20b10042fd9985d --- .../rockchip/phy-rockchip-naneng-combphy.c | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 0351ed80aafe..6964c473611d 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -809,6 +809,27 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) return -EINVAL; } + if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) { + param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); + if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) { + val = 0x10; + writel(val, priv->mmio + (0x20 << 2)); + + val = 0x0c; + writel(val, priv->mmio + (0x1b << 2)); + + /* Set up su_trim: */ + val = 0xf0; + writel(val, priv->mmio + (0xa << 2)); + val = 0x45; + writel(val, priv->mmio + (0xb << 2)); + val = 0xb8; + writel(val, priv->mmio + (0xc << 2)); + val = 0x59; + writel(val, priv->mmio + (0xd << 2)); + } + } + return 0; }