diff --git a/sound/soc/codecs/rk3308_codec.c b/sound/soc/codecs/rk3308_codec.c
index 5fb9a243de45..9387cd646f9c 100644
--- a/sound/soc/codecs/rk3308_codec.c
+++ b/sound/soc/codecs/rk3308_codec.c
@@ -633,6 +633,17 @@ static int rk3308_set_dai_fmt(struct snd_soc_dai *codec_dai,
 				   RK3308_ADC_DIG_WORK,
 				   RK3308_ADC_DIG_WORK);
 
+	/* Enable high pass filter and cut-off 20Hz for ADCs */
+	for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) {
+		regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON04(grp),
+				   RK3308_ADC_HPF_PATH_MSK,
+				   RK3308_ADC_HPF_PATH_EN);
+		udelay(10);
+		regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON04(grp),
+				   RK3308_ADC_HPF_CUTOFF_MSK,
+				   RK3308_ADC_HPF_CUTOFF_20HZ);
+	}
+
 	regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01,
 			   RK3308_DAC_I2S_LRC_POL_MSK |
 			   RK3308_DAC_I2S_MODE_MSK,
diff --git a/sound/soc/codecs/rk3308_codec.h b/sound/soc/codecs/rk3308_codec.h
index 586400f9905e..4905eacc8fc3 100644
--- a/sound/soc/codecs/rk3308_codec.h
+++ b/sound/soc/codecs/rk3308_codec.h
@@ -26,7 +26,8 @@
 #define ACODEC_ADC_I2S_CTL0			0x04 /* REG 0x01 */
 #define ACODEC_ADC_I2S_CTL1			0x08 /* REG 0x02 */
 #define ACODEC_ADC_BIST_MODE_SEL		0x0c /* REG 0x03 */
-/* Resevred REG 0x04 ~ 0x06 */
+#define ACODEC_ADC_HPF_PATH			0x10 /* REG 0x04 */
+/* Resevred REG 0x05 ~ 0x06 */
 #define ACODEC_ADC_DATA_PATH			0x1c /* REG 0x07 */
 /* Resevred REG 0x08 ~ 0x0f */
 
@@ -123,6 +124,7 @@
 #define RK3308_ADC_DIG_CON01(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_I2S_CTL0)
 #define RK3308_ADC_DIG_CON02(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_I2S_CTL1)
 #define RK3308_ADC_DIG_CON03(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_BIST_MODE_SEL)
+#define RK3308_ADC_DIG_CON04(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_HPF_PATH)
 #define RK3308_ADC_DIG_CON07(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_DATA_PATH)
 
 #define RK3308_ALC_L_DIG_CON00(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL0)
@@ -273,6 +275,17 @@
 #define RK3308_ADC_R_CH_BIST_CUBE		(0x1 << RK3308_ADC_R_CH_BIST_SFT)
 #define RK3308_ADC_R_CH_NORMAL_RIGHT		(0x0 << RK3308_ADC_R_CH_BIST_SFT) /* normal mode */
 
+/* RK3308_ADC_DIG_CON04 - REG: 0x0010 */
+#define RK3308_ADC_HPF_PATH_SFT			2
+#define RK3308_ADC_HPF_PATH_MSK			(1 << RK3308_ADC_HPF_PATH_SFT)
+#define RK3308_ADC_HPF_PATH_DIS			(1 << RK3308_ADC_HPF_PATH_SFT)
+#define RK3308_ADC_HPF_PATH_EN			(0 << RK3308_ADC_HPF_PATH_SFT)
+#define RK3308_ADC_HPF_CUTOFF_SFT		0
+#define RK3308_ADC_HPF_CUTOFF_MSK		(0x3 << RK3308_ADC_HPF_CUTOFF_SFT)
+#define RK3308_ADC_HPF_CUTOFF_612HZ		(0x2 << RK3308_ADC_HPF_CUTOFF_SFT)
+#define RK3308_ADC_HPF_CUTOFF_245HZ		(0x1 << RK3308_ADC_HPF_CUTOFF_SFT)
+#define RK3308_ADC_HPF_CUTOFF_20HZ		(0x0 << RK3308_ADC_HPF_CUTOFF_SFT)
+
 /* RK3308_ADC_DIG_CON07 - REG: 0x001c */
 #define RK3308_ADCL_DATA_SFT			4
 #define RK3308_ADCL_DATA(x)			(x << RK3308_ADCL_DATA_SFT)