From 150255a2ec0bd524d13101ddd9307fa3fdba5ec2 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 15 Nov 2021 17:43:59 +0800 Subject: [PATCH] clk: rockchip: pll: fix up rk3588 pll setting Signed-off-by: Elaine Zhang Change-Id: Ibf78a3c9d141da2bbb17026096aadbe26ddfd293 --- drivers/clk/rockchip/clk-pll.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 3bd161d066ec..3650ab47f80e 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -1370,9 +1370,8 @@ static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll, RK3588_PLLCON1_S_SHIFT), pll->reg_base + RK3399_PLLCON(1)); - if (rate->k) - writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, - RK3588_PLLCON2_K_SHIFT), + writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, + RK3588_PLLCON2_K_SHIFT), pll->reg_base + RK3399_PLLCON(2)); /* set pll power up */