From 151189f520fe27630e4ab77765fe7a5b1f5704f5 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Thu, 11 Nov 2021 20:10:01 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588: Set SDHCI core clk to 200MHz As we mask our SDHCI controller as SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, host->max_clk is derived from core clock in the first place. Then f_max works together with it. If we adjust loader's core clk setting, such as 50MHz, we will get 50MHz for host->max_clk, because .get_max_clock() reads core clk when probing driver. That will lead f_max be set to 50MHz as well, no matter if max-frequency is set higher than 50MHz. We can simple solve this problem by assigning core clk as 200MHz in the first place and then let max-frequency property takes over it. Signed-off-by: Shawn Lin Change-Id: I25986720fa441da3786ca0904a2d4b1a5b0568e5 --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 1dc49ee83101..1e4da5b54163 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -2912,8 +2912,8 @@ compatible = "rockchip,rk3588-dwcmshc", "rockchip,dwcmshc-sdhci"; reg = <0x0 0xfe2e0000 0x0 0x10000>; interrupts = ; - assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>; - assigned-clock-rates = <200000000>, <24000000>; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; + assigned-clock-rates = <200000000>, <24000000>, <200000000>; clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>;