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spicc: initial add spicc driver

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PD#138714: spicc: initial add spicc driver

Change-Id: I60aa176f7bd9d64bd6e9db56adc7f592bc856f50
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
This commit is contained in:
Sunny Luo
2017-03-31 21:14:34 +08:00
committed by Jianxin Pan
parent 8a363156d2
commit 1570047aa4
11 changed files with 1308 additions and 37 deletions
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7
MAINTAINERS
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@@ -13751,3 +13751,10 @@ F: drivers/amlogic/media/video_processor/video_dev/Makefile
F: drivers/amlogic/media/video_processor/video_dev/amlvideo.h
F: drivers/amlogic/media/video_processor/video_dev/amlvideo.c
F: drivers/amlogic/media/video_processor/video_dev/common/vfutil.c
AMLOGIC SPICC DRIVER
M: Sunny Luo <sunny.luo@amlogic.com>
F: drivers/amlogic/spicc/spicc.c
F: drivers/amlogic/spicc/spicc.h
F: drivers/amlogic/spicc/Kconfig
F: drivers/amlogic/spicc/Makefile

16
arch/arm64/boot/dts/amlogic/gxl_p212_1g.dts
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@@ -1152,3 +1152,19 @@
&efuse {
status = "ok";
};
&spicc{
status = "disabled";
pinctrl-names = "spicc_pulldown","spicc_pullup";
pinctrl-0 = <&spicc_pulldown_x8x9x11>;
pinctrl-1 = <&spicc_pullup_x8x9x11>;
num_chipselect = <1>;
cs-gpios = <&gpio GPIOX_10 GPIO_ACTIVE_HIGH>;
dma_en = <0>;
dma_tx_threshold = <3>;
dma_rx_threshold = <3>;
dma_num_per_read_burst = <3>;
dma_num_per_write_burst = <3>;
delay_control = <0x15>;
ssctl = <0>;
};

30
arch/arm64/boot/dts/amlogic/mesongxl.dtsi
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@@ -248,6 +248,17 @@
/* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
/* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */
};
spicc:@c1108d80{
compatible = "amlogic, spicc";
status = "disabled";
reg = <0x0 0xc1108d80 0x0 0x28>;
clocks = <&clkc CLKID_SPICC>;
clock-names = "spicc_clk";
interrupts = <0 81 1>;
device_id = <0>;
};
i2c_ao: i2c@c8100500{ /*I2C-AO*/
compatible = "amlogic, meson-i2c";
dev_name = "i2c-AO";
@@ -775,15 +786,6 @@
};
};
spicc_pins_z11z12z13: spicc_pins_z11z12z13 {
mux {
groups = "spi_sclk_0",
"spi_miso_0",
"spi_mosi_0";
function = "spi";
};
};
spicc_pulldown_z11z12z13: spicc_pulldown_z11z12z13 {
mux {
groups = "spi_sclk_0",
@@ -802,15 +804,6 @@
};
};
spicc_pins_x8x9x11: spicc_pins_x8x9x11 {
mux {
groups = "spi_sclk_1",
"spi_miso_1",
"spi_mosi_1";
function = "spi";
};
};
spicc_pulldown_x8x9x11: spicc_pulldown_x8x9x11 {
mux {
groups = "spi_sclk_1",
@@ -1127,4 +1120,3 @@
tbl = <&clk125_cfg &clk285_cfg &clk400_cfg
&clk500_cfg &clk666_cfg &clk750_cfg &clk750_cfg>;
};

29
arch/arm64/boot/dts/amlogic/mesongxm.dtsi
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@@ -338,6 +338,17 @@
/* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
/* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */
};
spicc:@c1108d80{
compatible = "amlogic, spicc";
status = "disabled";
reg = <0x0 0xc1108d80 0x0 0x28>;
clocks = <&clkc CLKID_SPICC>;
clock-names = "spicc_clk";
interrupts = <0 81 1>;
device_id = <0>;
};
i2c_ao: i2c@c8100500{ /*I2C-AO*/
compatible = "amlogic, meson-i2c";
dev_name = "i2c-AO";
@@ -865,15 +876,6 @@
};
};
spicc_pins_z11z12z13: spicc_pins_z11z12z13 {
mux {
groups = "spi_sclk_0",
"spi_miso_0",
"spi_mosi_0";
function = "spi";
};
};
spicc_pulldown_z11z12z13: spicc_pulldown_z11z12z13 {
mux {
groups = "spi_sclk_0",
@@ -892,15 +894,6 @@
};
};
spicc_pins_x8x9x11: spicc_pins_x8x9x11 {
mux {
groups = "spi_sclk_1",
"spi_miso_1",
"spi_mosi_1";
function = "spi";
};
};
spicc_pulldown_x8x9x11: spicc_pulldown_x8x9x11 {
mux {
groups = "spi_sclk_1",

5
arch/arm64/configs/meson64_defconfig
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@@ -170,6 +170,7 @@ CONFIG_AMLOGIC_USB2PHY=y
CONFIG_AMLOGIC_USB3PHY=y
CONFIG_AMLOGIC_I2C=y
CONFIG_AMLOGIC_I2C_MASTER=y
CONFIG_AMLOGIC_SPICC_MASTER=y
CONFIG_AMLOGIC_SEC=y
CONFIG_AMLOGIC_CPU_VERSION=y
CONFIG_AMLOGIC_MESON64_VERSION=y
@@ -289,6 +290,10 @@ CONFIG_INPUT_UINPUT=y
# CONFIG_DEVMEM is not set
# CONFIG_DEVKMEM is not set
CONFIG_HW_RANDOM=y
CONFIG_SPI=y
CONFIG_SPI_DEBUG=y
CONFIG_SPI_GPIO=y
CONFIG_SPI_SPIDEV=y
CONFIG_THERMAL=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR=y

2
drivers/amlogic/Kconfig
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@@ -21,6 +21,8 @@ source "drivers/amlogic/usb/Kconfig"
source "drivers/amlogic/i2c/Kconfig"
source "drivers/amlogic/spicc/Kconfig"
source "drivers/amlogic/secmon/Kconfig"
source "drivers/amlogic/cpu_version/Kconfig"

2
drivers/amlogic/Makefile
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@@ -21,6 +21,8 @@ obj-$(CONFIG_AMLOGIC_CPU_VERSION) += cpu_version/
obj-$(CONFIG_AMLOGIC_I2C) += i2c/
obj-$(CONFIG_AMLOGIC_SPICC_MASTER) += spicc/
obj-$(CONFIG_AMLOGIC_CPU_INFO) += cpu_info/
obj-$(CONFIG_AMLOGIC_MHU_MBOX) += mailbox/

15
drivers/amlogic/spicc/Kconfig Normal file
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@@ -0,0 +1,15 @@
#
# Sensor device configuration
#
menu "AMLOGIC SPI Hardware bus support"
config AMLOGIC_SPICC_MASTER
tristate "AMLOGIC SPICC MASTER SUPPORT"
default n
help
This is amlogic SPICC hardware bus master.
This driver can also be built as a module.
endmenu

5
drivers/amlogic/spicc/Makefile Normal file
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@@ -0,0 +1,5 @@
#
# Makefile for the amlogic SPI bus drivers.
#
obj-$(CONFIG_AMLOGIC_SPICC_MASTER) += spicc.o

1122
drivers/amlogic/spicc/spicc.c Normal file
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File diff suppressed because it is too large Load Diff

112
drivers/amlogic/spicc/spicc.h Normal file
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@@ -0,0 +1,112 @@
/*
* drivers/amlogic/spicc/spicc.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __SPICC_H__
#define __SPICC_H__
#include <linux/amlogic/saradc.h>
#define SPICC_FIFO_SIZE 16
#define SPICC_DEFAULT_BIT_WIDTH 8
#define SPICC_DEFAULT_SPEED_HZ 3000000
#define SPICC_REG_RXDATA (0<<2)
#define SPICC_REG_TXDATA (1<<2)
#define SPICC_REG_CON (2<<2)
#define SPICC_REG_INT (3<<2)
#define SPICC_REG_DMA (4<<2)
#define SPICC_REG_STA (5<<2)
#define SPICC_REG_PERIOD (6<<2)
#define SPICC_REG_TEST (7<<2)
#define SPICC_REG_DRADDR (8<<2)
#define SPICC_REG_DWADDR (9<<2)
#define SPICC_REG_LD_CNTL0 (10<<2)
#define SPICC_REG_LD_CNTL1 (11<<2)
#define SPICC_REG_LD_RADDR (12<<2)
#define SPICC_REG_LD_WADDR (13<<2)
#define SPICC_REG_ENHANCE_CNTL (14<<2)
#define CON_ENABLE bits_desc(SPICC_REG_CON, 0, 1)
#define CON_MODE bits_desc(SPICC_REG_CON, 1, 1)
#define CON_XCH bits_desc(SPICC_REG_CON, 2, 1)
#define CON_SMC bits_desc(SPICC_REG_CON, 3, 1)
#define CON_CLK_POL bits_desc(SPICC_REG_CON, 4, 1)
#define CON_CLK_PHA bits_desc(SPICC_REG_CON, 5, 1)
#define CON_SS_CTL bits_desc(SPICC_REG_CON, 6, 1)
#define CON_SS_POL bits_desc(SPICC_REG_CON, 7, 1)
#define CON_DRCTL bits_desc(SPICC_REG_CON, 8, 2)
#define CON_CHIP_SELECT bits_desc(SPICC_REG_CON, 12, 2)
#define CON_DATA_RATE_DIV bits_desc(SPICC_REG_CON, 16, 3)
#define CON_BITS_PER_WORD bits_desc(SPICC_REG_CON, 19, 6)
#define CON_BURST_LEN bits_desc(SPICC_REG_CON, 25, 7)
#define BURST_LEN_MAX 128
#define INT_TX_EMPTY_EN bits_desc(SPICC_REG_INT, 0, 1)
#define INT_TX_HALF_EN bits_desc(SPICC_REG_INT, 1, 1)
#define INT_TX_FULL_EN bits_desc(SPICC_REG_INT, 2, 1)
#define INT_RX_READY_EN bits_desc(SPICC_REG_INT, 3, 1)
#define INT_RX_HALF_EN bits_desc(SPICC_REG_INT, 4, 1)
#define INT_RX_FULL_EN bits_desc(SPICC_REG_INT, 5, 1)
#define INT_RX_OF_EN bits_desc(SPICC_REG_INT, 6, 1)
#define INT_XFER_COM_EN bits_desc(SPICC_REG_INT, 7, 1)
#define DMA_EN bits_desc(SPICC_REG_DMA, 0, 1)
#define DMA_TX_FIFO_TH bits_desc(SPICC_REG_DMA, 1, 5)
#define DMA_RX_FIFO_TH bits_desc(SPICC_REG_DMA, 6, 5)
#define DMA_NUM_RD_BURST bits_desc(SPICC_REG_DMA, 11, 4)
#define DMA_NUM_WR_BURST bits_desc(SPICC_REG_DMA, 15, 4)
#define DMA_URGENT bits_desc(SPICC_REG_DMA, 19, 1)
#define DMA_THREAD_ID bits_desc(SPICC_REG_DMA, 20, 6)
#define DMA_BURST_NUM bits_desc(SPICC_REG_DMA, 26, 6)
#define STA_TX_EMPTY bits_desc(SPICC_REG_STA, 0, 1)
#define STA_TX_HALF bits_desc(SPICC_REG_STA, 1, 1)
#define STA_TX_FULL bits_desc(SPICC_REG_STA, 2, 1)
#define STA_RX_READY bits_desc(SPICC_REG_STA, 3, 1)
#define STA_RX_HALF bits_desc(SPICC_REG_STA, 4, 1)
#define STA_RX_FULL bits_desc(SPICC_REG_STA, 5, 1)
#define STA_RX_OF bits_desc(SPICC_REG_STA, 6, 1)
#define STA_XFER_COM bits_desc(SPICC_REG_STA, 7, 1)
#define TX_COUNT bits_desc(SPICC_REG_TEST, 0, 5)
#define RX_COUNT bits_desc(SPICC_REG_TEST, 5, 5)
#define DELAY_CONTROL bits_desc(SPICC_REG_TEST, 16, 6)
#define RX_FIFO_RESET bits_desc(SPICC_REG_TEST, 22, 1)
#define TX_FIFO_RESET bits_desc(SPICC_REG_TEST, 23, 1)
#define CLK_FREE_EN bits_desc(SPICC_REG_TEST, 24, 1)
#define CS_DELAY bits_desc(SPICC_REG_ENHANCE_CNTL, 0, 16)
#define ENHANCE_CLK_DIV bits_desc(SPICC_REG_ENHANCE_CNTL, 16, 8)
#define ENHANCE_CLK_DIV_SELECT bits_desc(SPICC_REG_ENHANCE_CNTL, 24, 1)
#define MOSI_OEN bits_desc(SPICC_REG_ENHANCE_CNTL, 25, 1)
#define CLK_OEN bits_desc(SPICC_REG_ENHANCE_CNTL, 26, 1)
#define CS_OEN bits_desc(SPICC_REG_ENHANCE_CNTL, 27, 1)
#define CS_DELAY_EN bits_desc(SPICC_REG_ENHANCE_CNTL, 28, 1)
#define MAIN_CLK_AO bits_desc(SPICC_REG_ENHANCE_CNTL, 29, 1)
struct spicc_platform_data {
int device_id;
struct spicc_regs __iomem *regs;
struct pinctrl *pinctrl;
struct clk *clk;
int num_chipselect;
int *cs_gpios;
};
#endif