shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-09 12:17:12 +09:00
Code Issues Packages Projects Releases Wiki Activity

deinterlace: set post phase to 8 when crop left odd [2/2]

Browse Source 
PD#SWPL-13223

Problem:
there is a white line on left when crop left is odd

Solution:
set post mif phase to 8;

Verify:
TL1

Change-Id: Ic39e15f5c1d07e756ecc4909366af35d1472dc29
Signed-off-by: Jihong Sui <jihong.sui@amlogic.com>
This commit is contained in:
Jihong Sui
2019-08-23 17:24:24 +08:00
committed by Luke Go
parent 7e3ef1e914
commit 15c7bea6f2
1 changed files with 23 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
drivers/amlogic/media/deinterlace/deinterlace_hw.c
View File

@@ -2012,6 +2012,8 @@ static void set_di_if2_mif(struct DI_MIF_s *mif, int urgent,
{
unsigned int bytes_per_pixel, demux_mode;
unsigned int pat, loop = 0, chro_rpt_lastl_ctrl = 0;
/*crop issue*/
unsigned int hz_ini_phase = 0;
if (mif->set_separate_en == 1) {
pat = vpat[(vskip_cnt<<1)+1];
@@ -2084,10 +2086,13 @@ static void set_di_if2_mif(struct DI_MIF_s *mif, int urgent,
/* Dummy pixel value */
DI_VSYNC_WR_MPEG_REG(DI_IF2_DUMMY_PIXEL, 0x00808000);
/*crop issue*/
if (mif->luma_x_start0 % 2)
hz_ini_phase = 8;
if (mif->set_separate_en != 0) { /* 4:2:0 block mode. */
set_di_if2_fmt_more(1, /* hfmt_en */
1,/* hz_yc_ratio */
0,/* hz_ini_phase */
hz_ini_phase,/* hz_ini_phase */
1, /* vfmt_en */
1, /* vt_yc_ratio */
0, /* vt_ini_phase */
@@ -2097,7 +2102,7 @@ static void set_di_if2_mif(struct DI_MIF_s *mif, int urgent,
} else {
set_di_if2_fmt_more(1, /* hfmt_en */
1, /* hz_yc_ratio */
0, /* hz_ini_phase */
hz_ini_phase, /* hz_ini_phase */
0, /* vfmt_en */
0, /* vt_yc_ratio */
0, /* vt_ini_phase */
@@ -2112,6 +2117,8 @@ static void set_di_if1_mif(struct DI_MIF_s *mif, int urgent,
{
unsigned int bytes_per_pixel, demux_mode;
unsigned int pat, loop = 0, chro_rpt_lastl_ctrl = 0;
/*crop issue*/
unsigned int hz_ini_phase = 0;
if (mif->set_separate_en == 1) {
pat = vpat[(vskip_cnt<<1)+1];
@@ -2181,10 +2188,14 @@ static void set_di_if1_mif(struct DI_MIF_s *mif, int urgent,
/* Dummy pixel value */
DI_VSYNC_WR_MPEG_REG(DI_IF1_DUMMY_PIXEL, 0x00808000);
/*crop issue*/
if (mif->luma_x_start0 % 2)
hz_ini_phase = 8;
if (mif->set_separate_en != 0) { /* 4:2:0 block mode. */
set_di_if1_fmt_more(1, /* hfmt_en */
1,/* hz_yc_ratio */
0,/* hz_ini_phase */
hz_ini_phase,/* hz_ini_phase */
1, /* vfmt_en */
1, /* vt_yc_ratio */
0, /* vt_ini_phase */
@@ -2194,7 +2205,7 @@ static void set_di_if1_mif(struct DI_MIF_s *mif, int urgent,
} else {
set_di_if1_fmt_more(1, /* hfmt_en */
1, /* hz_yc_ratio */
0, /* hz_ini_phase */
hz_ini_phase, /* hz_ini_phase */
0, /* vfmt_en */
0, /* vt_yc_ratio */
0, /* vt_ini_phase */
@@ -2478,7 +2489,8 @@ static void set_di_if0_mif_g12(struct DI_MIF_s *mif, int urgent, int hold_line,
{
unsigned int pat, loop = 0;
unsigned int bytes_per_pixel, demux_mode;
/*crop issue*/
unsigned int hz_ini_phase = 0;
if (mif->set_separate_en == 1) {
pat = vpat[(vskip_cnt<<1)+1];
@@ -2544,12 +2556,16 @@ static void set_di_if0_mif_g12(struct DI_MIF_s *mif, int urgent, int hold_line,
DI_VSYNC_WR_MPEG_REG(DI_IF0_LUMA0_RPT_PAT, pat);
DI_VSYNC_WR_MPEG_REG(DI_IF0_CHROMA0_RPT_PAT, pat);
/*crop issue*/
if (mif->luma_x_start0 % 2)
hz_ini_phase = 8;
/* 4:2:0 block mode. */
if (mif->set_separate_en != 0) {
set_di_if0_fmt_more_g12(
1, /* hfmt_en */
1, /* hz_yc_ratio */
0, /* hz_ini_phase */
hz_ini_phase, /* hz_ini_phase */
1, /* vfmt_en */
1, /* vt_yc_ratio */
0, /* vt_ini_phase */
@@ -2560,7 +2576,7 @@ mif->chroma_x_end0 - mif->chroma_x_start0 + 1, /* c length */
set_di_if0_fmt_more_g12(
1, /* hfmt_en */
1, /* hz_yc_ratio */
0, /* hz_ini_phase */
hz_ini_phase, /* hz_ini_phase */
0, /* vfmt_en */
0, /* vt_yc_ratio */
0, /* vt_ini_phase */