From 15e40b35158ee21f7709233c40950bbcd3931f7d Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Tue, 25 Jan 2022 20:05:14 +0800 Subject: [PATCH] soc: rockchip: cpuinfo: Add support for rv1106/3 This patch adds support for rv1106/3 soc and get chip version from OS_REG1[2:0] which was written by SPL. Details ref to Rockchip_Introduction_OS_REG.md Signed-off-by: Sugar Zhang Change-Id: Ib833a55acb70490945a37b5fdab7a29dcb5c3e6e --- drivers/soc/rockchip/rockchip-cpuinfo.c | 27 +++++++++++++++++++++++++ include/linux/rockchip/cpu.h | 25 +++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/drivers/soc/rockchip/rockchip-cpuinfo.c b/drivers/soc/rockchip/rockchip-cpuinfo.c index 4c075088304c..a0984b46cd49 100644 --- a/drivers/soc/rockchip/rockchip-cpuinfo.c +++ b/drivers/soc/rockchip/rockchip-cpuinfo.c @@ -108,6 +108,16 @@ static struct platform_driver rockchip_cpuinfo_driver = { }, }; +static void rockchip_set_cpu_version_from_os_reg(u32 reg) +{ + void __iomem *r = ioremap(reg, 0x4); + + if (r) { + rockchip_set_cpu_version(readl_relaxed(r) & GENMASK(2, 0)); + iounmap(r); + } +} + static void px30_init(void) { void __iomem *base; @@ -125,6 +135,19 @@ static void px30_init(void) } } +#define RV1106_OS_REG1 0xff020204 +static void rv1103_init(void) +{ + rockchip_soc_id = ROCKCHIP_SOC_RV1103; + rockchip_set_cpu_version_from_os_reg(RV1106_OS_REG1); +} + +static void rv1106_init(void) +{ + rockchip_soc_id = ROCKCHIP_SOC_RV1106; + rockchip_set_cpu_version_from_os_reg(RV1106_OS_REG1); +} + static void rv1109_init(void) { rockchip_soc_id = ROCKCHIP_SOC_RV1109; @@ -230,6 +253,10 @@ int __init rockchip_soc_id_init(void) rk3126_init(); } else if (cpu_is_rk3308()) { rk3308_init(); + } else if (cpu_is_rv1103()) { + rv1103_init(); + } else if (cpu_is_rv1106()) { + rv1106_init(); } else if (cpu_is_rv1109()) { rv1109_init(); } else if (cpu_is_rv1126()) { diff --git a/include/linux/rockchip/cpu.h b/include/linux/rockchip/cpu.h index babdd014f671..ed881b1c1657 100644 --- a/include/linux/rockchip/cpu.h +++ b/include/linux/rockchip/cpu.h @@ -19,6 +19,8 @@ #define ROCKCHIP_CPU_MASK 0xffff0000 #define ROCKCHIP_CPU_SHIFT 16 #define ROCKCHIP_CPU_PX30 0x33260000 +#define ROCKCHIP_CPU_RV1103 0x11030000 +#define ROCKCHIP_CPU_RV1106 0x11060000 #define ROCKCHIP_CPU_RV1109 0x11090000 #define ROCKCHIP_CPU_RV1126 0x11260000 #define ROCKCHIP_CPU_RK312X 0x31260000 @@ -96,6 +98,25 @@ static inline bool cpu_is_px30(void) static inline bool cpu_is_px30(void) { return false; } #endif +#if defined(CONFIG_CPU_RV1106) +static inline bool cpu_is_rv1103(void) +{ + if (rockchip_soc_id) + return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RV1103; + return of_machine_is_compatible("rockchip,rv1103"); +} + +static inline bool cpu_is_rv1106(void) +{ + if (rockchip_soc_id) + return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RV1106; + return of_machine_is_compatible("rockchip,rv1106"); +} +#else +static inline bool cpu_is_rv1103(void) { return false; } +static inline bool cpu_is_rv1106(void) { return false; } +#endif + #if defined(CONFIG_CPU_RV1126) || defined(CONFIG_CPU_RV1109) static inline bool cpu_is_rv1109(void) { @@ -176,6 +197,8 @@ static inline bool cpu_is_rk3568(void) { return false; } #define ROCKCHIP_SOC_MASK (ROCKCHIP_CPU_MASK | 0xff) #define ROCKCHIP_SOC_PX30 (ROCKCHIP_CPU_PX30 | 0x00) #define ROCKCHIP_SOC_PX30S (ROCKCHIP_CPU_PX30 | 0x01) +#define ROCKCHIP_SOC_RV1103 (ROCKCHIP_CPU_RV1103 | 0x00) +#define ROCKCHIP_SOC_RV1106 (ROCKCHIP_CPU_RV1106 | 0x00) #define ROCKCHIP_SOC_RV1109 (ROCKCHIP_CPU_RV1109 | 0x00) #define ROCKCHIP_SOC_RV1126 (ROCKCHIP_CPU_RV1126 | 0x00) #define ROCKCHIP_SOC_RK3126 (ROCKCHIP_CPU_RK312X | 0x00) @@ -202,6 +225,8 @@ static inline bool soc_is_##id(void) \ ROCKCHIP_SOC(PX30, px30, PX30) ROCKCHIP_SOC(PX30, px30s, PX30S) +ROCKCHIP_SOC(RV1106, rv1103, RV1103) +ROCKCHIP_SOC(RV1106, rv1106, RV1106) ROCKCHIP_SOC(RV1126, rv1109, RV1109) ROCKCHIP_SOC(RV1126, rv1126, RV1126) ROCKCHIP_SOC(RK312X, rk3126, RK3126)