From 6b1273024db483c5c3c99c32bcf1e6ff16c22a5f Mon Sep 17 00:00:00 2001
From: Zefa Chen <zefa.chen@rock-chips.com>
Date: Tue, 30 May 2023 16:45:05 +0800
Subject: [PATCH 01/60] media: rockchip: vicap send sof both online and read
 back

Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: Iec76f92835eb4bb6ec24cd10a10157f0af8dae44
---
 drivers/media/platform/rockchip/cif/capture.c | 39 ++++++++++---------
 1 file changed, 21 insertions(+), 18 deletions(-)

diff --git a/drivers/media/platform/rockchip/cif/capture.c b/drivers/media/platform/rockchip/cif/capture.c
index c1b4e8545111..a188e552e969 100644
--- a/drivers/media/platform/rockchip/cif/capture.c
+++ b/drivers/media/platform/rockchip/cif/capture.c
@@ -9195,6 +9195,22 @@ static int rkcif_stop_dma_capture(struct rkcif_stream *stream)
 	return 0;
 }
 
+static void rkcif_send_sof(struct rkcif_device *cif_dev)
+{
+	struct v4l2_mbus_config *mbus = &cif_dev->active_sensor->mbus;
+	struct csi2_dev *csi;
+
+	if (mbus->type == V4L2_MBUS_CSI2_DPHY ||
+	    mbus->type == V4L2_MBUS_CSI2_CPHY) {
+		csi = container_of(cif_dev->active_sensor->sd, struct csi2_dev, sd);
+		rkcif_csi2_event_inc_sof(csi);
+	} else if (mbus->type == V4L2_MBUS_CCP2) {
+		rkcif_lvds_event_inc_sof(cif_dev);
+	} else {
+		rkcif_dvp_event_inc_sof(cif_dev);
+	}
+}
+
 static int rkcif_g_toisp_ch(unsigned int intstat_glb, int index)
 {
 	if (intstat_glb & TOISP_END_CH0(index))
@@ -9280,6 +9296,8 @@ static void rkcif_toisp_check_stop_status(struct sditf_priv *priv,
 				stream = &priv->cif_dev->stream[0];
 			else
 				stream = &priv->cif_dev->stream[src_id % 4];
+			if (stream->id == 0)
+				rkcif_send_sof(stream->cifdev);
 			stream->frame_idx++;
 			cur_time = ktime_get_ns();
 			stream->readout.readout_time = cur_time - stream->readout.fs_timestamp;
@@ -9395,22 +9413,6 @@ static int rkcif_check_group_sync_state(struct rkcif_device *cif_dev)
 	return ret;
 }
 
-static void rkcif_send_sof(struct rkcif_device *cif_dev)
-{
-	struct v4l2_mbus_config *mbus = &cif_dev->active_sensor->mbus;
-	struct csi2_dev *csi;
-
-	if (mbus->type == V4L2_MBUS_CSI2_DPHY ||
-	    mbus->type == V4L2_MBUS_CSI2_CPHY) {
-		csi = container_of(cif_dev->active_sensor->sd, struct csi2_dev, sd);
-		rkcif_csi2_event_inc_sof(csi);
-	} else if (mbus->type == V4L2_MBUS_CCP2) {
-		rkcif_lvds_event_inc_sof(cif_dev);
-	} else {
-		rkcif_dvp_event_inc_sof(cif_dev);
-	}
-}
-
 static void rkcif_deal_sof(struct rkcif_device *cif_dev)
 {
 	struct rkcif_stream *detect_stream = &cif_dev->stream[0];
@@ -9463,9 +9465,10 @@ static void rkcif_deal_sof(struct rkcif_device *cif_dev)
 			}
 		}
 	} else {
-		rkcif_send_sof(cif_dev);
-		if (!cif_dev->sditf[0] || cif_dev->sditf[0]->mode.rdbk_mode)
+		if (!cif_dev->sditf[0] || cif_dev->sditf[0]->mode.rdbk_mode) {
+			rkcif_send_sof(cif_dev);
 			detect_stream->frame_idx++;
+		}
 		if (detect_stream->cifdev->rdbk_debug &&
 		    detect_stream->frame_idx < 15 &&
 		    (!cif_dev->sditf[0] || cif_dev->sditf[0]->mode.rdbk_mode))

From 2c94291de8f08a1d44d498d8bbd4ce149d0073e2 Mon Sep 17 00:00:00 2001
From: ZiHan Huang <zack.huang@rock-chips.com>
Date: Tue, 30 May 2023 11:28:52 +0800
Subject: [PATCH 02/60] arm64: dts: rockchip: add
 rk3588-evb7-lp4-v11-linux-ipc.dts

Signed-off-by: ZiHan Huang <zack.huang@rock-chips.com>
Change-Id: I01791bd56777bf570de41e0468890a08f9fc5e55
---
 arch/arm64/boot/dts/rockchip/Makefile            |  1 +
 .../rockchip/rk3588-evb7-lp4-v11-linux-ipc.dts   | 16 ++++++++++++++++
 2 files changed, 17 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v11-linux-ipc.dts

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 2a728949f0ca..2b2df22ab2ba 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -166,6 +166,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb6-lp4-v10-linux.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v10-linux.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v10-rk1608-ipc-8x-linux.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v11-linux-ipc.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h0-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h0-v10-linux.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v11-linux-ipc.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v11-linux-ipc.dts
new file mode 100644
index 000000000000..74cf867cd913
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v11-linux-ipc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "rk3588-evb7-lp4.dtsi"
+#include "rk3588-evb7-imx415.dtsi"
+#include "rk3588-ipc.dtsi"
+
+/ {
+	model = "Rockchip RK3588 EVB7 LP4 V11 Board";
+	compatible = "rockchip,rk3588-evb7-lp4-v11-linux-ipc", "rockchip,rk3588";
+};

From e6c7ea7d4da7e43ca05bb2634165e7c143a108ba Mon Sep 17 00:00:00 2001
From: Hisping Lin <hisping.lin@rock-chips.com>
Date: Tue, 28 Feb 2023 10:17:52 +0800
Subject: [PATCH 03/60] tee: optee: interrupt an RPC when supplicant has been
 killed

check supplicant is dead or alive when get signal,
run normal program if supplicant is alive,
interrupting an RPC if supplicant is dead, Otherwise,
the current thread will be stuck in the optee driver.
The error is printed as follows:

INFO: task gatekeeper@1.0-:461 blocked for more than 20 seconds.
Not tainted 5.10.66 #2
task:gatekeeper@1.0- state:D stack: 0 pid: 461 ppid: 1 flags:0x0400002d
Call trace:
switch_to+0x180/0x230
__schedule+0x49c/0x704
schedule+0xa0/0xe8
schedule_timeout+0x38/0x124
wait_for_common+0xa4/0x134
wait_for_completion+0x1c/0x2c
optee_handle_rpc+0x1a4/0x6ec
optee_do_call_with_arg+0x1a4/0x298
optee_release+0x134/0x1bc
tee_release+0xa4/0x100

Change-Id: I2f82338ecccc1bc97bb5a6c25767eca4542cbcdf
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
---
 drivers/tee/optee/supp.c | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/tee/optee/supp.c b/drivers/tee/optee/supp.c
index 322a543b8c27..2d556b79a67e 100644
--- a/drivers/tee/optee/supp.c
+++ b/drivers/tee/optee/supp.c
@@ -82,6 +82,9 @@ u32 optee_supp_thrd_req(struct tee_context *ctx, u32 func, size_t num_params,
 	struct optee_supp_req *req;
 	bool interruptable;
 	u32 ret;
+	unsigned long timeleft;
+	int id;
+	struct optee_supp_req *get_req;
 
 	/*
 	 * Return in case there is no supplicant available and
@@ -114,8 +117,17 @@ u32 optee_supp_thrd_req(struct tee_context *ctx, u32 func, size_t num_params,
 	 * exclusive access again.
 	 */
 	while (wait_for_completion_interruptible(&req->c)) {
+		pr_err("Warning, Interrupting an RPC to supplicant!\n");
+		timeleft = wait_for_completion_timeout(&req->c, msecs_to_jiffies(2000));
+		if (timeleft) {
+			/* get completion, it means tee-supplicant is alive. */
+			break;
+		} else {
+			/* timeout, it means tee-supplicant is dead, interrupting an RPC. */
+			interruptable = true;
+		}
+
 		mutex_lock(&supp->mutex);
-		interruptable = !supp->ctx;
 		if (interruptable) {
 			/*
 			 * There's no supplicant available and since the
@@ -134,6 +146,14 @@ u32 optee_supp_thrd_req(struct tee_context *ctx, u32 func, size_t num_params,
 				list_del(&req->link);
 				req->in_queue = false;
 			}
+
+			idr_for_each_entry(&supp->idr, get_req, id) {
+				if (get_req == req) {
+					idr_remove(&supp->idr, id);
+					supp->req_id = -1;
+					break;
+				}
+			}
 		}
 		mutex_unlock(&supp->mutex);
 

From 2f2ba4a8f8da7b54072abacf24d4695db358e518 Mon Sep 17 00:00:00 2001
From: Algea Cao <algea.cao@rock-chips.com>
Date: Tue, 16 Aug 2022 14:59:14 +0800
Subject: [PATCH 04/60] phy: rockchip-samsung-hdptx-hdmi: Don't set bus_width 8
 when probe

Fix set pll rate err when play hdr video first time after
system boot.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ic85b8f8b20a2a588627f650ff402076decd23b63
---
 drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c
index e10776a28864..15f361facdf3 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c
@@ -2313,7 +2313,6 @@ static int rockchip_hdptx_phy_probe(struct platform_device *pdev)
 	}
 
 	phy_set_drvdata(hdptx->phy, hdptx);
-	phy_set_bus_width(hdptx->phy, 8);
 
 	pm_runtime_enable(dev);
 	ret = devm_add_action_or_reset(dev, rockchip_hdptx_phy_runtime_disable,

From c73d891d8e6e20383db490f234afe4157915d198 Mon Sep 17 00:00:00 2001
From: Cliff Chen <cliff.chen@rock-chips.com>
Date: Thu, 25 May 2023 10:14:23 +0800
Subject: [PATCH 05/60] mm: optimize readahead for the file with fscrypt

For files with fscrypt enabled, to allow IO and the encryption
or decryption process to ping-pong, lookahead is forcibly enabled.

Change-Id: I137b8439dcd1fd99052bef1d1b0526af0d4a611e
Signed-off-by: Cliff Chen <cmc@rock-chips.com>
---
 mm/readahead.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/mm/readahead.c b/mm/readahead.c
index a95364c99487..393fe69001ab 100644
--- a/mm/readahead.c
+++ b/mm/readahead.c
@@ -27,6 +27,10 @@
 
 #include "internal.h"
 
+#ifdef CONFIG_ARCH_ROCKCHIP
+#include <linux/fscrypt.h>
+#endif
+
 /*
  * Initialise a struct file's readahead state.  Assumes that the caller has
  * memset *ra to zero.
@@ -287,6 +291,9 @@ void force_page_cache_ra(struct readahead_control *ractl,
 	struct address_space *mapping = ractl->mapping;
 	struct backing_dev_info *bdi = inode_to_bdi(mapping->host);
 	unsigned long max_pages, index;
+#ifdef CONFIG_ARCH_ROCKCHIP
+	bool force_lookahead = false;
+#endif
 
 	if (unlikely(!mapping->a_ops->readpage && !mapping->a_ops->readpages &&
 			!mapping->a_ops->readahead))
@@ -298,6 +305,13 @@ void force_page_cache_ra(struct readahead_control *ractl,
 	 */
 	index = readahead_index(ractl);
 	max_pages = max_t(unsigned long, bdi->io_pages, ra->ra_pages);
+#ifdef CONFIG_ARCH_ROCKCHIP
+	/* For files with fscrypt enabled, to allow IO and the encryption
+	 * or decryption process to ping-pong, lookahead is forcibly enabled.
+	 */
+	if (nr_to_read > max_pages && fscrypt_inode_uses_fs_layer_crypto(mapping->host))
+		force_lookahead = true;
+#endif
 	nr_to_read = min_t(unsigned long, nr_to_read, max_pages);
 	while (nr_to_read) {
 		unsigned long this_chunk = (2 * 1024 * 1024) / PAGE_SIZE;
@@ -305,7 +319,14 @@ void force_page_cache_ra(struct readahead_control *ractl,
 		if (this_chunk > nr_to_read)
 			this_chunk = nr_to_read;
 		ractl->_index = index;
+#ifdef CONFIG_ARCH_ROCKCHIP
+		if (force_lookahead)
+			do_page_cache_ra(ractl, this_chunk, this_chunk / 2);
+		else
+			do_page_cache_ra(ractl, this_chunk, 0);
+#else
 		do_page_cache_ra(ractl, this_chunk, 0);
+#endif
 
 		index += this_chunk;
 		nr_to_read -= this_chunk;

From a8efd060aa942aefb186d1b1758c2838f2c8082d Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Tue, 30 May 2023 17:46:32 +0800
Subject: [PATCH 06/60] spi: rockchip-sfc: Optimize the judgment mechanism
 completed by the controller

There is very little data left in fifo, and the controller will
complete the transmission in a short period of time, so
use readl_poll_timeout() for busy wait 10us to accelerate response.

Change-Id: I63e7cfd35dc05d0af860cc9724d66d827aa47d51
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
 drivers/spi/spi-rockchip-sfc.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/spi/spi-rockchip-sfc.c b/drivers/spi/spi-rockchip-sfc.c
index ebb14271e8cf..b9fb8f429e10 100644
--- a/drivers/spi/spi-rockchip-sfc.c
+++ b/drivers/spi/spi-rockchip-sfc.c
@@ -510,6 +510,16 @@ static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us)
 	int ret = 0;
 	u32 status;
 
+	/*
+	 * There is very little data left in fifo, and the controller will
+	 * complete the transmission in a short period of time.
+	 */
+	ret = readl_poll_timeout(sfc->regbase + SFC_SR, status,
+				 !(status & SFC_SR_IS_BUSY),
+				 0, 10);
+	if (!ret)
+		return 0;
+
 	ret = readl_poll_timeout(sfc->regbase + SFC_SR, status,
 				 !(status & SFC_SR_IS_BUSY),
 				 20, timeout_us);

From 2196ad1ae9fdcf75e73072458b6b137fa814610b Mon Sep 17 00:00:00 2001
From: Damon Ding <damon.ding@rock-chips.com>
Date: Wed, 24 May 2023 09:52:21 +0800
Subject: [PATCH 07/60] pwm: rockchip: disable the pclk dynamic switch if
 oneshot mode enabled

If the pclk of pwm is off, the interrupt will not be
generated.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I1c68a22e875712fd7260ba8f24bd8f53cb8aa679
---
 drivers/pwm/pwm-rockchip.c | 73 +++++++++++++++++++++++++++++---------
 1 file changed, 56 insertions(+), 17 deletions(-)

diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c
index e604c5dd8aa5..e2837c45f0d7 100644
--- a/drivers/pwm/pwm-rockchip.c
+++ b/drivers/pwm/pwm-rockchip.c
@@ -9,6 +9,7 @@
 #include <linux/clk.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
+#include <linux/iopoll.h>
 #include <linux/irq.h>
 #include <linux/module.h>
 #include <linux/of.h>
@@ -25,7 +26,11 @@
 #define PWM_CTRL_OUTPUT_EN	(1 << 3)
 
 #define PWM_ENABLE		(1 << 0)
-#define PWM_CONTINUOUS		(1 << 1)
+#define PWM_MODE_SHIFT		1
+#define PWM_MODE_MASK		(0x3 << PWM_MODE_SHIFT)
+#define PWM_ONESHOT		(0 << PWM_MODE_SHIFT)
+#define PWM_CONTINUOUS		(1 << PWM_MODE_SHIFT)
+#define PWM_CAPTURE		(2 << PWM_MODE_SHIFT)
 #define PWM_DUTY_POSITIVE	(1 << 3)
 #define PWM_DUTY_NEGATIVE	(0 << 3)
 #define PWM_INACTIVE_NEGATIVE	(0 << 4)
@@ -56,7 +61,7 @@ struct rockchip_pwm_chip {
 	unsigned long clk_rate;
 	bool vop_pwm_en; /* indicate voppwm mirror register state */
 	bool center_aligned;
-	bool oneshot;
+	bool oneshot_en;
 	int channel_id;
 	int irq;
 };
@@ -93,9 +98,11 @@ static void rockchip_pwm_get_state(struct pwm_chip *chip,
 	u32 val;
 	int ret;
 
-	ret = clk_enable(pc->pclk);
-	if (ret)
-		return;
+	if (!pc->oneshot_en) {
+		ret = clk_enable(pc->pclk);
+		if (ret)
+			return;
+	}
 
 	tmp = readl_relaxed(pc->base + pc->data->regs.period);
 	tmp *= pc->data->prescaler * NSEC_PER_SEC;
@@ -106,6 +113,8 @@ static void rockchip_pwm_get_state(struct pwm_chip *chip,
 	state->duty_cycle =  DIV_ROUND_CLOSEST_ULL(tmp, pc->clk_rate);
 
 	val = readl_relaxed(pc->base + pc->data->regs.ctrl);
+	if (pc->oneshot_en)
+		enable_conf &= ~PWM_CONTINUOUS;
 	state->enabled = (val & enable_conf) == enable_conf;
 
 	if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE))
@@ -113,7 +122,8 @@ static void rockchip_pwm_get_state(struct pwm_chip *chip,
 	else
 		state->polarity = PWM_POLARITY_NORMAL;
 
-	clk_disable(pc->pclk);
+	if (!pc->oneshot_en)
+		clk_disable(pc->pclk);
 }
 
 static irqreturn_t rockchip_pwm_oneshot_irq(int irq, void *data)
@@ -179,13 +189,13 @@ static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 	}
 
 #ifdef CONFIG_PWM_ROCKCHIP_ONESHOT
-	if (state->oneshot_count > PWM_ONESHOT_COUNT_MAX) {
-		pc->oneshot = false;
-		dev_err(chip->dev, "Oneshot_count value overflow.\n");
-	} else if (state->oneshot_count > 0) {
+	if (state->oneshot_count > 0 && state->oneshot_count <= PWM_ONESHOT_COUNT_MAX) {
 		u32 int_ctrl;
 
-		pc->oneshot = true;
+		pc->oneshot_en = true;
+		ctrl &= ~PWM_MODE_MASK;
+		ctrl |= PWM_ONESHOT;
+
 		ctrl &= ~PWM_ONESHOT_COUNT_MASK;
 		ctrl |= (state->oneshot_count - 1) << PWM_ONESHOT_COUNT_SHIFT;
 
@@ -195,9 +205,15 @@ static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 	} else {
 		u32 int_ctrl;
 
-		pc->oneshot = false;
+		if (state->oneshot_count)
+			dev_err(chip->dev, "Oneshot_count must be between 1 and 256.\n");
+
+		pc->oneshot_en = false;
+		ctrl &= ~PWM_MODE_MASK;
 		ctrl |= PWM_CONTINUOUS;
 
+		ctrl &= ~PWM_ONESHOT_COUNT_MASK;
+
 		int_ctrl = readl_relaxed(pc->base + PWM_REG_INT_EN(pc->channel_id));
 		int_ctrl &= ~PWM_CH_INT(pc->channel_id);
 		writel_relaxed(int_ctrl, pc->base + PWM_REG_INT_EN(pc->channel_id));
@@ -257,7 +273,7 @@ static int rockchip_pwm_enable(struct pwm_chip *chip,
 
 	if (enable) {
 		val |= enable_conf;
-		if (pc->oneshot)
+		if (pc->oneshot_en)
 			val &= ~PWM_CONTINUOUS;
 	} else {
 		val &= ~enable_conf;
@@ -281,9 +297,11 @@ static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 	bool enabled;
 	int ret = 0;
 
-	ret = clk_enable(pc->pclk);
-	if (ret)
-		return ret;
+	if (!pc->oneshot_en) {
+		ret = clk_enable(pc->pclk);
+		if (ret)
+			return ret;
+	}
 
 	pwm_get_state(pwm, &curstate);
 	enabled = curstate.enabled;
@@ -306,7 +324,8 @@ static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 	if (state->enabled)
 		ret = pinctrl_select_state(pc->pinctrl, pc->active_state);
 out:
-	clk_disable(pc->pclk);
+	if (!pc->oneshot_en)
+		clk_disable(pc->pclk);
 
 	return ret;
 }
@@ -537,7 +556,27 @@ err_clk:
 static int rockchip_pwm_remove(struct platform_device *pdev)
 {
 	struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
+	struct pwm_state state;
+	u32 val;
 
+	/*
+	 * For oneshot mode, it is needed to wait for bit PWM_ENABLE
+	 * to 0, which is automatic if all periods have been sent.
+	 */
+	pwm_get_state(&pc->chip.pwms[0], &state);
+	if (state.enabled) {
+		if (pc->oneshot_en) {
+			if (readl_poll_timeout(pc->base + pc->data->regs.ctrl,
+					       val, !(val & PWM_ENABLE), 1000, 10 * 1000))
+				dev_err(&pdev->dev, "Wait for oneshot to complete failed\n");
+		} else {
+			state.enabled = false;
+			pwm_apply_state(&pc->chip.pwms[0], &state);
+		}
+	}
+
+	if (pc->oneshot_en)
+		clk_disable(pc->pclk);
 	clk_unprepare(pc->pclk);
 	clk_unprepare(pc->clk);
 

From 25030c287cc0cb10ddf0ebc7e24d852a2a27041d Mon Sep 17 00:00:00 2001
From: Cai Wenzhong <cwz@rock-chips.com>
Date: Wed, 31 May 2023 14:28:18 +0800
Subject: [PATCH 08/60] media: i2c: max96712: version 1.03.00

Signed-off-by: Cai Wenzhong <cwz@rock-chips.com>
Change-Id: I3faa1465a4db3edd7337cad2afbdc16f0495f905
---
 drivers/media/i2c/max96712.c | 174 ++++++++++++++++++++++++++++++-----
 1 file changed, 152 insertions(+), 22 deletions(-)

diff --git a/drivers/media/i2c/max96712.c b/drivers/media/i2c/max96712.c
index f1a8dbace008..d5795f52e0d2 100644
--- a/drivers/media/i2c/max96712.c
+++ b/drivers/media/i2c/max96712.c
@@ -11,6 +11,8 @@
  *         support modes enable select.
  *         auto initial deskew enable configure.
  *         frame sync period enable configure.
+ * V1.3.00 t_lpx timing adjust from 53.4ns to 106.7ns.
+ *         mipi dpll predef rate set api.
  *
  */
 
@@ -38,13 +40,13 @@
 #include <media/v4l2-fwnode.h>
 #include <media/v4l2-subdev.h>
 
-#define DRIVER_VERSION			KERNEL_VERSION(1, 0x02, 0x00)
+#define DRIVER_VERSION			KERNEL_VERSION(1, 0x03, 0x00)
 
 #ifndef V4L2_CID_DIGITAL_GAIN
 #define V4L2_CID_DIGITAL_GAIN		V4L2_CID_GAIN
 #endif
 
-#define MAX96712_LINK_FREQ_1000MHZ	1000000000UL
+#define MAX96712_LINK_FREQ_MHZ(x)	((x) * 1000000UL)
 #define MAX96712_XVCLK_FREQ		25000000
 
 #define MAX96712_CHIP_ID		0xA0
@@ -242,16 +244,7 @@ static const struct regval max96712_mipi_4lane_1920x1440_30fps[] = {
 	{ 0x29, 0x090A, 0xc0, 0x00 }, // MIPI PHY 0: 4 lanes, DPHY, 2bit VC
 	{ 0x29, 0x094A, 0xc0, 0x00 }, // MIPI PHY 1: 4 lanes, DPHY, 2bit VC
 	// Turn on MIPI PHYs
-	{ 0x29, 0x08A2, 0x30, 0x00 }, // Enable MIPI PHY 0/1
-	// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
-	{ 0x29, 0x1C00, 0xf4, 0x00 },
-	{ 0x29, 0x1D00, 0xf4, 0x00 },
-	// Set Data rate to be 2000Mbps/lane for port A and enable software override
-	{ 0x29, 0x0415, 0x34, 0x00 }, // Enable freq fine tuning, 2000Mbps
-	{ 0x29, 0x0418, 0x34, 0x00 }, // Enable freq fine tuning, 2000Mbps
-	// Release reset to DPLL (config_soft_rst_n = 1)
-	{ 0x29, 0x1C00, 0xf5, 0x00 },
-	{ 0x29, 0x1D00, 0xf5, 0x00 },
+	{ 0x29, 0x08A2, 0x34, 0x00 }, // Enable MIPI PHY 0/1, t_lpx = 106.7ns
 	// YUV422 8bit software override for all pipes since connected GMSL1 is under parallel mode
 	{ 0x29, 0x040B, 0x80, 0x00 }, // pipe 0 bpp=0x10: Datatypes = 0x22, 0x1E, 0x2E
 	{ 0x29, 0x040E, 0x5e, 0x00 }, // pipe 0 DT=0x1E: YUV422 8-bit
@@ -278,7 +271,7 @@ static const struct max96712_mode supported_modes_4lane[] = {
 			.denominator = 300000,
 		},
 		.reg_list = max96712_mipi_4lane_1920x1440_30fps,
-		.link_freq_idx = 0,
+		.link_freq_idx = 10,
 		.bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
 		.bpp = 16,
 		.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
@@ -288,8 +281,34 @@ static const struct max96712_mode supported_modes_4lane[] = {
 	},
 };
 
+/* link freq = index * MAX96712_LINK_FREQ_MHZ(50) */
 static const s64 link_freq_items[] = {
-	MAX96712_LINK_FREQ_1000MHZ,
+	MAX96712_LINK_FREQ_MHZ(0),
+	MAX96712_LINK_FREQ_MHZ(50),
+	MAX96712_LINK_FREQ_MHZ(100),
+	MAX96712_LINK_FREQ_MHZ(150),
+	MAX96712_LINK_FREQ_MHZ(200),
+	MAX96712_LINK_FREQ_MHZ(250),
+	MAX96712_LINK_FREQ_MHZ(300),
+	MAX96712_LINK_FREQ_MHZ(350),
+	MAX96712_LINK_FREQ_MHZ(400),
+	MAX96712_LINK_FREQ_MHZ(450),
+	MAX96712_LINK_FREQ_MHZ(500),
+	MAX96712_LINK_FREQ_MHZ(550),
+	MAX96712_LINK_FREQ_MHZ(600),
+	MAX96712_LINK_FREQ_MHZ(650),
+	MAX96712_LINK_FREQ_MHZ(700),
+	MAX96712_LINK_FREQ_MHZ(750),
+	MAX96712_LINK_FREQ_MHZ(800),
+	MAX96712_LINK_FREQ_MHZ(850),
+	MAX96712_LINK_FREQ_MHZ(900),
+	MAX96712_LINK_FREQ_MHZ(950),
+	MAX96712_LINK_FREQ_MHZ(1000),
+	MAX96712_LINK_FREQ_MHZ(1050),
+	MAX96712_LINK_FREQ_MHZ(1100),
+	MAX96712_LINK_FREQ_MHZ(1150),
+	MAX96712_LINK_FREQ_MHZ(1200),
+	MAX96712_LINK_FREQ_MHZ(1250),
 };
 
 /* Write registers up to 4 at a time */
@@ -589,6 +608,108 @@ static irqreturn_t max96712_hot_plug_detect_irq_handler(int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
+static int __maybe_unused max96712_dphy_dpll_predef_set(struct i2c_client *client,
+				u32 link_freq_mhz)
+{
+	int ret = 0;
+	u8 dpll_val = 0, dpll_lock = 0;
+	u8 mipi_tx_phy_enable = 0;
+
+	ret = max96712_read_reg(client, MAX96712_I2C_ADDR,
+			0x08A2, MAX96712_REG_VALUE_08BIT, &mipi_tx_phy_enable);
+	if (ret)
+		return ret;
+	mipi_tx_phy_enable = (mipi_tx_phy_enable & 0xF0) >> 4;
+
+	dev_info(&client->dev, "DPLL predef set: mipi_tx_phy_enable = 0x%02x, link_freq_mhz = %d\n",
+			mipi_tx_phy_enable, link_freq_mhz);
+
+	// dphy max data rate is 2500MHz
+	if (link_freq_mhz > (2500 >> 1))
+		link_freq_mhz = (2500 >> 1);
+
+	dpll_val = DIV_ROUND_UP(link_freq_mhz * 2, 100) & 0x1F;
+	// Disable software override for frequency fine tuning
+	dpll_val |= BIT(5);
+
+	// MIPI PHY0
+	if (mipi_tx_phy_enable & BIT(0)) {
+		// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
+		ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
+			0x1C00,
+			MAX96712_REG_VALUE_08BIT,
+			0xf4);
+		// Set data rate and enable software override
+		ret |= max96712_update_reg_bits(client, MAX96712_I2C_ADDR,
+			0x0415, 0x3F, dpll_val);
+		// Release reset to DPLL (config_soft_rst_n = 1)
+		ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
+			0x1C00,
+			MAX96712_REG_VALUE_08BIT,
+			0xf5);
+	}
+
+	// MIPI PHY1
+	if (mipi_tx_phy_enable & BIT(1)) {
+		// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
+		ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
+			0x1D00,
+			MAX96712_REG_VALUE_08BIT,
+			0xf4);
+		// Set data rate and enable software override
+		ret |= max96712_update_reg_bits(client, MAX96712_I2C_ADDR,
+			0x0418, 0x3F, dpll_val);
+		// Release reset to DPLL (config_soft_rst_n = 1)
+		ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
+			0x1D00,
+			MAX96712_REG_VALUE_08BIT,
+			0xf5);
+	}
+
+	// MIPI PHY2
+	if (mipi_tx_phy_enable & BIT(2)) {
+		// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
+		ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
+			0x1E00,
+			MAX96712_REG_VALUE_08BIT,
+			0xf4);
+		// Set data rate and enable software override
+		ret |= max96712_update_reg_bits(client, MAX96712_I2C_ADDR,
+			0x041B, 0x3F, dpll_val);
+		// Release reset to DPLL (config_soft_rst_n = 1)
+		ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
+			0x1E00,
+			MAX96712_REG_VALUE_08BIT,
+			0xf5);
+	}
+
+	// MIPI PHY3
+	if (mipi_tx_phy_enable & BIT(3)) {
+		// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
+		ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
+			0x1F00,
+			MAX96712_REG_VALUE_08BIT,
+			0xf4);
+		// Set data rate and enable software override
+		ret |= max96712_update_reg_bits(client, MAX96712_I2C_ADDR,
+			0x041E, 0x3F, dpll_val);
+		// Release reset to DPLL (config_soft_rst_n = 1)
+		ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
+			0x1F00,
+			MAX96712_REG_VALUE_08BIT,
+			0xf5);
+	}
+
+	ret |= max96712_read_reg(client, MAX96712_I2C_ADDR,
+			0x0400, MAX96712_REG_VALUE_08BIT, &dpll_lock);
+	if (ret)
+		return ret;
+
+	dev_info(&client->dev, "DPLL predef set: dpll_lock = 0x%02x\n", dpll_lock);
+
+	return ret;
+}
+
 static int max96712_auto_init_deskew(struct i2c_client *client, u32 deskew_mask)
 {
 	int ret = 0;
@@ -1070,6 +1191,7 @@ static long max96712_compat_ioctl32(struct v4l2_subdev *sd, unsigned int cmd,
 static int __max96712_start_stream(struct max96712 *max96712)
 {
 	int ret;
+	u32 link_freq_mhz, link_freq_idx;
 
 	ret = max96712_check_link_lock_state(max96712);
 	if (ret)
@@ -1090,6 +1212,12 @@ static int __max96712_start_stream(struct max96712 *max96712)
 			return ret;
 	}
 
+	link_freq_idx = max96712->cur_mode->link_freq_idx;
+	link_freq_mhz = (u32)div_s64(link_freq_items[link_freq_idx], 1000000L);
+	ret = max96712_dphy_dpll_predef_set(max96712->client, link_freq_mhz);
+	if (ret)
+		return ret;
+
 	if (max96712->frame_sync_period != 0) {
 		ret = max96712_frame_sync_period(max96712->client,
 					max96712->frame_sync_period);
@@ -1201,10 +1329,10 @@ static int __max96712_power_on(struct max96712 *max96712)
 	u32 delay_us;
 	struct device *dev = &max96712->client->dev;
 
-	if (!IS_ERR(max96712->power_gpio))
+	if (!IS_ERR(max96712->power_gpio)) {
 		gpiod_set_value_cansleep(max96712->power_gpio, 1);
-
-	usleep_range(1000, 2000);
+		usleep_range(5000, 10000);
+	}
 
 	if (!IS_ERR_OR_NULL(max96712->pins_default)) {
 		ret = pinctrl_select_state(max96712->pinctrl,
@@ -1221,10 +1349,11 @@ static int __max96712_power_on(struct max96712 *max96712)
 		dev_err(dev, "Failed to enable regulators\n");
 		goto disable_clk;
 	}
-	if (!IS_ERR(max96712->reset_gpio))
+	if (!IS_ERR(max96712->reset_gpio)) {
 		gpiod_set_value_cansleep(max96712->reset_gpio, 1);
+		usleep_range(500, 1000);
+	}
 
-	usleep_range(500, 1000);
 	if (!IS_ERR(max96712->pwdn_gpio))
 		gpiod_set_value_cansleep(max96712->pwdn_gpio, 1);
 
@@ -1258,10 +1387,11 @@ static void __max96712_power_off(struct max96712 *max96712)
 		if (ret < 0)
 			dev_dbg(dev, "could not set pins\n");
 	}
-	if (!IS_ERR(max96712->power_gpio))
-		gpiod_set_value_cansleep(max96712->power_gpio, 0);
 
 	regulator_bulk_disable(MAX96712_NUM_SUPPLIES, max96712->supplies);
+
+	if (!IS_ERR(max96712->power_gpio))
+		gpiod_set_value_cansleep(max96712->power_gpio, 0);
 }
 
 static int max96712_runtime_resume(struct device *dev)
@@ -1332,7 +1462,7 @@ static int max96712_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
 	u8 data_lanes = max96712->bus_cfg.bus.mipi_csi2.num_data_lanes;
 
 	val |= V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
-	val |= 1 << (data_lanes - 1);
+	val |= (1 << (data_lanes - 1));
 	switch (data_lanes) {
 	case 4:
 		val |= V4L2_MBUS_CSI2_CHANNEL_3;

From e45c069df7712728c41487b762960483c3815367 Mon Sep 17 00:00:00 2001
From: Xiao Ya peng <yp.xiao@rock-chips.com>
Date: Fri, 19 May 2023 11:56:06 +0800
Subject: [PATCH 09/60] PCI: rockchip: dw_ep: Update pcie ep status.

Add the rkep device mode definition and sync with SPL.

Signed-off-by: Xiao Ya peng <yp.xiao@rock-chips.com>
Change-Id: I60e4809119cf60ddcafe45f6b5ccb11a19aa56e6
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
 .../pci/controller/dwc/pcie-dw-ep-rockchip.c  |  9 ++++++++
 include/uapi/linux/rk-pcie-ep.h               | 22 ++++++++++++++++++-
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c
index fd01beeb78fb..6655bed9a26c 100644
--- a/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c
@@ -149,6 +149,12 @@ static const struct of_device_id rockchip_pcie_ep_of_match[] = {
 
 MODULE_DEVICE_TABLE(of, rockchip_pcie_ep_of_match);
 
+static void rockchip_pcie_devmode_update(struct rockchip_pcie *rockchip, int mode, int submode)
+{
+	rockchip->obj_info->devmode.mode = mode;
+	rockchip->obj_info->devmode.submode = submode;
+}
+
 static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, u32 reg)
 {
 	return readl(rockchip->apb_base + reg);
@@ -294,6 +300,7 @@ static int rockchip_pcie_resource_get(struct platform_device *pdev,
 		memset_io(rockchip->obj_info, 0, sizeof(struct pcie_ep_obj_info));
 		rockchip->obj_info->magic = PCIE_EP_OBJ_INFO_MAGIC;
 		rockchip->obj_info->version = PCIE_EP_OBJ_INFO_DRV_VERSION;
+		rockchip_pcie_devmode_update(rockchip, RKEP_MODE_KERNEL, RKEP_SMODE_INIT);
 	} else {
 		dev_err(dev, "missing bar0 memory region\n");
 		return -ENODEV;
@@ -1173,6 +1180,7 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev)
 	rockchip_pcie_fast_link_setup(rockchip);
 
 	rockchip_pcie_start_link(&rockchip->pci);
+	rockchip_pcie_devmode_update(rockchip, RKEP_MODE_KERNEL, RKEP_SMODE_LNKRDY);
 
 	for (retry = 0; retry < 10000; retry++) {
 		if (dw_pcie_link_up(&rockchip->pci)) {
@@ -1200,6 +1208,7 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev)
 	}
 
 already_linkup:
+	rockchip_pcie_devmode_update(rockchip, RKEP_MODE_KERNEL, RKEP_SMODE_LNKUP);
 	rockchip->pci.iatu_unroll_enabled = rockchip_pcie_iatu_unroll_enabled(&rockchip->pci);
 	for (i = 0; i < PCIE_BAR_MAX_NUM; i++)
 		if (rockchip->ib_target_size[i])
diff --git a/include/uapi/linux/rk-pcie-ep.h b/include/uapi/linux/rk-pcie-ep.h
index 42483e7620a8..b6e3ac04ac2b 100644
--- a/include/uapi/linux/rk-pcie-ep.h
+++ b/include/uapi/linux/rk-pcie-ep.h
@@ -8,6 +8,22 @@
 
 #include <linux/types.h>
 
+/* rkep device mode status definition */
+#define RKEP_MODE_BOOTROM       1
+#define RKEP_MODE_LOADER        2
+#define RKEP_MODE_KERNEL        3
+#define RKEP_MODE_FUN0          4
+/* Common status */
+#define RKEP_SMODE_INIT         0
+#define RKEP_SMODE_LNKRDY       1
+#define RKEP_SMODE_LNKUP        2
+#define RKEP_SMODE_ERR          0xff
+/* Firmware download status */
+#define RKEP_SMODE_FWDLRDY      0x10
+#define RKEP_SMODE_FWDLDONE     0x11
+/* Application status*/
+#define RKEP_SMODE_APPRDY       0x20
+
 /*
  * rockchip pcie driver elbi ioctrl output data
  */
@@ -52,7 +68,11 @@ enum pcie_ep_mmap_resource {
 struct pcie_ep_obj_info {
 	__u32 magic;
 	__u32 version;
-	__u8 reserved[0x1F8];
+	struct {
+		__u16 mode;
+		__u16 submode;
+	} devmode;
+	__u8 reserved[0x1F4];
 
 	__u32 irq_type_rc;					/* Generate in ep isr, valid only for rc, clear in rc */
 	struct pcie_ep_obj_irq_dma_status dma_status_rc;	/* Generate in ep isr, valid only for rc, clear in rc */

From ae995acd3ee1a3fac3afb75d0b59acdc92a96f6a Mon Sep 17 00:00:00 2001
From: David Wu <david.wu@rock-chips.com>
Date: Mon, 8 May 2023 18:47:02 +0800
Subject: [PATCH 10/60] ARM: dts: rv1106: Set flow ctrl off for gmac

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Iec93bbff8f20de69a31dd618111abef04393b8a4
---
 arch/arm/boot/dts/rv1106.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/rv1106.dtsi b/arch/arm/boot/dts/rv1106.dtsi
index 1ba284ed3b19..2d3c4d87dc99 100644
--- a/arch/arm/boot/dts/rv1106.dtsi
+++ b/arch/arm/boot/dts/rv1106.dtsi
@@ -1275,6 +1275,9 @@
 		clock_in_out = "input";
 		phy-handle = <&rmii_phy>;
 
+		/* FLOW_OFF: 0, FLOW_RX: 1, FLOW_TX: 2, FLOW_AUTO: 3 */
+		snps,flow-ctrl = <0>;
+
 		nvmem-cells = <&macphy_bgs>;
 		nvmem-cell-names = "bgs";
 		status = "disabled";

From c91152fefdd06711950a44331e059fa0b07111f6 Mon Sep 17 00:00:00 2001
From: David Wu <david.wu@rock-chips.com>
Date: Tue, 16 May 2023 11:16:58 +0800
Subject: [PATCH 11/60] ARM: dts: rv1106: Change gmac rx dma size to 128

Increase the size to avoid rx overflow.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ie2b1ad948393c8254bf6e20b2cf34b033a3e67c1
---
 arch/arm/boot/dts/rv1106.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/rv1106.dtsi b/arch/arm/boot/dts/rv1106.dtsi
index 2d3c4d87dc99..38e0703778b4 100644
--- a/arch/arm/boot/dts/rv1106.dtsi
+++ b/arch/arm/boot/dts/rv1106.dtsi
@@ -1265,7 +1265,7 @@
 		snps,tso;
 
 		tx-dma-size = <256>;
-		rx-dma-size = <16>;
+		rx-dma-size = <128>;
 
 		snps,axi-config = <&stmmac_axi_setup>;
 		snps,mtl-rx-config = <&mtl_rx_setup>;

From 750f6e702fa2df6ced70c0f5877e7a546f5807df Mon Sep 17 00:00:00 2001
From: Liang Chen <cl@rock-chips.com>
Date: Tue, 30 May 2023 17:09:55 +0800
Subject: [PATCH 12/60] clk: rockchip: rv1106: adjust pvtpll length for cpu

Signed-off-by: Liang Chen <cl@rock-chips.com>
Change-Id: I26b02751a38dad4dc501cbbcd4497636dd6ac991
---
 drivers/clk/rockchip/clk-rv1106.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rv1106.c b/drivers/clk/rockchip/clk-rv1106.c
index 551c3396bc84..0833bf2adb8b 100644
--- a/drivers/clk/rockchip/clk-rv1106.c
+++ b/drivers/clk/rockchip/clk-rv1106.c
@@ -1118,7 +1118,7 @@ static void rockchip_rv1106_pvtpll_init(struct rockchip_clk_provider *ctx)
 	/* set pvtpll ref clk mux */
 	writel_relaxed(CPU_PVTPLL_PATH_CORE, ctx->reg_base + CPU_CLK_PATH_BASE);
 
-	regmap_write(ctx->grf, CPU_PVTPLL_CON0_H, HIWORD_UPDATE(0x6, PVTPLL_LENGTH_SEL_MASK,
+	regmap_write(ctx->grf, CPU_PVTPLL_CON0_H, HIWORD_UPDATE(0x7, PVTPLL_LENGTH_SEL_MASK,
 		     PVTPLL_LENGTH_SEL_SHIFT));
 	regmap_write(ctx->grf, CPU_PVTPLL_CON0_L, HIWORD_UPDATE(0x1, PVTPLL_RING_SEL_MASK,
 		     PVTPLL_RING_SEL_SHIFT));

From bc08d84830a8d9def3d7593c953fcff94ea24e28 Mon Sep 17 00:00:00 2001
From: Sugar Zhang <sugar.zhang@rock-chips.com>
Date: Thu, 1 Jun 2023 11:26:57 +0800
Subject: [PATCH 13/60] ARM: configs: rv1106: Updated by savedefconfig

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I56d8849dd1c0b6a68b55d0533dc22852e8e08846
---
 arch/arm/configs/rv1106_defconfig | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/configs/rv1106_defconfig b/arch/arm/configs/rv1106_defconfig
index 01d5d3502dd7..6f36bc73d8d0 100644
--- a/arch/arm/configs/rv1106_defconfig
+++ b/arch/arm/configs/rv1106_defconfig
@@ -180,12 +180,6 @@ CONFIG_DMABUF_RK_HEAPS_DEBUG=y
 # CONFIG_VIRTIO_MENU is not set
 # CONFIG_VHOST_MENU is not set
 CONFIG_STAGING=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_RK_CONSOLE_THREAD=y
-CONFIG_FIQ_DEBUGGER_FIQ_GLUE=y
 CONFIG_COMMON_CLK_PROCFS=y
 # CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
 # CONFIG_IOMMU_SUPPORT is not set
@@ -193,13 +187,19 @@ CONFIG_CPU_RV1106=y
 CONFIG_ROCKCHIP_AMP=y
 CONFIG_ROCKCHIP_CPUINFO=y
 CONFIG_ROCKCHIP_PVTM=y
+CONFIG_ROCKCHIP_SYSTEM_MONITOR=y
+CONFIG_FIQ_DEBUGGER=y
+CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
+CONFIG_FIQ_DEBUGGER_CONSOLE=y
+CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
+CONFIG_RK_CONSOLE_THREAD=y
+CONFIG_FIQ_DEBUGGER_FIQ_GLUE=y
 CONFIG_ROCKCHIP_NPOR_POWERGOOD=y
 CONFIG_PM_DEVFREQ=y
 CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
 CONFIG_DEVFREQ_GOV_USERSPACE=y
 CONFIG_IIO=y
 CONFIG_ROCKCHIP_SARADC=y
-CONFIG_ROCKCHIP_SYSTEM_MONITOR=y
 CONFIG_PWM=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_CSI2_DPHY=m

From b67f47f2429e2bdbd3c6edf676beab0535e6e7fc Mon Sep 17 00:00:00 2001
From: David Wu <david.wu@rock-chips.com>
Date: Wed, 24 May 2023 17:34:50 +0800
Subject: [PATCH 14/60] net: phy: rk630phy: Add adc performance

Increase ad gain and vcm voltage to get better performance,
If it was 10M speed, also increase eq gain.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I7bad65f14a753c4d3de18c702394d1f91d47dc4a
---
 drivers/net/phy/rk630phy.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/rk630phy.c b/drivers/net/phy/rk630phy.c
index 3579397410b9..b0da4525e3e9 100644
--- a/drivers/net/phy/rk630phy.c
+++ b/drivers/net/phy/rk630phy.c
@@ -219,7 +219,7 @@ static void rk630_phy_t22_config_init(struct phy_device *phydev)
 	/* Switch to page 6 */
 	phy_write(phydev, REG_PAGE_SEL, 0x0600);
 	/* PHYAFE ADC optimization */
-	phy_write(phydev, REG_PAGE6_ADC_ANONTROL, 0x5540);
+	phy_write(phydev, REG_PAGE6_ADC_ANONTROL, 0x555e);
 	/* PHYAFE Gain optimization */
 	phy_write(phydev, REG_PAGE6_GAIN_ANONTROL, 0x0400);
 	/* PHYAFE EQ optimization */
@@ -284,6 +284,23 @@ static int rk630_phy_config_init(struct phy_device *phydev)
 	return 0;
 }
 
+static void rk630_link_change_notify(struct phy_device *phydev)
+{
+	unsigned int val;
+
+	if (phydev->state == PHY_RUNNING || phydev->state == PHY_NOLINK) {
+		/* Switch to page 6 */
+		phy_write(phydev, REG_PAGE_SEL, 0x0600);
+		val = phy_read(phydev, REG_PAGE6_AFE_TX_CTRL);
+		val &= ~GENMASK(14, 13);
+		if (phydev->speed == SPEED_10 && phydev->link)
+			val |= BIT(13);
+		phy_write(phydev, REG_PAGE6_AFE_TX_CTRL, val);
+		/* Switch to page 0 */
+		phy_write(phydev, REG_PAGE_SEL, 0x0000);
+	}
+}
+
 static irqreturn_t rk630_wol_irq_thread(int irq, void *dev_id)
 {
 	struct rk630_phy_priv *priv = (struct rk630_phy_priv *)dev_id;
@@ -369,6 +386,7 @@ static struct phy_driver rk630_phy_driver[] = {
 	.name			= "RK630 PHY",
 	.features		= PHY_BASIC_FEATURES,
 	.flags			= 0,
+	.link_change_notify	= rk630_link_change_notify,
 	.probe			= rk630_phy_probe,
 	.remove			= rk630_phy_remove,
 	.soft_reset		= genphy_soft_reset,

From ec2ae3a6987bd51446261f31f00eec6e6a2e5a96 Mon Sep 17 00:00:00 2001
From: David Wu <david.wu@rock-chips.com>
Date: Wed, 24 May 2023 17:32:09 +0800
Subject: [PATCH 15/60] ARM: dts: rv1106: rmii_phy bgs increment to 2

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I23e7eb6249e53a13adcb8679c55c401e98d290f4
---
 arch/arm/boot/dts/rv1106.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/rv1106.dtsi b/arch/arm/boot/dts/rv1106.dtsi
index 38e0703778b4..f877096e8060 100644
--- a/arch/arm/boot/dts/rv1106.dtsi
+++ b/arch/arm/boot/dts/rv1106.dtsi
@@ -1294,6 +1294,7 @@
 				phy-is-integrated;
 				nvmem-cells = <&macphy_txlevel>;
 				nvmem-cell-names = "txlevel";
+				bgs,increment = <2>;
 			};
 		};
 

From c5e85bafa0c26003714d31feacc7bf46d28660f2 Mon Sep 17 00:00:00 2001
From: Caesar Wang <wxt@rock-chips.com>
Date: Thu, 1 Jun 2023 11:49:02 +0800
Subject: [PATCH 16/60] arm64: dts: rockchip: change dp sound card name on
 rk3588 platform

pulseaudio ucm2 config can not handle the character "," or long name,
so change it.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: Idd25349d3b11e058b391bb5b0c205288ccdb3e74
---
 arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi          | 4 ++--
 arch/arm64/boot/dts/rockchip/rk3588-nvr.dtsi          | 4 ++--
 arch/arm64/boot/dts/rockchip/rk3588-pcie-ep-demo.dtsi | 2 +-
 arch/arm64/boot/dts/rockchip/rk3588-toybrick.dtsi     | 4 ++--
 arch/arm64/boot/dts/rockchip/rk3588-vehicle.dtsi      | 4 ++--
 arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi         | 2 +-
 arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi      | 2 +-
 7 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi
index c9cdc0817251..deb40fdea728 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi
@@ -107,7 +107,7 @@
 	dp0_sound: dp0-sound {
 		status = "disabled";
 		compatible = "rockchip,hdmi";
-		rockchip,card-name= "rockchip,dp0";
+		rockchip,card-name= "rockchip-dp0";
 		rockchip,mclk-fs = <512>;
 		rockchip,cpu = <&spdif_tx2>;
 		rockchip,codec = <&dp0 1>;
@@ -117,7 +117,7 @@
 	dp1_sound: dp1-sound {
 		status = "disabled";
 		compatible = "rockchip,hdmi";
-		rockchip,card-name= "rockchip,dp1";
+		rockchip,card-name= "rockchip-dp1";
 		rockchip,mclk-fs = <512>;
 		rockchip,cpu = <&spdif_tx5>;
 		rockchip,codec = <&dp1 1>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nvr.dtsi
index d9f69e07dd70..0301d6f3118d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-nvr.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nvr.dtsi
@@ -31,7 +31,7 @@
 	dp0_sound: dp0-sound {
 		status = "disabled";
 		compatible = "rockchip,hdmi";
-		rockchip,card-name= "rockchip,dp0";
+		rockchip,card-name= "rockchip-dp0";
 		rockchip,mclk-fs = <512>;
 		rockchip,cpu = <&spdif_tx2>;
 		rockchip,codec = <&dp0 1>;
@@ -41,7 +41,7 @@
 	dp1_sound: dp1-sound {
 		status = "disabled";
 		compatible = "rockchip,hdmi";
-		rockchip,card-name= "rockchip,dp1";
+		rockchip,card-name= "rockchip-dp1";
 		rockchip,mclk-fs = <512>;
 		rockchip,cpu = <&spdif_tx5>;
 		rockchip,codec = <&dp1 1>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-pcie-ep-demo.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-pcie-ep-demo.dtsi
index 65ff203aab31..f44fd9e15c00 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-pcie-ep-demo.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-pcie-ep-demo.dtsi
@@ -32,7 +32,7 @@
 	dp0_sound: dp0-sound {
 		status = "disabled";
 		compatible = "rockchip,hdmi";
-		rockchip,card-name= "rockchip,dp0";
+		rockchip,card-name= "rockchip-dp0";
 		rockchip,mclk-fs = <512>;
 		rockchip,cpu = <&spdif_tx2>;
 		rockchip,codec = <&dp0 1>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-toybrick.dtsi
index ae4131045a07..a76bedcfcdc1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-toybrick.dtsi
@@ -87,7 +87,7 @@
 	dp0_sound: dp0-sound {
 		status = "disabled";
 		compatible = "rockchip,hdmi";
-		rockchip,card-name= "rockchip,dp0";
+		rockchip,card-name= "rockchip-dp0";
 		rockchip,mclk-fs = <512>;
 		rockchip,cpu = <&spdif_tx2>;
 		rockchip,codec = <&dp0 1>;
@@ -97,7 +97,7 @@
 	dp1_sound: dp1-sound {
 		status = "disabled";
 		compatible = "rockchip,hdmi";
-		rockchip,card-name= "rockchip,dp1";
+		rockchip,card-name= "rockchip-dp1";
 		rockchip,mclk-fs = <512>;
 		rockchip,cpu = <&spdif_tx5>;
 		rockchip,codec = <&dp1 1>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle.dtsi
index 383591104b0e..f4498cdd21c9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle.dtsi
@@ -107,7 +107,7 @@
 	dp0_sound: dp0-sound {
 		status = "disabled";
 		compatible = "rockchip,hdmi";
-		rockchip,card-name= "rockchip,dp0";
+		rockchip,card-name= "rockchip-dp0";
 		rockchip,mclk-fs = <512>;
 		rockchip,cpu = <&spdif_tx2>;
 		rockchip,codec = <&dp0 1>;
@@ -117,7 +117,7 @@
 	dp1_sound: dp1-sound {
 		status = "disabled";
 		compatible = "rockchip,hdmi";
-		rockchip,card-name= "rockchip,dp1";
+		rockchip,card-name= "rockchip-dp1";
 		rockchip,mclk-fs = <512>;
 		rockchip,cpu = <&spdif_tx5>;
 		rockchip,codec = <&dp1 1>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi
index 6db4c5734836..586c6277449c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi
@@ -87,7 +87,7 @@
 	dp0_sound: dp0-sound {
 		status = "disabled";
 		compatible = "rockchip,hdmi";
-		rockchip,card-name= "rockchip,dp0";
+		rockchip,card-name= "rockchip-dp0";
 		rockchip,mclk-fs = <512>;
 		rockchip,cpu = <&spdif_tx2>;
 		rockchip,codec = <&dp0 1>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi
index b61a843ef28f..2a78a4eb05a1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi
@@ -114,7 +114,7 @@
 	dp0_sound: dp0-sound {
 		status = "okay";
 		compatible = "rockchip,hdmi";
-		rockchip,card-name= "rockchip,dp0";
+		rockchip,card-name= "rockchip-dp0";
 		rockchip,mclk-fs = <512>;
 		rockchip,cpu = <&spdif_tx2>;
 		rockchip,codec = <&dp0 1>;

From 757588ef41194cc7328892186573978cfdc34691 Mon Sep 17 00:00:00 2001
From: David Wu <david.wu@rock-chips.com>
Date: Tue, 30 May 2023 10:28:58 +0800
Subject: [PATCH 17/60] ethernet: stmmac: dwmac-rk: Fix Dribble bit error at
 10M mode

At the 10M mode, gmac can detect odd nibbles package sometimes,
this is valid at mii mode. Make 25M at init for rmii mode, can
solve the issue by tests.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I22dc619fbc9983d4b58efc42c5c92d0f8c8aaab5
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index fc4398406338..f4f756125e15 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -1446,7 +1446,8 @@ static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
 			     RK3528_GMAC1_PHY_INTF_SEL_RMII);
 	else
 		regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,
-			     RK3528_GMAC0_PHY_INTF_SEL_RMII);
+			     RK3528_GMAC0_PHY_INTF_SEL_RMII |
+			     RK3528_GMAC0_CLK_RMII_DIV2);
 }
 
 static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
@@ -2022,7 +2023,8 @@ static void rv1106_set_to_rmii(struct rk_priv_data *bsp_priv)
 	}
 
 	regmap_write(bsp_priv->grf, RV1106_VOGRF_GMAC_CLK_CON,
-		     RV1106_VOGRF_MACPHY_RMII_MODE);
+		     RV1106_VOGRF_MACPHY_RMII_MODE |
+		     RV1106_VOGRF_GMAC_CLK_RMII_DIV2);
 }
 
 static void rv1106_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)

From ee144563a528bc2558c4a34e9be0368f49dae9ae Mon Sep 17 00:00:00 2001
From: David Wu <david.wu@rock-chips.com>
Date: Tue, 30 May 2023 14:32:52 +0800
Subject: [PATCH 18/60] net: phy: rk630: Enable aps && uaps to save power
 consumption

aps and uaps can save power consumption when RJ45 plug out.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Iec36feb6ba1d734408efa9430e7889015c9d3fd1
---
 drivers/net/phy/rk630phy.c | 27 ++++++++++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)

diff --git a/drivers/net/phy/rk630phy.c b/drivers/net/phy/rk630phy.c
index b0da4525e3e9..471baeca43a8 100644
--- a/drivers/net/phy/rk630phy.c
+++ b/drivers/net/phy/rk630phy.c
@@ -160,14 +160,33 @@ static void rk630_phy_ieee_set(struct phy_device *phydev, bool enable)
 	phy_write(phydev, REG_PAGE_SEL, 0x0000);
 }
 
-static void rk630_phy_set_uaps(struct phy_device *phydev)
+static void rk630_phy_set_aps(struct phy_device *phydev, bool enable)
+{
+	u32 value;
+
+	/* Switch to page 1 */
+	phy_write(phydev, REG_PAGE_SEL, 0x0100);
+	value = phy_read(phydev, REG_PAGE1_APS_CTRL);
+	if (enable)
+		value |= BIT(15);
+	else
+		value &= ~BIT(15);
+	phy_write(phydev, REG_PAGE1_APS_CTRL, value);
+	/* Switch to page 0 */
+	phy_write(phydev, REG_PAGE_SEL, 0x0000);
+}
+
+static void rk630_phy_set_uaps(struct phy_device *phydev, bool enable)
 {
 	u32 value;
 
 	/* Switch to page 1 */
 	phy_write(phydev, REG_PAGE_SEL, 0x0100);
 	value = phy_read(phydev, REG_PAGE1_UAPS_CONFIGURE);
-	value |= BIT(15);
+	if (enable)
+		value |= BIT(15);
+	else
+		value &= ~BIT(15);
 	phy_write(phydev, REG_PAGE1_UAPS_CONFIGURE, value);
 	/* Switch to page 0 */
 	phy_write(phydev, REG_PAGE_SEL, 0x0000);
@@ -268,10 +287,12 @@ static int rk630_phy_config_init(struct phy_device *phydev)
 		 * Ultra Auto-Power Saving Mode (UAPS) is designed to
 		 * save power when cable is not plugged into PHY.
 		 */
-		rk630_phy_set_uaps(phydev);
+		rk630_phy_set_uaps(phydev, true);
 		break;
 	case PHY_ADDR_T22:
 		rk630_phy_t22_config_init(phydev);
+		rk630_phy_set_aps(phydev, true);
+		rk630_phy_set_uaps(phydev, true);
 		break;
 	default:
 		phydev_err(phydev, "Unsupported address for current phy: %d\n",

From b2dbb37c586a404949d94ae2a4becf72670924aa Mon Sep 17 00:00:00 2001
From: Sugar Zhang <sugar.zhang@rock-chips.com>
Date: Thu, 1 Jun 2023 11:33:41 +0800
Subject: [PATCH 19/60] ARM: configs: rv1106: Optimize for cpu load

-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_HZ_300=y

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I68fe3a17e0a4b05ca724862ef3ad44d81280f4f4
---
 arch/arm/configs/rv1106_defconfig | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/configs/rv1106_defconfig b/arch/arm/configs/rv1106_defconfig
index 6f36bc73d8d0..dfe7208ad22c 100644
--- a/arch/arm/configs/rv1106_defconfig
+++ b/arch/arm/configs/rv1106_defconfig
@@ -4,8 +4,6 @@ CONFIG_DEFAULT_HOSTNAME="localhost"
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 # CONFIG_BUG is not set
@@ -18,7 +16,6 @@ CONFIG_EMBEDDED=y
 CONFIG_ARCH_ROCKCHIP=y
 # CONFIG_VDSO is not set
 CONFIG_VMSPLIT_3G_OPT=y
-CONFIG_HZ_300=y
 CONFIG_THUMB2_KERNEL=y
 # CONFIG_CPU_SW_DOMAIN_PAN is not set
 CONFIG_FORCE_MAX_ZONEORDER=9

From 776837f7b4fc9376817d5ee6d3145b3eaf403ee1 Mon Sep 17 00:00:00 2001
From: Cai Wenzhong <cwz@rock-chips.com>
Date: Thu, 1 Jun 2023 16:38:35 +0800
Subject: [PATCH 20/60] media: i2c: max96712: fix 4 lane mode mipi link freq
 index setting error.

Signed-off-by: Cai Wenzhong <cwz@rock-chips.com>
Change-Id: Id1c1add779df6ec7c041cec53243645f8b2159d0
---
 drivers/media/i2c/max96712.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/media/i2c/max96712.c b/drivers/media/i2c/max96712.c
index d5795f52e0d2..dec31723107a 100644
--- a/drivers/media/i2c/max96712.c
+++ b/drivers/media/i2c/max96712.c
@@ -271,7 +271,7 @@ static const struct max96712_mode supported_modes_4lane[] = {
 			.denominator = 300000,
 		},
 		.reg_list = max96712_mipi_4lane_1920x1440_30fps,
-		.link_freq_idx = 10,
+		.link_freq_idx = 20,
 		.bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
 		.bpp = 16,
 		.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,

From 6e8bd488603a2a8793f59b50625e38d37ad501a6 Mon Sep 17 00:00:00 2001
From: Cai Wenzhong <cwz@rock-chips.com>
Date: Thu, 1 Jun 2023 09:40:10 +0800
Subject: [PATCH 21/60] arm64: dts: rockchip:
 rk3588-vehicle-evb-maxim-max96712: default disable fsync

Signed-off-by: Cai Wenzhong <cwz@rock-chips.com>
Change-Id: I3b56dacded01bbbbbb1898a0ed0f8d557851f7d7
---
 .../boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712.dtsi    | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712.dtsi
index 244f3ea1888f..491a59e2352f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712.dtsi
@@ -64,7 +64,7 @@
 		//reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
 		lock-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;
 		auto-init-deskew-mask = <0x03>;
-		frame-sync-period = <30>;
+		frame-sync-period = <0>;
 		rockchip,camera-module-index = <0>;
 		rockchip,camera-module-facing = "back";
 		rockchip,camera-module-name = "max96712";

From b2216221577aceeff17c27c1faeabb1a5257063c Mon Sep 17 00:00:00 2001
From: David Wu <david.wu@rock-chips.com>
Date: Wed, 24 May 2023 17:30:07 +0800
Subject: [PATCH 22/60] ethernet: stmmac: dwmac-rk: Add bgs increment

Add the configuration of BGS from DTB.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I0549f1a9327827441e83d7b17f20719026e8f27c
---
 .../net/ethernet/stmicro/stmmac/dwmac-rk.c    | 26 ++++++++++++++++---
 1 file changed, 23 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index f4f756125e15..cf9c46ea426e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -79,6 +79,7 @@ struct rk_priv_data {
 	struct regmap *xpcs;
 
 	unsigned char otp_data;
+	unsigned int bgs_increment;
 };
 
 /* XPCS */
@@ -279,6 +280,8 @@ static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv)
 
 #define RK_FEPHY_BGS			HIWORD_UPDATE(0x0, 0xf, 0)
 
+#define RK_FEPHY_BGS_MAX		7
+
 static void rk_gmac_integrated_fephy_power(struct rk_priv_data *priv,
 					   unsigned int ctrl_offset,
 					   unsigned int bgs_offset,
@@ -293,7 +296,7 @@ static void rk_gmac_integrated_fephy_power(struct rk_priv_data *priv,
 	}
 
 	if (up) {
-		unsigned int bgs = RK_FEPHY_BGS;
+		unsigned int bgs = priv->otp_data;
 
 		reset_control_assert(priv->phy_reset);
 		udelay(20);
@@ -303,8 +306,14 @@ static void rk_gmac_integrated_fephy_power(struct rk_priv_data *priv,
 			     RK_FEPHY_24M_CLK_SEL |
 			     RK_FEPHY_PHY_ID);
 
-		if (priv->otp_data > 0)
-			bgs = HIWORD_UPDATE(priv->otp_data, 0xf, 0);
+		if (bgs > (RK_FEPHY_BGS_MAX - priv->bgs_increment) &&
+		    bgs <= RK_FEPHY_BGS_MAX) {
+			bgs = HIWORD_UPDATE(RK_FEPHY_BGS_MAX, 0xf, 0);
+		} else {
+			bgs += priv->bgs_increment;
+			bgs &= 0xf;
+			bgs = HIWORD_UPDATE(bgs, 0xf, 0);
+		}
 
 		regmap_write(priv->grf, bgs_offset, bgs);
 		usleep_range(10 * 1000, 12 * 1000);
@@ -2520,6 +2529,17 @@ static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
 				bsp_priv->phy_reset = NULL;
 			}
 
+			if (of_property_read_u32(plat->phy_node, "bgs,increment",
+						 &bsp_priv->bgs_increment)) {
+				bsp_priv->bgs_increment = 0;
+			} else {
+				if (bsp_priv->bgs_increment > RK_FEPHY_BGS_MAX) {
+					dev_err(dev, "%s: error bgs increment: %d\n",
+						__func__, bsp_priv->bgs_increment);
+					bsp_priv->bgs_increment = RK_FEPHY_BGS_MAX;
+				}
+			}
+
 			/* Read bgs from OTP if it exists */
 			cell = nvmem_cell_get(dev, "bgs");
 			if (IS_ERR(cell)) {

From 7aaa4bb7a27f1e4649b1a1eb5ccbc1a562c8aab8 Mon Sep 17 00:00:00 2001
From: Jianqun Xu <jay.xu@rock-chips.com>
Date: Thu, 1 Jun 2023 15:43:52 +0800
Subject: [PATCH 23/60] ASoC: rockchip: i2s-tdm: try normal clear before switch
 master mode

As mind by sugar, sometimes the master device will exit unexpectly, stop
the sclk before the slave device to do stop trigger, for example the bt
module, which not act as a codec driver, is replaced by a dummy codec.

This patch adds a normal clear for i2s tdm before force switch to
master.

Fixes: c003b7fd8a44 ("ASoC: rockchip: i2s-tdm: Fix FIFO Clear failed on SLAVE mode sometimes")

Change-Id: Ia3ae2d9b008b07addcfcec38d4e970c376dae1e7
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
 sound/soc/rockchip/rockchip_i2s_tdm.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/sound/soc/rockchip/rockchip_i2s_tdm.c b/sound/soc/rockchip/rockchip_i2s_tdm.c
index 2ff2b9c4a020..a8da138200ad 100644
--- a/sound/soc/rockchip/rockchip_i2s_tdm.c
+++ b/sound/soc/rockchip/rockchip_i2s_tdm.c
@@ -397,6 +397,12 @@ static int rockchip_i2s_tdm_clear(struct rk_i2s_tdm_dev *i2s_tdm,
 		return -EINVAL;
 	}
 
+	regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr);
+	ret = regmap_read_poll_timeout_atomic(i2s_tdm->regmap, I2S_CLR, val,
+					      !(val & clr), 10, 100);
+	if (ret == 0)
+		return 0;
+
 	/*
 	 * Workaround for FIFO clear on SLAVE mode:
 	 *

From 010c01545519c5d305a50af092781ab303ba8e8d Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Tue, 23 May 2023 19:18:05 +0800
Subject: [PATCH 24/60] phy: rockchip: naneng-combphy: Fix swing to 650mv under
 100M refclk for rk3528

Change-Id: I30b988fe60a09ad3aafd6527238926526b1c3693
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index b2517e02f2e8..5b8ca4686fb4 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -519,10 +519,8 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
 			val |= 0x2 << 10;
 			writel(val, priv->mmio + 0x18);
 
-			/* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */
-			val = readl(priv->mmio + 0x108);
-			val &= ~(0x7f7);
-			val |= 0x4f0;
+			/* su_trim[6:4]=111, [10:7]=1001, [2:0]=000, swing 650mv */
+			val = 0x570804f0;
 			writel(val, priv->mmio + 0x108);
 		}
 		break;

From 13639746faf395861e0a1f27bae82cc5388a2251 Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Tue, 23 May 2023 20:04:57 +0800
Subject: [PATCH 25/60] phy: rockchip: naneng-combphy: Fix swing to 650mv under
 100M refclk for rk3562

Change-Id: Ia71ec0851c1d1bc686277a49af70488f413f423c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index 5b8ca4686fb4..42ef316599fa 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -684,6 +684,12 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
 
 			writel(0x32, priv->mmio + (0x11 << 2));
 			writel(0xf0, priv->mmio + (0xa << 2));
+
+			/* CKDRV output swing adjust to 650mv */
+			val = readl(priv->mmio + (0xd << 2));
+			val &= ~(0xf << 1);
+			val |= 0xb;
+			writel(val, priv->mmio + (0xd << 2));
 		}
 		break;
 	default:

From b41e989448119db75135f60b43f186ccb9fef59f Mon Sep 17 00:00:00 2001
From: Cai Wenzhong <cwz@rock-chips.com>
Date: Thu, 1 Jun 2023 15:09:21 +0800
Subject: [PATCH 26/60] media: i2c: max96712: add poc_en gpio conctrol for
 remote camera power suppply.

1. poc_en gpio control remote camera 12V power supply: active high.
2. max96712_V11 board need to control poc_en for remote camera power supply.

Signed-off-by: Cai Wenzhong <cwz@rock-chips.com>
Change-Id: Ica5c446ce85877efd18ccca7180a8b18da609297
---
 drivers/media/i2c/max96712.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/media/i2c/max96712.c b/drivers/media/i2c/max96712.c
index dec31723107a..9cd5d41a0f6b 100644
--- a/drivers/media/i2c/max96712.c
+++ b/drivers/media/i2c/max96712.c
@@ -129,6 +129,7 @@ struct max96712 {
 	struct gpio_desc *power_gpio;
 	struct gpio_desc *reset_gpio;
 	struct gpio_desc *pwdn_gpio;
+	struct gpio_desc *pocen_gpio;
 	struct gpio_desc *lock_gpio;
 	struct regulator_bulk_data supplies[MAX96712_NUM_SUPPLIES];
 
@@ -1334,6 +1335,11 @@ static int __max96712_power_on(struct max96712 *max96712)
 		usleep_range(5000, 10000);
 	}
 
+	if (!IS_ERR(max96712->pocen_gpio)) {
+		gpiod_set_value_cansleep(max96712->pocen_gpio, 1);
+		usleep_range(5000, 10000);
+	}
+
 	if (!IS_ERR_OR_NULL(max96712->pins_default)) {
 		ret = pinctrl_select_state(max96712->pinctrl,
 					   max96712->pins_default);
@@ -1390,6 +1396,9 @@ static void __max96712_power_off(struct max96712 *max96712)
 
 	regulator_bulk_disable(MAX96712_NUM_SUPPLIES, max96712->supplies);
 
+	if (!IS_ERR(max96712->pocen_gpio))
+		gpiod_set_value_cansleep(max96712->pocen_gpio, 0);
+
 	if (!IS_ERR(max96712->power_gpio))
 		gpiod_set_value_cansleep(max96712->power_gpio, 0);
 }
@@ -1724,6 +1733,10 @@ static int max96712_probe(struct i2c_client *client,
 	if (IS_ERR(max96712->pwdn_gpio))
 		dev_warn(dev, "Failed to get pwdn-gpios\n");
 
+	max96712->pocen_gpio = devm_gpiod_get(dev, "pocen", GPIOD_OUT_LOW);
+	if (IS_ERR(max96712->pocen_gpio))
+		dev_warn(dev, "Failed to get pocen-gpios\n");
+
 	max96712->lock_gpio = devm_gpiod_get(dev, "lock", GPIOD_IN);
 	if (IS_ERR(max96712->lock_gpio))
 		dev_warn(dev, "Failed to get lock-gpios\n");

From e8913fed9fd95c227f2970c17d0a50fddce445af Mon Sep 17 00:00:00 2001
From: Cai Wenzhong <cwz@rock-chips.com>
Date: Thu, 1 Jun 2023 16:19:35 +0800
Subject: [PATCH 27/60] arm64: dts: rockchip: rk3588-vehicle-max96712: add
 pocen-gpios for dphy1 poc_en.

Signed-off-by: Cai Wenzhong <cwz@rock-chips.com>
Change-Id: Iad0c9a35c662dbc54062ea7afff78fb18dd9bc56
---
 .../boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712.dtsi     | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712.dtsi
index 491a59e2352f..4daa67699c94 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712.dtsi
@@ -61,6 +61,7 @@
 		power-domains = <&power RK3588_PD_VI>;
 		rockchip,grf = <&sys_grf>;
 		power-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pocen-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
 		//reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
 		lock-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;
 		auto-init-deskew-mask = <0x03>;

From 760cdbbc1982973b818b5e925d958df2fd80c263 Mon Sep 17 00:00:00 2001
From: Xing Zheng <zhengxing@rock-chips.com>
Date: Sat, 27 May 2023 18:13:24 +0800
Subject: [PATCH 28/60] ASoC: es8323: fix 32kHz coeff configurations

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Change-Id: I2f74a42dd133c40e90b29b872f41d1d501913d8e
---
 sound/soc/codecs/es8323.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/soc/codecs/es8323.c b/sound/soc/codecs/es8323.c
index 4fc6bc5d5ed7..5ffdbe3b5f99 100644
--- a/sound/soc/codecs/es8323.c
+++ b/sound/soc/codecs/es8323.c
@@ -382,8 +382,8 @@ static const struct _coeff_div coeff_div[] = {
 	{12000000, 22050, 544, 0x6, 0x1},
 
 	/* 32k */
-	{8192000, 16000, 256, 0x2, 0x0},
-	{16384000, 16000, 512, 0x4, 0x0},
+	{8192000, 32000, 256, 0x2, 0x0},
+	{16384000, 32000, 512, 0x4, 0x0},
 	{12288000, 32000, 384, 0x3, 0x0},
 	{18432000, 32000, 576, 0x5, 0x0},
 	{12000000, 32000, 375, 0x4, 0x1},

From 3f2bd708992d05062e7e526ecf4c36981e33ea9f Mon Sep 17 00:00:00 2001
From: Wangqiang Guo <kay.guo@rock-chips.com>
Date: Thu, 18 May 2023 03:43:12 +0000
Subject: [PATCH 29/60] media: rockchip: hdmirx: notify the bound cpu to bl31.

Change-Id: I4354213eb23c734626a7b51ee90feb31d6a66c3e
Signed-off-by: Wangqiang Guo <kay.guo@rock-chips.com>
---
 drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c b/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c
index 91c85ccf742f..067314d49162 100644
--- a/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c
+++ b/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c
@@ -2032,6 +2032,7 @@ static int hdmirx_start_streaming(struct vb2_queue *queue, unsigned int count)
 	struct v4l2_dv_timings timings = hdmirx_dev->timings;
 	struct v4l2_bt_timings *bt = &timings.bt;
 	int line_flag;
+	uint32_t touch_flag;
 
 	if (!hdmirx_dev->get_timing) {
 		v4l2_err(v4l2_dev, "Err, timing is invalid\n");
@@ -2045,7 +2046,8 @@ static int hdmirx_start_streaming(struct vb2_queue *queue, unsigned int count)
 	}
 
 	mutex_lock(&hdmirx_dev->stream_lock);
-	sip_hdmirx_config(HDMIRX_AUTO_TOUCH_EN, 0, 1, 100);
+	touch_flag = (hdmirx_dev->bound_cpu << 1) | 0x1;
+	sip_hdmirx_config(HDMIRX_AUTO_TOUCH_EN, 0, touch_flag, 100);
 	stream->frame_idx = 0;
 	stream->line_flag_int_cnt = 0;
 	stream->curr_buf = NULL;
@@ -4176,9 +4178,6 @@ static int hdmirx_probe(struct platform_device *pdev)
 			__func__, cpu_aff,
 			hdmirx_dev->bound_cpu,
 			hdmirx_dev->wdt_cfg_bound_cpu);
-	if (hdmirx_dev->bound_cpu != 4)
-		dev_err(dev, "%s: Bound_cpu:%d, expect bound cpu 4!\n",
-			__func__, hdmirx_dev->bound_cpu);
 	cpu_latency_qos_add_request(&hdmirx_dev->pm_qos, PM_QOS_DEFAULT_VALUE);
 
 	mutex_init(&hdmirx_dev->stream_lock);

From 0eee997bed4a7842442f7670ef02ff435b922d48 Mon Sep 17 00:00:00 2001
From: Cai Wenzhong <cwz@rock-chips.com>
Date: Thu, 1 Jun 2023 18:48:20 +0800
Subject: [PATCH 30/60] media: i2c: max96712: add rk3588 dcphy param get and
 set ioctl cmd.

Signed-off-by: Cai Wenzhong <cwz@rock-chips.com>
Change-Id: Ie548dbecfd049b70a19ef1232530bbcc238c75b4
---
 drivers/media/i2c/max96712.c | 54 ++++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/drivers/media/i2c/max96712.c b/drivers/media/i2c/max96712.c
index 9cd5d41a0f6b..d47209e3c7fb 100644
--- a/drivers/media/i2c/max96712.c
+++ b/drivers/media/i2c/max96712.c
@@ -176,6 +176,17 @@ static const struct regmap_config max96712_regmap_config = {
 	.max_register = 0x1F17,
 };
 
+static struct rkmodule_csi_dphy_param rk3588_dcphy_param = {
+	.vendor = PHY_VENDOR_SAMSUNG,
+	.lp_vol_ref = 3,
+	.lp_hys_sw = {3, 0, 0, 0},
+	.lp_escclk_pol_sel = {1, 0, 0, 0},
+	.skew_data_cal_clk = {0, 0, 0, 0},
+	.clk_hs_term_sel = 2,
+	.data_hs_term_sel = {2, 2, 2, 2},
+	.reserved = {0},
+};
+
 static const struct regval max96712_mipi_4lane_1920x1440_30fps[] = {
 	// Link A/B/C/D all use GMSL2, and disabled
 	{ 0x29, 0x0006, 0xf0, 0x00 }, // Link A/B/C/D: select GMSL2, Disabled
@@ -1053,6 +1064,7 @@ max96712_set_vicap_rst_inf(struct max96712 *max96712,
 static long max96712_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
 {
 	struct max96712 *max96712 = v4l2_get_subdevdata(sd);
+	struct rkmodule_csi_dphy_param *dphy_param;
 	long ret = 0;
 	u32 stream = 0;
 
@@ -1078,6 +1090,18 @@ static long max96712_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
 		break;
 	case RKMODULE_GET_START_STREAM_SEQ:
 		break;
+	case RKMODULE_SET_CSI_DPHY_PARAM:
+		dphy_param = (struct rkmodule_csi_dphy_param *)arg;
+		if (dphy_param->vendor == rk3588_dcphy_param.vendor)
+			rk3588_dcphy_param = *dphy_param;
+		dev_dbg(&max96712->client->dev, "sensor set dphy param\n");
+		break;
+	case RKMODULE_GET_CSI_DPHY_PARAM:
+		dphy_param = (struct rkmodule_csi_dphy_param *)arg;
+		if (dphy_param->vendor == rk3588_dcphy_param.vendor)
+			*dphy_param = rk3588_dcphy_param;
+		dev_dbg(&max96712->client->dev, "sensor get dphy param\n");
+		break;
 	default:
 		ret = -ENOIOCTLCMD;
 		break;
@@ -1094,6 +1118,7 @@ static long max96712_compat_ioctl32(struct v4l2_subdev *sd, unsigned int cmd,
 	struct rkmodule_inf *inf;
 	struct rkmodule_awb_cfg *cfg;
 	struct rkmodule_vicap_reset_info *vicap_rst_inf;
+	struct rkmodule_csi_dphy_param *dphy_param;
 	long ret = 0;
 	int *seq;
 	u32 stream = 0;
@@ -1180,6 +1205,35 @@ static long max96712_compat_ioctl32(struct v4l2_subdev *sd, unsigned int cmd,
 		else
 			ret = -EFAULT;
 		break;
+	case RKMODULE_SET_CSI_DPHY_PARAM:
+		dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL);
+		if (!dphy_param) {
+			ret = -ENOMEM;
+			return ret;
+		}
+
+		ret = copy_from_user(dphy_param, up, sizeof(*dphy_param));
+		if (!ret)
+			ret = max96712_ioctl(sd, cmd, dphy_param);
+		else
+			ret = -EFAULT;
+		kfree(dphy_param);
+		break;
+	case RKMODULE_GET_CSI_DPHY_PARAM:
+		dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL);
+		if (!dphy_param) {
+			ret = -ENOMEM;
+			return ret;
+		}
+
+		ret = max96712_ioctl(sd, cmd, dphy_param);
+		if (!ret) {
+			ret = copy_to_user(up, dphy_param, sizeof(*dphy_param));
+			if (ret)
+				ret = -EFAULT;
+		}
+		kfree(dphy_param);
+		break;
 	default:
 		ret = -ENOIOCTLCMD;
 		break;

From ee55fc9efad1aa549962db692ba932007d47ee77 Mon Sep 17 00:00:00 2001
From: Yu Qiaowei <cerf.yu@rock-chips.com>
Date: Wed, 31 May 2023 08:44:16 +0000
Subject: [PATCH 31/60] video: rockchip: rga3: fix compile errors on kernel-6.1

Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I3b0de1f1da992975c13f99de7574ff0cd0865e25
---
 drivers/video/rockchip/rga3/rga_dma_buf.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/video/rockchip/rga3/rga_dma_buf.c b/drivers/video/rockchip/rga3/rga_dma_buf.c
index 7459d9211a01..718010088d5a 100644
--- a/drivers/video/rockchip/rga3/rga_dma_buf.c
+++ b/drivers/video/rockchip/rga3/rga_dma_buf.c
@@ -209,6 +209,8 @@ static dma_addr_t rga_iommu_dma_alloc_iova(struct iommu_domain *domain,
 
 	shift = iova_shift(iovad);
 	iova_len = size >> shift;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
 	/*
 	 * Freeing non-power-of-two-sized allocations back into the IOVA caches
 	 * will come back to bite us badly, so we have to waste a bit of space
@@ -217,6 +219,7 @@ static dma_addr_t rga_iommu_dma_alloc_iova(struct iommu_domain *domain,
 	 */
 	if (iova_len < (1 << (IOVA_RANGE_CACHE_MAX_SIZE - 1)))
 		iova_len = roundup_pow_of_two(iova_len);
+#endif
 
 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0))
 	dma_limit = min_not_zero(dma_limit, dev->bus_dma_limit);

From 840f3f259f00ea9c8cc261aeac541506f7d24a22 Mon Sep 17 00:00:00 2001
From: Weiwen Chen <cww@rock-chips.com>
Date: Tue, 30 May 2023 10:20:47 +0800
Subject: [PATCH 32/60] ARM: configs: add rv1106-nand.config

Change-Id: Ibdc0c656f9a371c90ebf68b35d7274badfc9ba41
Signed-off-by: Weiwen Chen <cww@rock-chips.com>
---
 arch/arm/configs/rv1106-nand.config | 122 ++++++++++++++++++++++++++++
 1 file changed, 122 insertions(+)
 create mode 100644 arch/arm/configs/rv1106-nand.config

diff --git a/arch/arm/configs/rv1106-nand.config b/arch/arm/configs/rv1106-nand.config
new file mode 100644
index 000000000000..00af96cd9eb9
--- /dev/null
+++ b/arch/arm/configs/rv1106-nand.config
@@ -0,0 +1,122 @@
+CONFIG_CRC16=y
+CONFIG_CRYPTO=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_UBI=y
+# CONFIG_ARM_CRYPTO is not set
+# CONFIG_CRYPTO_842 is not set
+CONFIG_CRYPTO_ACOMP2=y
+# CONFIG_CRYPTO_ADIANTUM is not set
+# CONFIG_CRYPTO_AEGIS128 is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_AES_TI is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_BLAKE2B is not set
+# CONFIG_CRYPTO_BLAKE2S is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_CFB is not set
+# CONFIG_CRYPTO_CHACHA20 is not set
+# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
+# CONFIG_CRYPTO_CMAC is not set
+# CONFIG_CRYPTO_CRC32 is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CRCT10DIF is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_CURVE25519 is not set
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set
+# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
+# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
+# CONFIG_CRYPTO_DEV_CCREE is not set
+# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
+# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
+# CONFIG_CRYPTO_DH is not set
+# CONFIG_CRYPTO_DRBG_MENU is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_ECDH is not set
+# CONFIG_CRYPTO_ECHAINIV is not set
+# CONFIG_CRYPTO_ECRDSA is not set
+# CONFIG_CRYPTO_ESSIV is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_GHASH is not set
+CONFIG_CRYPTO_HASH_INFO=y
+# CONFIG_CRYPTO_HMAC is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_JITTERENTROPY is not set
+# CONFIG_CRYPTO_KEYWRAP is not set
+# CONFIG_CRYPTO_LIB_CHACHA is not set
+# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_LZ4 is not set
+# CONFIG_CRYPTO_LZ4HC is not set
+CONFIG_CRYPTO_LZO=y
+# CONFIG_CRYPTO_MANAGER is not set
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_OFB is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_POLY1305 is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_RSA is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEQIV is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA3 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_SM2 is not set
+# CONFIG_CRYPTO_SM3 is not set
+# CONFIG_CRYPTO_SM4 is not set
+# CONFIG_CRYPTO_STREEBOG is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_USER is not set
+# CONFIG_CRYPTO_USER_API_AEAD is not set
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_RNG is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+# CONFIG_CRYPTO_VMAC is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_XXHASH is not set
+# CONFIG_CRYPTO_ZSTD is not set
+CONFIG_LIB_MEMNEQ=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MTD_NAND_BBT_USING_FLASH=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_SGL_ALLOC=y
+# CONFIG_UBIFS_ATIME_SUPPORT is not set
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+# CONFIG_UBIFS_FS_AUTHENTICATION is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_SECURITY=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_ZSTD is not set

From 1255f11b25c3d9074abae3bd938b4bca8d28dce9 Mon Sep 17 00:00:00 2001
From: Sugar Zhang <sugar.zhang@rock-chips.com>
Date: Thu, 1 Jun 2023 19:03:58 +0800
Subject: [PATCH 33/60] clk: rockchip: clk-out: Add CLK_IGNORE_UNUSED flag

It's used for compatible for old style mclk reference
which do not use the "mclkout_x".

The clk framework will disable all unused clk after
system boot done. in this situation, it is failed to
output mclk with old style DT, because "mclkout_x"
was disabled by framework.

We add CLK_IGNORE_UNUSED flag to clk-out to allow old
style usage still work well.

Suggest to drop this flag for totally new SDK or SoCs
in the future. at the moment, we still need this flag.

Fixes: b3cfac5e37cd ("clk: rockchip: Add support for clk input / output switch")

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I9d0a6b04637d055bc8beb0a03a630804108d4b28
---
 drivers/clk/rockchip/clk-out.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-out.c b/drivers/clk/rockchip/clk-out.c
index 22dcd98fbbef..689832ed00d6 100644
--- a/drivers/clk/rockchip/clk-out.c
+++ b/drivers/clk/rockchip/clk-out.c
@@ -50,7 +50,7 @@ static int rockchip_clk_out_probe(struct platform_device *pdev)
 
 	pm_runtime_enable(dev);
 
-	hw = clk_hw_register_gate(dev, clk_name, parent_name, CLK_SET_RATE_PARENT,
+	hw = clk_hw_register_gate(dev, clk_name, parent_name, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
 				  reg, shift, clk_gate_flags, &clk_out_lock);
 	if (IS_ERR(hw)) {
 		ret = -EINVAL;

From e2a24104ee979cfcc6943ae9160cb0b13b677a6d Mon Sep 17 00:00:00 2001
From: Algea Cao <algea.cao@rock-chips.com>
Date: Tue, 16 May 2023 17:26:01 +0800
Subject: [PATCH 34/60] drm/edid: add HF-EEODB support to EDID read and
 allocation

HDMI 2.1 section 10.3.6 defines an HDMI Forum EDID Extension Override
Data Block, which may contain a different extension count than the base
block claims. Add support for reading more EDID data if available.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Id2c7bd846330ae9ec9547db32e151bbf387e5734
---
 drivers/gpu/drm/drm_edid.c | 256 ++++++++++++++++++++++++++++++++-----
 1 file changed, 226 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 258b01e2f1b7..4a57b259e6c1 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1915,6 +1915,76 @@ int drm_add_override_edid_modes(struct drm_connector *connector)
 }
 EXPORT_SYMBOL(drm_add_override_edid_modes);
 
+#ifdef CONFIG_NO_GKI
+/*
+ * References:
+ * - CTA-861-H section 7.3.3 CTA Extension Version 3
+ */
+static int cea_db_collection_size(const u8 *cta)
+{
+	u8 d = cta[2];
+
+	if (d < 4 || d > 127)
+		return 0;
+
+	return d - 4;
+}
+
+#define CTA_EXT_DB_HF_EEODB		0x78
+#define CTA_DB_EXTENDED_TAG		7
+
+static int cea_db_tag(const u8 *db);
+static int cea_db_payload_len(const u8 *db);
+static int cea_db_extended_tag(const u8 *db);
+
+static bool cea_db_is_extended_tag(const void *db, int tag)
+{
+	return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
+		cea_db_payload_len(db) >= 1 &&
+		cea_db_extended_tag(db) == tag;
+}
+
+static bool cea_db_is_hdmi_forum_eeodb(const void *db)
+{
+	return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
+		cea_db_payload_len(db) >= 2;
+}
+
+static int edid_hfeeodb_extension_block_count(const struct edid *edid)
+{
+	const u8 *cta;
+
+	/* No extensions according to base block, no HF-EEODB. */
+	if (!edid->extensions)
+		return 0;
+
+	/* HF-EEODB is always in the first EDID extension block only */
+	cta = (u8 *)edid + EDID_LENGTH * 1;
+	if (cta[0] != CEA_EXT || cta[1] < 3)
+		return 0;
+
+	/* Need to have the data block collection, and at least 3 bytes. */
+	if (cea_db_collection_size(cta) < 3)
+		return 0;
+
+	/*
+	 * Sinks that include the HF-EEODB in their E-EDID shall include one and
+	 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
+	 * through 6 of Block 1 of the E-EDID.
+	 */
+	if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
+		return 0;
+
+	return cta[4 + 2];
+}
+
+static int edid_hfeeodb_block_count(const struct edid *edid)
+{
+	int eeodb = edid_hfeeodb_extension_block_count(edid);
+
+	return eeodb ? eeodb + 1 : 0;
+}
+
 /**
  * drm_do_get_edid - get EDID data using a custom EDID block read function
  * @connector: connector we're probing
@@ -1935,6 +2005,120 @@ EXPORT_SYMBOL(drm_add_override_edid_modes);
  *
  * Return: Pointer to valid EDID or NULL if we couldn't find any.
  */
+struct edid *drm_do_get_edid(struct drm_connector *connector,
+	int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
+			      size_t len),
+	void *data)
+{
+	int i, j = 0, valid_extensions = 0, num_blocks, invalid_blocks = 0;
+	u8 *edid, *new;
+	struct edid *override;
+
+	override = drm_get_override_edid(connector);
+	if (override)
+		return override;
+
+	edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
+	if (!edid)
+		return NULL;
+
+	/* base block fetch */
+	for (i = 0; i < 4; i++) {
+		if (get_edid_block(data, edid, 0, EDID_LENGTH))
+			goto out;
+		if (drm_edid_block_valid(edid, 0, false,
+					 &connector->edid_corrupt))
+			break;
+		if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
+			connector->null_edid_counter++;
+			goto out;
+		}
+	}
+	if (i == 4)
+		goto out;
+
+	/* if there's no extensions, we're done */
+	valid_extensions = edid[0x7e];
+	if (valid_extensions == 0)
+		return (struct edid *)edid;
+
+	new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
+	if (!new)
+		goto out;
+	edid = new;
+
+	num_blocks = edid[0x7e] + 1;
+
+	for (j = 1; j < num_blocks; j++) {
+		u8 *block = edid + j * EDID_LENGTH;
+
+		for (i = 0; i < 4; i++) {
+			if (get_edid_block(data, block, j, EDID_LENGTH))
+				goto out;
+			if (drm_edid_block_valid(block, j, false, NULL))
+				break;
+		}
+
+		if (i == 4)
+			invalid_blocks++;
+
+		if (j == 1) {
+			/*
+			 * If the first EDID extension is a CTA extension, and
+			 * the first Data Block is HF-EEODB, override the
+			 * extension block count.
+			 *
+			 * Note: HF-EEODB could specify a smaller extension
+			 * count too, but we can't risk allocating a smaller
+			 * amount.
+			 */
+			int eeodb = edid_hfeeodb_block_count((const struct edid *)edid);
+
+			if (eeodb > num_blocks) {
+				num_blocks = eeodb;
+				new = krealloc(edid, num_blocks * EDID_LENGTH, GFP_KERNEL);
+				if (!new)
+					goto out;
+				edid = new;
+			}
+		}
+	}
+
+	if (invalid_blocks) {
+		u8 *base;
+
+		connector_bad_edid(connector, edid, edid[0x7e] + 1);
+
+		new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
+				    GFP_KERNEL);
+		if (!new)
+			goto out;
+
+		base = new;
+		for (i = 0; i <= edid[0x7e]; i++) {
+			u8 *block = edid + i * EDID_LENGTH;
+
+			if (!drm_edid_block_valid(block, i, false, NULL))
+				continue;
+
+			memcpy(base, block, EDID_LENGTH);
+			base += EDID_LENGTH;
+		}
+
+		new[EDID_LENGTH - 1] += new[0x7e] - valid_extensions;
+		new[0x7e] = valid_extensions;
+
+		kfree(edid);
+		edid = new;
+	}
+
+	return (struct edid *)edid;
+
+out:
+	kfree(edid);
+	return NULL;
+}
+#else
 struct edid *drm_do_get_edid(struct drm_connector *connector,
 	int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
 			      size_t len),
@@ -2026,6 +2210,7 @@ out:
 	kfree(edid);
 	return NULL;
 }
+#endif
 EXPORT_SYMBOL_GPL(drm_do_get_edid);
 
 /**
@@ -3245,6 +3430,39 @@ add_detailed_modes(struct drm_connector *connector, struct edid *edid,
 /*
  * Search EDID for CEA extension block.
  */
+#ifdef CONFIG_NO_GKI
+static u8 *drm_find_edid_extension(const struct edid *edid,
+				   int ext_id, int *ext_index)
+{
+	u8 *edid_ext = NULL;
+	int i;
+	int len;
+
+	/* No EDID or EDID extensions */
+	if (edid == NULL || edid->extensions == 0)
+		return NULL;
+
+	if (edid_hfeeodb_extension_block_count(edid))
+		len = edid_hfeeodb_extension_block_count(edid);
+	else
+		len = edid->extensions;
+
+	/* Find CEA extension */
+	for (i = *ext_index; i < len; i++) {
+		edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
+
+		if (edid_ext[0] == ext_id)
+			break;
+	}
+
+	if (i >= len)
+		return NULL;
+
+	*ext_index = i + 1;
+
+	return edid_ext;
+}
+#else
 static u8 *drm_find_edid_extension(const struct edid *edid,
 				   int ext_id, int *ext_index)
 {
@@ -3269,7 +3487,7 @@ static u8 *drm_find_edid_extension(const struct edid *edid,
 
 	return edid_ext;
 }
-
+#endif
 
 static u8 *drm_find_displayid_extension(const struct edid *edid,
 					int *length, int *idx,
@@ -4266,32 +4484,6 @@ static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
 }
 
 #ifdef CONFIG_NO_GKI
-static int drm_find_all_edid_extension(const struct edid *edid,
-				       int ext_id, int *ext_list)
-{
-	u8 *edid_ext = NULL;
-	int i, count = 0;
-
-	/* No EDID or EDID extensions */
-	if (edid == NULL || edid->extensions == 0)
-		return -EINVAL;
-
-	/* too many EDID extensions */
-	if (edid->extensions > 32)
-		return -EINVAL;
-
-	/* Find CEA extension */
-	for (i = 0; i < edid->extensions; i++) {
-		edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
-		if (edid_ext[0] == ext_id) {
-			*ext_list = i;
-			ext_list++;
-			count++;
-		}
-	}
-
-	return count;
-}
 
 static int
 add_cea_modes(struct drm_connector *connector, struct edid *edid)
@@ -4301,11 +4493,15 @@ add_cea_modes(struct drm_connector *connector, struct edid *edid)
 	u8 dbl, hdmi_len, video_len = 0;
 	int i, count = 0, modes = 0;
 	int ext_index = 0;
-	int ext_list[32];
 
-	count = drm_find_all_edid_extension(edid, CEA_EXT, ext_list);
+	if (edid_hfeeodb_extension_block_count(edid))
+		count = edid_hfeeodb_extension_block_count(edid);
+	else
+		count = edid->extensions;
+
 	for (i = 0; i < count; i++) {
-		ext_index = ext_list[i];
+		ext_index = i;
+
 		cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index);
 		if (cea && cea_revision(cea) >= 3) {
 			int i, start, end;

From c7e2a3387eb9ef11a054957422c1684b0fc1cbce Mon Sep 17 00:00:00 2001
From: Sandy Huang <hjc@rock-chips.com>
Date: Tue, 30 May 2023 09:59:16 +0800
Subject: [PATCH 35/60] drm/rockchip: vop2: No need for a full modested when
 the only writeback connector changed

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I2c1f9e20777de3cb581b4c6678ff4f268cd97522
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 23 ++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
index e41b0f7cf16a..bef640a52971 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
@@ -3142,6 +3142,18 @@ vop2_wb_connector_mode_valid(struct drm_connector *connector,
 	return MODE_OK;
 }
 
+static inline bool
+vop2_wb_connector_changed_only(struct drm_crtc_state *cstate, struct drm_connector *conn)
+{
+	struct drm_crtc_state *old_state;
+	u32 changed_connectors;
+
+	old_state = drm_atomic_get_old_crtc_state(cstate->state, cstate->crtc);
+	changed_connectors = cstate->connector_mask ^ old_state->connector_mask;
+
+	return BIT(drm_connector_index(conn)) == changed_connectors;
+}
+
 static int vop2_wb_encoder_atomic_check(struct drm_encoder *encoder,
 			       struct drm_crtc_state *cstate,
 			       struct drm_connector_state *conn_state)
@@ -3153,8 +3165,15 @@ static int vop2_wb_encoder_atomic_check(struct drm_encoder *encoder,
 	struct drm_gem_object *obj, *uv_obj;
 	struct rockchip_gem_object *rk_obj, *rk_uv_obj;
 
-
-
+	/*
+	 * No need for a full modested when the only connector changed is the
+	 * writeback connector.
+	 */
+	if (cstate->connectors_changed &&
+	    vop2_wb_connector_changed_only(cstate, conn_state->connector)) {
+		cstate->connectors_changed = false;
+		DRM_DEBUG("VP%d force change connectors_changed to false when only wb changed\n", vp->id);
+	}
 	if (!conn_state->writeback_job || !conn_state->writeback_job->fb)
 		return 0;
 

From 82a56746d9becce4b488265539a8338f027f7ff8 Mon Sep 17 00:00:00 2001
From: Sandy Huang <hjc@rock-chips.com>
Date: Wed, 31 May 2023 18:58:01 +0800
Subject: [PATCH 36/60] Revert "drm: Not mark crtc state as connectors_changed
 when a writeback connector attatch to a crtc"

This reverts commit ae488c03abd7cf9291947c3bb01e58ac4de78bed.

Use the following commit instead:

22fe2c3d386e ("drm/rockchip: vop2: No need for a full modested when the
only writeback connector changed")

Change-Id: If8669d28ebc6c06331beaca588e9842920894a4c
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
---
 drivers/gpu/drm/drm_atomic_helper.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
index 4108c7265d53..33768ddfaacb 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -296,14 +296,12 @@ update_connector_routing(struct drm_atomic_state *state,
 	if (old_connector_state->crtc != new_connector_state->crtc) {
 		if (old_connector_state->crtc) {
 			crtc_state = drm_atomic_get_new_crtc_state(state, old_connector_state->crtc);
-			if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
-				crtc_state->connectors_changed = true;
+			crtc_state->connectors_changed = true;
 		}
 
 		if (new_connector_state->crtc) {
 			crtc_state = drm_atomic_get_new_crtc_state(state, new_connector_state->crtc);
-			if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
-				crtc_state->connectors_changed = true;
+			crtc_state->connectors_changed = true;
 		}
 	}
 
@@ -388,8 +386,7 @@ update_connector_routing(struct drm_atomic_state *state,
 
 	set_best_encoder(state, new_connector_state, new_encoder);
 
-	if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
-		crtc_state->connectors_changed = true;
+	crtc_state->connectors_changed = true;
 
 	DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] using [ENCODER:%d:%s] on [CRTC:%d:%s]\n",
 			 connector->base.id,

From 972d711bd4d4c189e9b789535a1018e745b771e5 Mon Sep 17 00:00:00 2001
From: Tony Zheng <tony.zheng@rock-chips.com>
Date: Fri, 2 Jun 2023 16:02:05 +0800
Subject: [PATCH 37/60] arm64: dts: rockchip: rk3308b-amp: Increase the size of
 AMP reserved memory to 18MB

Signed-off-by: Tony Zheng <tony.zheng@rock-chips.com>
Change-Id: I81a54a11a4b33c3539c760ffc054115e15854dbf
---
 arch/arm64/boot/dts/rockchip/rk3308b-amp.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3308b-amp.dtsi b/arch/arm64/boot/dts/rockchip/rk3308b-amp.dtsi
index 79c743180e8e..72f3029c62c0 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308b-amp.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3308b-amp.dtsi
@@ -21,7 +21,7 @@
 
 		/* remote amp core address */
 		amp_reserved: amp@2e00000 {
-			reg = <0x0 0x2e00000 0x0 0x200000>;
+			reg = <0x0 0x2e00000 0x0 0x1200000>;
 			no-map;
 		};
 	};

From 3852e749f03addf8f496d65c550f3219b41c8ed9 Mon Sep 17 00:00:00 2001
From: Zefa Chen <zefa.chen@rock-chips.com>
Date: Mon, 5 Jun 2023 10:22:23 +0800
Subject: [PATCH 38/60] media: rockchip: vicap change compact mode by align of
 width

and it only control with unit and online mode

Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: Ibdf6b6969dacdb0f418066594b9c0520d0d9a7fb
---
 .../media/platform/rockchip/cif/subdev-itf.c  | 32 +++++++++++--------
 1 file changed, 19 insertions(+), 13 deletions(-)

diff --git a/drivers/media/platform/rockchip/cif/subdev-itf.c b/drivers/media/platform/rockchip/cif/subdev-itf.c
index b8b79fc0b7a6..7f850cc75e47 100644
--- a/drivers/media/platform/rockchip/cif/subdev-itf.c
+++ b/drivers/media/platform/rockchip/cif/subdev-itf.c
@@ -172,23 +172,29 @@ static int sditf_get_set_fmt(struct v4l2_subdev *sd,
 		    priv->hdr_cfg.hdr_mode == HDR_COMPR) {
 			rkcif_set_fmt(&cif_dev->stream[0], &pixm, false);
 		} else if (priv->hdr_cfg.hdr_mode == HDR_X2) {
-			if (is_uncompact) {
-				cif_dev->stream[0].is_compact = false;
-				cif_dev->stream[0].is_high_align = true;
-			} else {
-				cif_dev->stream[0].is_compact = true;
+			if (priv->mode.rdbk_mode == RKISP_VICAP_ONLINE &&
+			    priv->toisp_inf.link_mode == TOISP_UNITE) {
+				if (is_uncompact) {
+					cif_dev->stream[0].is_compact = false;
+					cif_dev->stream[0].is_high_align = true;
+				} else {
+					cif_dev->stream[0].is_compact = true;
+				}
 			}
 			rkcif_set_fmt(&cif_dev->stream[0], &pixm, false);
 			rkcif_set_fmt(&cif_dev->stream[1], &pixm, false);
 		} else if (priv->hdr_cfg.hdr_mode == HDR_X3) {
-			if (is_uncompact) {
-				cif_dev->stream[0].is_compact = false;
-				cif_dev->stream[0].is_high_align = true;
-				cif_dev->stream[1].is_compact = false;
-				cif_dev->stream[1].is_high_align = true;
-			} else {
-				cif_dev->stream[0].is_compact = true;
-				cif_dev->stream[1].is_compact = true;
+			if (priv->mode.rdbk_mode == RKISP_VICAP_ONLINE &&
+			    priv->toisp_inf.link_mode == TOISP_UNITE) {
+				if (is_uncompact) {
+					cif_dev->stream[0].is_compact = false;
+					cif_dev->stream[0].is_high_align = true;
+					cif_dev->stream[1].is_compact = false;
+					cif_dev->stream[1].is_high_align = true;
+				} else {
+					cif_dev->stream[0].is_compact = true;
+					cif_dev->stream[1].is_compact = true;
+				}
 			}
 			rkcif_set_fmt(&cif_dev->stream[0], &pixm, false);
 			rkcif_set_fmt(&cif_dev->stream[1], &pixm, false);

From c4fc0a51539a96a25104eb586142c573ce16bf33 Mon Sep 17 00:00:00 2001
From: Qiqi Zhang <eddy.zhang@rock-chips.com>
Date: Mon, 9 Jan 2023 18:04:50 +0800
Subject: [PATCH 39/60] input: rockchip_pwm_remotectl: workaround rk3528 IR
 code reading issue

Change-Id: Ic1cf95c7347324fd5b87e97b8084b7fb2a3d6708
Signed-off-by: Qiqi Zhang <eddy.zhang@rock-chips.com>
---
 drivers/input/remotectl/rockchip_pwm_remotectl.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/input/remotectl/rockchip_pwm_remotectl.c b/drivers/input/remotectl/rockchip_pwm_remotectl.c
index f24ba9edf08b..fa3d7650d8ff 100644
--- a/drivers/input/remotectl/rockchip_pwm_remotectl.c
+++ b/drivers/input/remotectl/rockchip_pwm_remotectl.c
@@ -335,9 +335,12 @@ static irqreturn_t rockchip_pwm_irq(int irq, void *dev_id)
 		return IRQ_NONE;
 	if ((val & PWM_CH_POL(id)) == 0) {
 		temp_hpr = readl_relaxed(ddata->base + PWM_REG_HPR);
-		DBG("hpr=%d\n", temp_hpr);
+		writel_relaxed(0, ddata->base + PWM_REG_HPR);
 		temp_lpr = readl_relaxed(ddata->base + PWM_REG_LPR);
+		writel_relaxed(0, ddata->base + PWM_REG_LPR);
+		DBG("hpr=%d\n", temp_hpr);
 		DBG("lpr=%d\n", temp_lpr);
+
 		temp_period = ddata->pwm_freq_nstime * temp_lpr / 1000;
 		if (temp_period > RK_PWM_TIME_BIT0_MIN) {
 			ddata->period = ddata->temp_period

From 4fa69211093900430b7d096ea19fd7000b4dc2a4 Mon Sep 17 00:00:00 2001
From: Sisyphean Zhou <sisyphean.zhou@rock-chips.com>
Date: Mon, 5 Jun 2023 09:52:47 +0800
Subject: [PATCH 40/60] crypto: rockchip: v2: Fix pointer judgment errors

Change-Id: If13ef9030e42dc88feba351575dd0caa4ea4b66a
Signed-off-by: Sisyphean Zhou <sisyphean.zhou@rock-chips.com>
---
 drivers/crypto/rockchip/rk_crypto_v2_akcipher.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/crypto/rockchip/rk_crypto_v2_akcipher.c b/drivers/crypto/rockchip/rk_crypto_v2_akcipher.c
index 6ee2a5d40a00..1311ea3d4eac 100644
--- a/drivers/crypto/rockchip/rk_crypto_v2_akcipher.c
+++ b/drivers/crypto/rockchip/rk_crypto_v2_akcipher.c
@@ -160,7 +160,7 @@ static int rk_rsa_calc(struct akcipher_request *req, bool encypt)
 		goto exit;
 
 	out = rk_bn_alloc(key_byte_size);
-	if (!in)
+	if (!out)
 		goto exit;
 
 	tmp_buf = kzalloc(key_byte_size, GFP_KERNEL);

From 60c9e5240f35047a0f52b51cf551e47b9d0ceb71 Mon Sep 17 00:00:00 2001
From: Shawn Lin <shawn.lin@rock-chips.com>
Date: Thu, 1 Jun 2023 10:30:48 +0800
Subject: [PATCH 41/60] mmc: dw_mmc: Add normal and idle pinctrl control

normal pinctrl is used for sd working mode. idle pinctrl is
used when the card is added or removed, so pull down the
IO to avoid power leak which makes the card unable to work.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I8780b9de735b86918b4d5ba857711e56de740ecf
---
 drivers/mmc/host/dw_mmc.c | 25 +++++++++++++++++++++++++
 drivers/mmc/host/dw_mmc.h |  3 +++
 2 files changed, 28 insertions(+)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index a2114fb47edd..fde49464a637 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1507,6 +1507,9 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 
 	switch (ios->power_mode) {
 	case MMC_POWER_UP:
+		if (!IS_ERR_OR_NULL(slot->host->pinctrl))
+			pinctrl_select_state(slot->host->pinctrl, slot->host->idle_state);
+
 		if (!IS_ERR(mmc->supply.vmmc)) {
 			ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
 					ios->vdd);
@@ -1523,6 +1526,9 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 		mci_writel(slot->host, PWREN, regs);
 		break;
 	case MMC_POWER_ON:
+		if (!IS_ERR_OR_NULL(slot->host->pinctrl))
+			pinctrl_select_state(slot->host->pinctrl, slot->host->normal_state);
+
 		if (!slot->host->vqmmc_enabled) {
 			if (!IS_ERR(mmc->supply.vqmmc)) {
 				ret = regulator_enable(mmc->supply.vqmmc);
@@ -1547,6 +1553,9 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 
 		break;
 	case MMC_POWER_OFF:
+		if (!IS_ERR_OR_NULL(slot->host->pinctrl))
+			pinctrl_select_state(slot->host->pinctrl, slot->host->idle_state);
+
 		/* Turn clock off before power goes down */
 		dw_mci_setup_bus(slot, false);
 
@@ -3262,6 +3271,22 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
 			return ERR_PTR(ret);
 	}
 
+	host->pinctrl = devm_pinctrl_get(host->dev);
+	if (!IS_ERR(host->pinctrl)) {
+		host->normal_state = pinctrl_lookup_state(host->pinctrl, "normal");
+		if (IS_ERR(host->normal_state))
+			dev_warn(dev, "No normal pinctrl state\n");
+
+		host->idle_state = pinctrl_lookup_state(host->pinctrl, "idle");
+		if (IS_ERR(host->idle_state))
+			dev_warn(dev, "No idle pinctrl state\n");
+
+		if (!IS_ERR(host->normal_state) && !IS_ERR(host->idle_state))
+			pinctrl_select_state(host->pinctrl, host->idle_state);
+		else
+			host->pinctrl = NULL;
+	}
+
 	return pdata;
 }
 
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 0160a1769f62..6ffa2fd6db38 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -233,6 +233,9 @@ struct dw_mci {
 	bool			need_xfer_timer;
 	struct timer_list       xfer_timer;
 	bool			is_rv1106_sd;
+	struct pinctrl		*pinctrl;
+	struct pinctrl_state	*normal_state;
+	struct pinctrl_state	*idle_state;
 };
 
 /* DMA ops for Internal/External DMAC interface */

From 4bbb16bf8790f7aa5726edc3f6a9a6fde556332a Mon Sep 17 00:00:00 2001
From: William Wu <william.wu@rock-chips.com>
Date: Mon, 5 Jun 2023 09:50:28 +0800
Subject: [PATCH 42/60] phy: rockchip: naneng-combphy: Fix Rx squelch for
 RK3568 U3

This patch adjust the RK3568 U3 Rx squelch input filler
bandwidth to 3'b110 which is used for rx_lfps, reduce the
bandwidth to avoid filtering valid superspeed data.

With this patch, it can fix the issue that Kingston U3 Disk
(idVendor=0951, idProduct=1666, bcdDevice= 1.10) read error
on RK3568 platforms.

Change-Id: I27410c5702862df2d8829a2ca3c2c1d9f57885be
Signed-off-by: William Wu <william.wu@rock-chips.com>
---
 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index 42ef316599fa..5ba4864c9899 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -827,6 +827,9 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
 		/* Set PLL KVCO to min and set PLL charge pump current to max */
 		writel(0xf0, priv->mmio + (0xa << 2));
 
+		/* Set Rx squelch input filler bandwidth */
+		writel(0x0e, priv->mmio + (0x14 << 2));
+
 		param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
 		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
 		param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);

From ae3a28752ed345036b15f7ca5a927bb33d12ad3b Mon Sep 17 00:00:00 2001
From: William Wu <william.wu@rock-chips.com>
Date: Mon, 5 Jun 2023 09:59:13 +0800
Subject: [PATCH 43/60] phy: rockchip: naneng-combphy: Fix Rx squelch for
 RK3562 U3

This patch adjust the RK3562 U3 Rx squelch input filler
bandwidth to 3'b110 which is used for rx_lfps, reduce the
bandwidth to avoid filtering valid superspeed data.

With this patch, it can fix the issue that Kingston U3 Disk
(idVendor=0951, idProduct=1666, bcdDevice= 1.10) read error
on RK3562 platforms.

Change-Id: Idb667d159f9dba6b1de0a9ec04af9dae2d065927
Signed-off-by: William Wu <william.wu@rock-chips.com>
---
 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index 5ba4864c9899..ca47a6264a7f 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -635,6 +635,9 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
 		/* Set PLL KVCO to min and set PLL charge pump current to max */
 		writel(0xf0, priv->mmio + (0xa << 2));
 
+		/* Set Rx squelch input filler bandwidth */
+		writel(0x0e, priv->mmio + (0x14 << 2));
+
 		param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
 		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
 		param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);

From 27312ce9d832612ec16eed649c365231082a8cbb Mon Sep 17 00:00:00 2001
From: William Wu <william.wu@rock-chips.com>
Date: Mon, 5 Jun 2023 10:10:01 +0800
Subject: [PATCH 44/60] phy: rockchip: naneng-combphy: Fix Rx squelch for
 RK3528 U3

This patch adjust the RK3528 U3 Rx squelch input filler
bandwidth to 3'b110 which is used for rx_lfps, reduce the
bandwidth to avoid filtering valid superspeed data.

With this patch, it can fix the issue that Kingston U3 Disk
(idVendor=0951, idProduct=1666, bcdDevice= 1.10) read error
on RK3528 platforms.

Change-Id: Ifa4eac24bbdebe020db356ba45dae146f4df22f1
Signed-off-by: William Wu <william.wu@rock-chips.com>
---
 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index ca47a6264a7f..36b842060406 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -483,6 +483,12 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
 		val |= 0x01 << 17;
 		writel(val, priv->mmio + 0x200);
 
+		/* Set Rx squelch input filler bandwidth */
+		val = readl(priv->mmio + 0x20c);
+		val &= ~GENMASK(2, 0);
+		val |= 0x06;
+		writel(val, priv->mmio + 0x20c);
+
 		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
 		param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
 		param_write(priv->phy_grf, &cfg->usb_mode_set, true);

From ff60528776913145e413e8bde7444be41229b55e Mon Sep 17 00:00:00 2001
From: Caesar Wang <wxt@rock-chips.com>
Date: Tue, 6 Jun 2023 10:49:39 +0800
Subject: [PATCH 45/60] arm64: dts: rockchip: add camera sensor configuration
 for rk3588s-evb1-lp4x-v10-linux.dts

Add lt7911d type-c/DP to MIPI CSI-2 bridge dts configuration as an example

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: I3ccd33f0f8ecf991c3c0ea4e6d6574009dc0e04c
---
 arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x-v10-linux.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x-v10-linux.dts
index 121255ddfdbc..4d8157bcc7de 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x-v10-linux.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x-v10-linux.dts
@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include "rk3588s-evb1-lp4x.dtsi"
+#include "rk3588s-evb1-lp4x-v10-camera.dtsi"
 #include "rk3588-linux.dtsi"
 
 / {

From 6e858e1a974d771e74b5ddb12692adaeef9d9a80 Mon Sep 17 00:00:00 2001
From: Caesar Wang <wxt@rock-chips.com>
Date: Tue, 6 Jun 2023 10:51:09 +0800
Subject: [PATCH 46/60] arm64: configs: update camera sensors for
 rockchip_linux_defconfig

1/ Enable CONFIG_VIDEO_LT6911UXE for rk3588 evb1 extboard
2/ Enable CONFIG_VIDEO_OV13855 for rk3588s-tablet
3/ Enable CONFIG_VIDEO_OV50C40 rk3588s tablet & evb1.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: I78e7caeb11b7f1db4a7ec74aaba681e895bcc843
---
 arch/arm64/configs/rockchip_linux_defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/configs/rockchip_linux_defconfig b/arch/arm64/configs/rockchip_linux_defconfig
index 37e69e7e8ae4..a9639edaca7e 100644
--- a/arch/arm64/configs/rockchip_linux_defconfig
+++ b/arch/arm64/configs/rockchip_linux_defconfig
@@ -310,6 +310,7 @@ CONFIG_VIDEO_ROCKCHIP_HDMIRX=y
 CONFIG_V4L_MEM2MEM_DRIVERS=y
 CONFIG_VIDEO_ROCKCHIP_RGA=y
 CONFIG_VIDEO_LT6911UXC=y
+CONFIG_VIDEO_LT6911UXE=y
 CONFIG_VIDEO_LT7911D=y
 CONFIG_VIDEO_RK628_CSI=y
 CONFIG_VIDEO_RK628_BT1120=y
@@ -320,9 +321,11 @@ CONFIG_VIDEO_IMX415=y
 CONFIG_VIDEO_IMX464=y
 CONFIG_VIDEO_OS04A10=y
 CONFIG_VIDEO_OV4689=y
+CONFIG_VIDEO_OV50C40=y
 CONFIG_VIDEO_OV5695=y
 CONFIG_VIDEO_OV7251=y
 CONFIG_VIDEO_OV13850=y
+CONFIG_VIDEO_OV13855=y
 # CONFIG_VGA_ARB is not set
 CONFIG_DRM=y
 CONFIG_DRM_IGNORE_IOTCL_PERMIT=y

From db77afeb1d38d116d8c9cf9ab69dc48b6b3e2f54 Mon Sep 17 00:00:00 2001
From: Jianwei Fan <jianwei.fan@rock-chips.com>
Date: Mon, 20 Mar 2023 12:17:21 +0000
Subject: [PATCH 47/60] media: i2c: lt6911uxe: add interlaced support

Change-Id: I09156961998940fa78c87e591c3d89982d91868d
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
---
 drivers/media/i2c/lt6911uxe.c | 78 +++++++++++++++++++++++++++++------
 1 file changed, 66 insertions(+), 12 deletions(-)

diff --git a/drivers/media/i2c/lt6911uxe.c b/drivers/media/i2c/lt6911uxe.c
index 221d96ba09fd..a14ba83ab8cb 100644
--- a/drivers/media/i2c/lt6911uxe.c
+++ b/drivers/media/i2c/lt6911uxe.c
@@ -217,6 +217,7 @@ struct lt6911uxe_mode {
 	u32 vts_def;
 	u32 exp_def;
 	u32 mipi_freq_idx;
+	u32 interlace;
 };
 
 static struct rkmodule_csi_dphy_param rk3588_dcphy_param = {
@@ -241,6 +242,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 5500,
 		.vts_def = 2250,
 		.mipi_freq_idx = 0,
+		.interlace = 0,
 	}, {
 		.width = 4096,
 		.height = 2160,
@@ -251,6 +253,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 4400,
 		.vts_def = 2250,
 		.mipi_freq_idx = 0,
+		.interlace = 0,
 	}, {
 		.width = 4096,
 		.height = 2160,
@@ -261,6 +264,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 4400,
 		.vts_def = 2250,
 		.mipi_freq_idx = 1,
+		.interlace = 0,
 	}, {
 		.width = 3840,
 		.height = 2160,
@@ -271,6 +275,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 4400,
 		.vts_def = 2250,
 		.mipi_freq_idx = 0,
+		.interlace = 0,
 	}, {
 		.width = 3840,
 		.height = 2160,
@@ -281,6 +286,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 4400,
 		.vts_def = 2250,
 		.mipi_freq_idx = 1,
+		.interlace = 0,
 	}, {
 		.width = 1920,
 		.height = 1080,
@@ -291,6 +297,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 2200,
 		.vts_def = 1125,
 		.mipi_freq_idx = 3,
+		.interlace = 0,
 	}, {
 		.width = 1920,
 		.height = 1200,
@@ -301,6 +308,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 2592,
 		.vts_def = 1245,
 		.mipi_freq_idx = 3,
+		.interlace = 0,
 	}, {
 		.width = 1920,
 		.height = 1080,
@@ -311,6 +319,18 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 2200,
 		.vts_def = 1125,
 		.mipi_freq_idx = 4,
+		.interlace = 0,
+	}, {
+		.width = 1920,
+		.height = 1080,
+		.max_fps = {
+			.numerator = 10000,
+			.denominator = 600000,
+		},
+		.hts_def = 2200,
+		.vts_def = 1125,
+		.mipi_freq_idx = 4,
+		.interlace = 1,
 	}, {
 		.width = 1680,
 		.height = 1050,
@@ -321,6 +341,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 2240,
 		.vts_def = 1089,
 		.mipi_freq_idx = 3,
+		.interlace = 0,
 	}, {
 		.width = 1600,
 		.height = 1200,
@@ -331,6 +352,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 2160,
 		.vts_def = 1250,
 		.mipi_freq_idx = 3,
+		.interlace = 0,
 	}, {
 		.width = 1600,
 		.height = 900,
@@ -341,6 +363,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 1800,
 		.vts_def = 1000,
 		.mipi_freq_idx = 3,
+		.interlace = 0,
 	}, {
 		.width = 1440,
 		.height = 900,
@@ -351,6 +374,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 1904,
 		.vts_def = 934,
 		.mipi_freq_idx = 3,
+		.interlace = 0,
 	}, {
 		.width = 1440,
 		.height = 240,
@@ -361,6 +385,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 1716,
 		.vts_def = 262,
 		.mipi_freq_idx = 5,
+		.interlace = 0,
 	}, {
 		.width = 1360,
 		.height = 768,
@@ -371,6 +396,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 1792,
 		.vts_def = 795,
 		.mipi_freq_idx = 4,
+		.interlace = 0,
 	}, {
 		.width = 1280,
 		.height = 1024,
@@ -381,6 +407,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 1688,
 		.vts_def = 1066,
 		.mipi_freq_idx = 3,
+		.interlace = 0,
 	}, {
 		.width = 1280,
 		.height = 960,
@@ -391,6 +418,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 1712,
 		.vts_def = 994,
 		.mipi_freq_idx = 3,
+		.interlace = 0,
 	}, {
 		.width = 1280,
 		.height = 800,
@@ -401,6 +429,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 1680,
 		.vts_def = 828,
 		.mipi_freq_idx = 4,
+		.interlace = 0,
 	}, {
 		.width = 1280,
 		.height = 768,
@@ -411,6 +440,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 1664,
 		.vts_def = 798,
 		.mipi_freq_idx = 4,
+		.interlace = 0,
 	}, {
 		.width = 1280,
 		.height = 720,
@@ -421,6 +451,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 1650,
 		.vts_def = 750,
 		.mipi_freq_idx = 4,
+		.interlace = 0,
 	}, {
 		.width = 1152,
 		.height = 864,
@@ -431,6 +462,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 1600,
 		.vts_def = 900,
 		.mipi_freq_idx = 4,
+		.interlace = 0,
 	}, {
 		.width = 1024,
 		.height = 768,
@@ -441,6 +473,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 1344,
 		.vts_def = 806,
 		.mipi_freq_idx = 4,
+		.interlace = 0,
 	}, {
 		.width = 800,
 		.height = 600,
@@ -451,6 +484,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 1056,
 		.vts_def = 628,
 		.mipi_freq_idx = 5,
+		.interlace = 0,
 	}, {
 		.width = 720,
 		.height = 576,
@@ -461,6 +495,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 864,
 		.vts_def = 625,
 		.mipi_freq_idx = 5,
+		.interlace = 0,
 	}, {
 		.width = 720,
 		.height = 480,
@@ -471,6 +506,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 858,
 		.vts_def = 525,
 		.mipi_freq_idx = 5,
+		.interlace = 0,
 	}, {
 		.width = 720,
 		.height = 400,
@@ -481,6 +517,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 936,
 		.vts_def = 446,
 		.mipi_freq_idx = 5,
+		.interlace = 0,
 	}, {
 		.width = 720,
 		.height = 240,
@@ -489,6 +526,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 			.denominator = 600000,
 		},
 		.mipi_freq_idx = 5,
+		.interlace = 0,
 	}, {
 		.width = 640,
 		.height = 480,
@@ -499,6 +537,7 @@ static const struct lt6911uxe_mode supported_modes_dphy[] = {
 		.hts_def = 800,
 		.vts_def = 525,
 		.mipi_freq_idx = 5,
+		.interlace = 0,
 	},
 };
 
@@ -798,12 +837,6 @@ static int lt6911uxe_get_detected_timings(struct v4l2_subdev *sd,
 	vbp = vtotal - vact - vs - vfp;
 	lt6911uxe_i2c_disable(sd);
 
-	if (!lt6911uxe_rcv_supported_res(sd, hact, vact)) {
-		lt6911uxe->nosignal = true;
-		v4l2_err(sd, "%s: rcv err res, return no signal!\n", __func__);
-		return -EINVAL;
-	}
-
 	lt6911uxe->nosignal = false;
 	lt6911uxe->is_audio_present = true;
 	timings->type = V4L2_DV_BT_656_1120;
@@ -819,6 +852,22 @@ static int lt6911uxe_get_detected_timings(struct v4l2_subdev *sd,
 	bt->pixelclock = pixel_clock;
 	fps = pixel_clock / (htotal * vtotal);
 
+	/* for interlaced res 1080i 576i 480i*/
+	if ((hact == 1920 && vact == 540) || (hact == 1440 && vact == 288)
+			|| (hact == 1440 && vact == 240)) {
+		bt->interlaced = V4L2_DV_INTERLACED;
+		bt->height *= 2;
+		bt->il_vsync = bt->vsync + 1;
+	} else {
+		bt->interlaced = V4L2_DV_PROGRESSIVE;
+	}
+
+	if (!lt6911uxe_rcv_supported_res(sd, hact, bt->height)) {
+		lt6911uxe->nosignal = true;
+		v4l2_err(sd, "%s: rcv err res, return no signal!\n", __func__);
+		return -EINVAL;
+	}
+
 	v4l2_info(sd, "act:%dx%d, total:%dx%d, pixclk:%d, fps:%d\n",
 			hact, vact, htotal, vtotal, pixel_clock, fps);
 	v4l2_info(sd, "byte_clk:%u, mipi_clk:%u, mipi_data_rate:%u\n",
@@ -1132,9 +1181,10 @@ static int lt6911uxe_s_stream(struct v4l2_subdev *sd, int on)
 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
 	struct i2c_client *client = lt6911uxe->i2c_client;
 
-	dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
+	dev_info(&client->dev, "%s: on: %d, %dx%d%s%d\n", __func__, on,
 				lt6911uxe->cur_mode->width,
 				lt6911uxe->cur_mode->height,
+				lt6911uxe->cur_mode->interlace ? "I" : "P",
 		DIV_ROUND_CLOSEST(lt6911uxe->cur_mode->max_fps.denominator,
 				  lt6911uxe->cur_mode->max_fps.numerator));
 	enable_stream(sd, on);
@@ -1218,16 +1268,20 @@ lt6911uxe_find_best_fit(struct lt6911uxe *lt6911uxe)
 	unsigned int i;
 
 	for (i = 0; i < lt6911uxe->cfg_num; i++) {
-		dist = lt6911uxe_get_reso_dist(&lt6911uxe->support_modes[i], &lt6911uxe->timings);
-		if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
-			cur_best_fit_dist = dist;
-			cur_best_fit = i;
+		if (lt6911uxe->support_modes[i].interlace == lt6911uxe->timings.bt.interlaced) {
+			dist = lt6911uxe_get_reso_dist(&lt6911uxe->support_modes[i],
+							&lt6911uxe->timings);
+			if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
+				cur_best_fit_dist = dist;
+				cur_best_fit = i;
+			}
 		}
 	}
 	dev_info(&lt6911uxe->i2c_client->dev,
-		"find current mode: support_mode[%d], %dx%d@%dfps\n",
+		"find current mode: support_mode[%d], %dx%d%s%dfps\n",
 		cur_best_fit, lt6911uxe->support_modes[cur_best_fit].width,
 		lt6911uxe->support_modes[cur_best_fit].height,
+		lt6911uxe->support_modes[cur_best_fit].interlace ? "I" : "P",
 		DIV_ROUND_CLOSEST(lt6911uxe->support_modes[cur_best_fit].max_fps.denominator,
 		lt6911uxe->support_modes[cur_best_fit].max_fps.numerator));
 

From db473bd42390dae63b2717042ce5fc5bdaae68d1 Mon Sep 17 00:00:00 2001
From: Jianwei Fan <jianwei.fan@rock-chips.com>
Date: Mon, 5 Jun 2023 09:23:39 +0000
Subject: [PATCH 48/60] media: i2c: lt7911uxc: update driver to V0.0X01.0X07

1.fix driver probe sequence.
2.set default timing
3.fix dcphy params
4.fix hotplug event report

Change-Id: Ibd97f1498169798ff2a73e23330fdcb51b0a27ef
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
---
 drivers/media/i2c/lt7911uxc.c | 264 +++++++++++++++++++++++-----------
 1 file changed, 178 insertions(+), 86 deletions(-)

diff --git a/drivers/media/i2c/lt7911uxc.c b/drivers/media/i2c/lt7911uxc.c
index fe599dadab8e..a21235074f5f 100644
--- a/drivers/media/i2c/lt7911uxc.c
+++ b/drivers/media/i2c/lt7911uxc.c
@@ -13,6 +13,11 @@
  * V0.0X01.0X04 add 5K60 support for CPHY.
  * V0.0X01.0X05 add CSI BGR888 fmt.
  * V0.0X01.0X06 fix dcphy params and add more fmt.
+ * V0.0X01.0X07
+ *	1.fix driver probe sequence.
+ *	2.set default timing
+ *	3.fix dcphy params
+ *	4.fix hotplug event report
  *
  */
 
@@ -40,7 +45,7 @@
 #include <media/v4l2-event.h>
 #include <media/v4l2-fwnode.h>
 
-#define DRIVER_VERSION			KERNEL_VERSION(0, 0x01, 0x06)
+#define DRIVER_VERSION			KERNEL_VERSION(0, 0x01, 0x07)
 
 static int debug;
 module_param(debug, int, 0644);
@@ -180,11 +185,11 @@ struct lt7911uxc_mode {
 static struct rkmodule_csi_dphy_param rk3588_dcphy_param = {
 	.vendor = PHY_VENDOR_SAMSUNG,
 	.lp_vol_ref = 3,
-	.lp_hys_sw = {3, 3, 3, 0},
-	.lp_escclk_pol_sel = {1, 0, 0, 0},
-	.skew_data_cal_clk = {0, 0, 0, 3},
-	.clk_hs_term_sel = 2,
-	.data_hs_term_sel = {2, 2, 2, 2},
+	.lp_hys_sw = {3, 0, 3, 0},
+	.lp_escclk_pol_sel = {1, 1, 0, 0},
+	.skew_data_cal_clk = {0, 0, 0, 0},
+	.clk_hs_term_sel = 0,
+	.data_hs_term_sel = {0, 0, 0, 0},
 	.reserved = {0},
 };
 
@@ -573,7 +578,7 @@ static int lt7911uxc_get_detected_timings(struct v4l2_subdev *sd,
 	u32 pixel_clock, fps, halt_pix_clk;
 	u8 clk_h, clk_m, clk_l;
 	u8 val_h, val_l;
-	u32 byte_clk, mipi_clk, mipi_data_rate;
+	u64 byte_clk, mipi_clk, mipi_data_rate;
 
 	memset(timings, 0, sizeof(struct v4l2_dv_timings));
 
@@ -623,7 +628,7 @@ static int lt7911uxc_get_detected_timings(struct v4l2_subdev *sd,
 
 	v4l2_info(sd, "act:%dx%d, total:%dx%d, pixclk:%d, fps:%d\n",
 			hact, vact, htotal, vtotal, pixel_clock, fps);
-	v4l2_info(sd, "byte_clk:%d, mipi_clk:%d, mipi_data_rate:%d\n",
+	v4l2_info(sd, "byte_clk:%u, mipi_clk:%u, mipi_data_rate:%u\n",
 			byte_clk, mipi_clk, mipi_data_rate);
 	v4l2_info(sd, "inerlaced:%d\n", bt->interlaced);
 
@@ -640,6 +645,18 @@ static void lt7911uxc_delayed_work_hotplug(struct work_struct *work)
 	lt7911uxc_s_ctrl_detect_tx_5v(sd);
 }
 
+static void lt7911uxc_s_ctrl_detect_event(struct v4l2_subdev *sd)
+{
+	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
+	u8 val;
+
+	val = i2c_rd8(sd, 0xe084);
+	if (val == 0x01)
+		v4l2_ctrl_s_ctrl(lt7911uxc->detect_tx_5v_ctrl, 1);
+	else if (val == 0x00)
+		v4l2_ctrl_s_ctrl(lt7911uxc->detect_tx_5v_ctrl, 0);
+}
+
 static void lt7911uxc_delayed_work_res_change(struct work_struct *work)
 {
 	struct delayed_work *dwork = to_delayed_work(work);
@@ -647,6 +664,7 @@ static void lt7911uxc_delayed_work_res_change(struct work_struct *work)
 			struct lt7911uxc, delayed_work_res_change);
 	struct v4l2_subdev *sd = &lt7911uxc->sd;
 
+	lt7911uxc_s_ctrl_detect_event(sd);
 	lt7911uxc_format_change(sd);
 }
 
@@ -731,13 +749,55 @@ static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
 			__func__, enable ? "en" : "dis");
 }
 
+static int lt7911uxc_get_reso_dist(const struct lt7911uxc_mode *mode,
+				struct v4l2_dv_timings *timings)
+{
+	struct v4l2_bt_timings *bt = &timings->bt;
+	u32 cur_fps, dist_fps;
+
+	cur_fps = fps_calc(bt);
+	dist_fps = DIV_ROUND_CLOSEST(mode->max_fps.denominator, mode->max_fps.numerator);
+
+	return abs(mode->width - bt->width) +
+		abs(mode->height - bt->height) + abs(dist_fps - cur_fps);
+}
+
+static const struct lt7911uxc_mode *
+lt7911uxc_find_best_fit(struct lt7911uxc *lt7911uxc)
+{
+	int dist;
+	int cur_best_fit = 0;
+	int cur_best_fit_dist = -1;
+	unsigned int i;
+
+	for (i = 0; i < lt7911uxc->cfg_num; i++) {
+		dist = lt7911uxc_get_reso_dist(&lt7911uxc->support_modes[i], &lt7911uxc->timings);
+		if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
+			cur_best_fit_dist = dist;
+			cur_best_fit = i;
+		}
+	}
+	dev_dbg(&lt7911uxc->i2c_client->dev,
+		"find current mode: support_mode[%d], %dx%d@%dfps\n",
+		cur_best_fit, lt7911uxc->support_modes[cur_best_fit].width,
+		lt7911uxc->support_modes[cur_best_fit].height,
+		DIV_ROUND_CLOSEST(lt7911uxc->support_modes[cur_best_fit].max_fps.denominator,
+		lt7911uxc->support_modes[cur_best_fit].max_fps.numerator));
+
+	return &lt7911uxc->support_modes[cur_best_fit];
+}
+
 static void lt7911uxc_print_dv_timings(struct v4l2_subdev *sd, const char *prefix)
 {
 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
+	struct device *dev = &lt7911uxc->i2c_client->dev;
 	const struct v4l2_bt_timings *bt = &lt7911uxc->timings.bt;
+	const struct lt7911uxc_mode *mode;
 	u32 htot, vtot;
 	u32 fps;
 
+	mode = lt7911uxc_find_best_fit(lt7911uxc);
+	lt7911uxc->cur_mode = mode;
 	htot = lt7911uxc->cur_mode->hts_def;
 	vtot = lt7911uxc->cur_mode->vts_def;
 	if (bt->interlaced)
@@ -749,7 +809,7 @@ static void lt7911uxc_print_dv_timings(struct v4l2_subdev *sd, const char *prefi
 	if (prefix == NULL)
 		prefix = "";
 
-	v4l2_info(sd, "%s: %s%ux%u%s%u.%02u (%ux%u)\n", sd->name, prefix,
+	dev_info(dev, "%s: %s%ux%u%s%u.%02u (%ux%u)\n", sd->name, prefix,
 		bt->width, bt->height, bt->interlaced ? "i" : "p",
 		fps / 100, fps % 100, htot, vtot);
 }
@@ -992,33 +1052,6 @@ static int lt7911uxc_enum_frame_sizes(struct v4l2_subdev *sd,
 	return 0;
 }
 
-static int lt7911uxc_get_reso_dist(const struct lt7911uxc_mode *mode,
-				struct v4l2_mbus_framefmt *framefmt)
-{
-	return abs(mode->width - framefmt->width) +
-		abs(mode->height - framefmt->height);
-}
-
-static const struct lt7911uxc_mode *
-lt7911uxc_find_best_fit(struct lt7911uxc *lt7911uxc, struct v4l2_subdev_format *fmt)
-{
-	struct v4l2_mbus_framefmt *framefmt = &fmt->format;
-	int dist;
-	int cur_best_fit = 0;
-	int cur_best_fit_dist = -1;
-	unsigned int i;
-
-	for (i = 0; i < lt7911uxc->cfg_num; i++) {
-		dist = lt7911uxc_get_reso_dist(&lt7911uxc->support_modes[i], framefmt);
-		if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
-			cur_best_fit_dist = dist;
-			cur_best_fit = i;
-		}
-	}
-
-	return &lt7911uxc->support_modes[cur_best_fit];
-}
-
 static int lt7911uxc_get_fmt(struct v4l2_subdev *sd,
 			struct v4l2_subdev_pad_config *cfg,
 			struct v4l2_subdev_format *format)
@@ -1036,7 +1069,7 @@ static int lt7911uxc_get_fmt(struct v4l2_subdev *sd,
 	format->format.colorspace = V4L2_COLORSPACE_SRGB;
 	mutex_unlock(&lt7911uxc->confctl_mutex);
 
-	mode = lt7911uxc_find_best_fit(lt7911uxc, format);
+	mode = lt7911uxc_find_best_fit(lt7911uxc);
 	lt7911uxc->cur_mode = mode;
 
 	__v4l2_ctrl_s_ctrl_int64(lt7911uxc->pixel_rate,
@@ -1100,7 +1133,7 @@ static int lt7911uxc_set_fmt(struct v4l2_subdev *sd,
 		return 0;
 
 	lt7911uxc->mbus_fmt_code = format->format.code;
-	mode = lt7911uxc_find_best_fit(lt7911uxc, format);
+	mode = lt7911uxc_find_best_fit(lt7911uxc);
 	lt7911uxc->cur_mode = mode;
 
 	enable_stream(sd, false);
@@ -1480,11 +1513,6 @@ static int lt7911uxc_probe_of(struct lt7911uxc *lt7911uxc)
 
 	lt7911uxc->enable_hdcp = false;
 
-	gpiod_set_value(lt7911uxc->power_gpio, 1);
-	//delay 2~3ms before reset
-	usleep_range(2000, 3000);
-	gpiod_set_value(lt7911uxc->reset_gpio, 0);
-
 	ret = 0;
 
 put_node:
@@ -1497,6 +1525,61 @@ static inline int lt7911uxc_probe_of(struct lt7911uxc *state)
 	return -ENODEV;
 }
 #endif
+
+static int __lt7911uxc_power_on(struct lt7911uxc *lt7911uxc)
+{
+	struct device *dev = &lt7911uxc->i2c_client->dev;
+
+	dev_info(dev, "lt7911uxc power on\n");
+	gpiod_set_value(lt7911uxc->reset_gpio, 1);
+	usleep_range(20000, 25000);
+	gpiod_set_value(lt7911uxc->power_gpio, 1);
+	//delay 20ms before reset
+	usleep_range(25000, 30000);
+	gpiod_set_value(lt7911uxc->reset_gpio, 0);
+	usleep_range(25000, 30000);
+
+	return 0;
+}
+
+static void __lt7911uxc_power_off(struct lt7911uxc *lt7911uxc)
+{
+	struct device *dev = &lt7911uxc->i2c_client->dev;
+
+	dev_info(dev, "lt7911uxc power off\n");
+
+	if (!IS_ERR(lt7911uxc->reset_gpio))
+		gpiod_set_value(lt7911uxc->reset_gpio, 1);
+
+	if (!IS_ERR(lt7911uxc->power_gpio))
+		gpiod_set_value(lt7911uxc->power_gpio, 0);
+}
+
+static int lt7911uxc_resume(struct device *dev)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
+
+	return __lt7911uxc_power_on(lt7911uxc);
+}
+
+static int lt7911uxc_suspend(struct device *dev)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
+
+	__lt7911uxc_power_off(lt7911uxc);
+
+	return 0;
+}
+
+static const struct dev_pm_ops lt7911uxc_pm_ops = {
+	.suspend = lt7911uxc_suspend,
+	.resume = lt7911uxc_resume,
+};
+
 static int lt7911uxc_check_chip_id(struct lt7911uxc *lt7911uxc)
 {
 	struct device *dev = &lt7911uxc->i2c_client->dev;
@@ -1524,6 +1607,8 @@ static int lt7911uxc_check_chip_id(struct lt7911uxc *lt7911uxc)
 static int lt7911uxc_probe(struct i2c_client *client,
 			  const struct i2c_device_id *id)
 {
+	struct v4l2_dv_timings default_timing =
+				V4L2_DV_BT_CEA_640X480P59_94;
 	struct lt7911uxc *lt7911uxc;
 	struct v4l2_subdev *sd;
 	struct device *dev = &client->dev;
@@ -1549,47 +1634,14 @@ static int lt7911uxc_probe(struct i2c_client *client,
 		return err;
 	}
 
+	lt7911uxc->timings = default_timing;
 	lt7911uxc->cur_mode = &lt7911uxc->support_modes[0];
+
+	__lt7911uxc_power_on(lt7911uxc);
 	err = lt7911uxc_check_chip_id(lt7911uxc);
 	if (err < 0)
 		return err;
 
-	mutex_init(&lt7911uxc->confctl_mutex);
-	err = lt7911uxc_init_v4l2_ctrls(lt7911uxc);
-	if (err)
-		goto err_free_hdl;
-
-	client->flags |= I2C_CLIENT_SCCB;
-#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
-	v4l2_i2c_subdev_init(sd, client, &lt7911uxc_ops);
-	sd->internal_ops = &lt7911uxc_internal_ops;
-	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
-#endif
-
-#if defined(CONFIG_MEDIA_CONTROLLER)
-	lt7911uxc->pad.flags = MEDIA_PAD_FL_SOURCE;
-	sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
-	err = media_entity_pads_init(&sd->entity, 1, &lt7911uxc->pad);
-	if (err < 0) {
-		v4l2_err(sd, "media entity init failed! err:%d\n", err);
-		goto err_free_hdl;
-	}
-#endif
-	memset(facing, 0, sizeof(facing));
-	if (strcmp(lt7911uxc->module_facing, "back") == 0)
-		facing[0] = 'b';
-	else
-		facing[0] = 'f';
-
-	snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
-		 lt7911uxc->module_index, facing,
-		 LT7911UXC_NAME, dev_name(sd->dev));
-	err = v4l2_async_register_subdev_sensor_common(sd);
-	if (err < 0) {
-		v4l2_err(sd, "v4l2 register subdev failed! err:%d\n", err);
-		goto err_clean_entity;
-	}
-
 	INIT_DELAYED_WORK(&lt7911uxc->delayed_work_hotplug,
 			lt7911uxc_delayed_work_hotplug);
 	INIT_DELAYED_WORK(&lt7911uxc->delayed_work_res_change,
@@ -1626,23 +1678,56 @@ static int lt7911uxc_probe(struct i2c_client *client,
 	if (err)
 		dev_err(dev, "failed to register plugin det irq (%d), maybe no use\n", err);
 
+	mutex_init(&lt7911uxc->confctl_mutex);
+	err = lt7911uxc_init_v4l2_ctrls(lt7911uxc);
+	if (err)
+		goto err_free_hdl;
+
+	client->flags |= I2C_CLIENT_SCCB;
+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
+	v4l2_i2c_subdev_init(sd, client, &lt7911uxc_ops);
+	sd->internal_ops = &lt7911uxc_internal_ops;
+	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
+#endif
+
+#if defined(CONFIG_MEDIA_CONTROLLER)
+	lt7911uxc->pad.flags = MEDIA_PAD_FL_SOURCE;
+	sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
+	err = media_entity_pads_init(&sd->entity, 1, &lt7911uxc->pad);
+	if (err < 0) {
+		v4l2_err(sd, "media entity init failed! err:%d\n", err);
+		goto err_free_hdl;
+	}
+#endif
+	memset(facing, 0, sizeof(facing));
+	if (strcmp(lt7911uxc->module_facing, "back") == 0)
+		facing[0] = 'b';
+	else
+		facing[0] = 'f';
+
+	snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
+		 lt7911uxc->module_index, facing,
+		 LT7911UXC_NAME, dev_name(sd->dev));
+	err = v4l2_async_register_subdev_sensor_common(sd);
+	if (err < 0) {
+		v4l2_err(sd, "v4l2 register subdev failed! err:%d\n", err);
+		goto err_clean_entity;
+	}
+
 	err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
 	if (err) {
 		v4l2_err(sd, "v4l2 ctrl handler setup failed! err:%d\n", err);
-		goto err_work_queues;
+		goto err_clean_entity;
 	}
-	lt7911uxc_format_change(sd);
 
+	schedule_delayed_work(&lt7911uxc->delayed_work_res_change, 100);
+
+	enable_stream(sd, false);
 	v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
 			client->addr << 1, client->adapter->name);
 
 	return 0;
 
-err_work_queues:
-	if (!lt7911uxc->i2c_client->irq)
-		flush_work(&lt7911uxc->work_i2c_poll);
-	cancel_delayed_work(&lt7911uxc->delayed_work_hotplug);
-	cancel_delayed_work(&lt7911uxc->delayed_work_res_change);
 err_clean_entity:
 #if defined(CONFIG_MEDIA_CONTROLLER)
 	media_entity_cleanup(&sd->entity);
@@ -1650,6 +1735,12 @@ err_clean_entity:
 err_free_hdl:
 	v4l2_ctrl_handler_free(&lt7911uxc->hdl);
 	mutex_destroy(&lt7911uxc->confctl_mutex);
+err_work_queues:
+	if (!lt7911uxc->i2c_client->irq)
+		flush_work(&lt7911uxc->work_i2c_poll);
+	cancel_delayed_work(&lt7911uxc->delayed_work_hotplug);
+	cancel_delayed_work(&lt7911uxc->delayed_work_res_change);
+
 	return err;
 }
 
@@ -1687,6 +1778,7 @@ MODULE_DEVICE_TABLE(of, lt7911uxc_of_match);
 static struct i2c_driver lt7911uxc_driver = {
 	.driver = {
 		.name = LT7911UXC_NAME,
+		.pm = &lt7911uxc_pm_ops,
 		.of_match_table = of_match_ptr(lt7911uxc_of_match),
 	},
 	.probe = lt7911uxc_probe,

From 6676316bd08d246b06e9d455e930f496db97d65c Mon Sep 17 00:00:00 2001
From: Jianwei Fan <jianwei.fan@rock-chips.com>
Date: Mon, 5 Jun 2023 09:25:43 +0000
Subject: [PATCH 49/60] media: i2c: lt6911uxe/c: set default timing

Change-Id: Id22160e280ef23d93e9ad8cbe5ab972eb6f98c11
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
---
 drivers/media/i2c/lt6911uxc.c | 3 +++
 drivers/media/i2c/lt6911uxe.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/media/i2c/lt6911uxc.c b/drivers/media/i2c/lt6911uxc.c
index 02af340a4f15..23da66e26ac7 100644
--- a/drivers/media/i2c/lt6911uxc.c
+++ b/drivers/media/i2c/lt6911uxc.c
@@ -1282,6 +1282,8 @@ static inline int lt6911uxc_parse_of(struct lt6911uxc *lt6911uxc)
 static int lt6911uxc_probe(struct i2c_client *client,
 		const struct i2c_device_id *id)
 {
+	struct v4l2_dv_timings default_timing =
+				V4L2_DV_BT_CEA_640X480P59_94;
 	struct lt6911uxc *lt6911uxc;
 	struct v4l2_subdev *sd;
 	struct device *dev = &client->dev;
@@ -1299,6 +1301,7 @@ static int lt6911uxc_probe(struct i2c_client *client,
 
 	sd = &lt6911uxc->sd;
 	lt6911uxc->i2c_client = client;
+	lt6911uxc->timings = default_timing;
 	lt6911uxc->cur_mode = &supported_modes[0];
 	lt6911uxc->mbus_fmt_code = LT6911UXC_MEDIA_BUS_FMT;
 
diff --git a/drivers/media/i2c/lt6911uxe.c b/drivers/media/i2c/lt6911uxe.c
index a14ba83ab8cb..50cf2920eed0 100644
--- a/drivers/media/i2c/lt6911uxe.c
+++ b/drivers/media/i2c/lt6911uxe.c
@@ -1777,6 +1777,8 @@ static int lt6911uxe_check_chip_id(struct lt6911uxe *lt6911uxe)
 static int lt6911uxe_probe(struct i2c_client *client,
 			  const struct i2c_device_id *id)
 {
+	struct v4l2_dv_timings default_timing =
+				V4L2_DV_BT_CEA_640X480P59_94;
 	struct lt6911uxe *lt6911uxe;
 	struct v4l2_subdev *sd;
 	struct device *dev = &client->dev;
@@ -1802,6 +1804,7 @@ static int lt6911uxe_probe(struct i2c_client *client,
 		return err;
 	}
 
+	lt6911uxe->timings = default_timing;
 	lt6911uxe->cur_mode = &lt6911uxe->support_modes[0];
 	err = lt6911uxe_check_chip_id(lt6911uxe);
 	if (err < 0)

From 1d030d294ec7186ee402419a3759291e7b0a198c Mon Sep 17 00:00:00 2001
From: Zhang Yubing <yubing.zhang@rock-chips.com>
Date: Sun, 23 Apr 2023 15:28:25 +0800
Subject: [PATCH 50/60] drm/rockchip: dw-dp: notify audio when enable/disable
 dptx

Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I61e07cce16f8e0a30e6a67ff508be03a5b249563
---
 drivers/gpu/drm/rockchip/dw-dp.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-dp.c b/drivers/gpu/drm/rockchip/dw-dp.c
index 66522bfb7e77..1f399982fceb 100644
--- a/drivers/gpu/drm/rockchip/dw-dp.c
+++ b/drivers/gpu/drm/rockchip/dw-dp.c
@@ -3106,6 +3106,9 @@ static void dw_dp_bridge_atomic_enable(struct drm_bridge *bridge,
 
 	if (dp->panel)
 		drm_panel_enable(dp->panel);
+
+	extcon_set_state_sync(dp->extcon, EXTCON_DISP_DP, true);
+	dw_dp_audio_handle_plugged_change(&dp->audio, true);
 }
 
 static void dw_dp_reset(struct dw_dp *dp)
@@ -3141,6 +3144,9 @@ static void dw_dp_bridge_atomic_disable(struct drm_bridge *bridge,
 	dw_dp_link_disable(dp);
 	bitmap_zero(dp->sdp_reg_bank, SDP_REG_BANK_SIZE);
 	dw_dp_reset(dp);
+
+	extcon_set_state_sync(dp->extcon, EXTCON_DISP_DP, false);
+	dw_dp_audio_handle_plugged_change(&dp->audio, false);
 }
 
 static bool dw_dp_detect_dpcd(struct dw_dp *dp)
@@ -3200,14 +3206,6 @@ static enum drm_connector_status dw_dp_bridge_detect(struct drm_bridge *bridge)
 	}
 
 out:
-	if (status == connector_status_connected) {
-		extcon_set_state_sync(dp->extcon, EXTCON_DISP_DP, true);
-		dw_dp_audio_handle_plugged_change(&dp->audio, true);
-	} else {
-		extcon_set_state_sync(dp->extcon, EXTCON_DISP_DP, false);
-		dw_dp_audio_handle_plugged_change(&dp->audio, false);
-	}
-
 	return status;
 }
 

From dcc194b4d4a1b299c39c5d416cabfb9ba13d2141 Mon Sep 17 00:00:00 2001
From: Steven Liu <steven.liu@rock-chips.com>
Date: Fri, 19 May 2023 18:06:24 +0800
Subject: [PATCH 51/60] arm64: dts: rockchip: rk3528: Split I2Sx pinctrl

Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: Ibfc99cfbd5ef324f549ae356059b7fc7ab45fe96
---
 .../boot/dts/rockchip/rk3528-pinctrl.dtsi     | 138 ++++++++++++++----
 arch/arm64/boot/dts/rockchip/rk3528.dtsi      |  16 +-
 2 files changed, 127 insertions(+), 27 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi
index 969b8c09ec23..2b8b2d38bf6b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi
@@ -363,60 +363,148 @@
 
 	i2s0 {
 		/omit-if-no-ref/
-		i2s0m0_pins: i2s0m0-pins {
+		i2s0m0_lrck: i2s0m0-lrck {
 			rockchip,pins =
 				/* i2s0_lrck_m0 */
-				<3 RK_PB6 1 &pcfg_pull_none>,
+				<3 RK_PB6 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s0m0_mclk: i2s0m0-mclk {
+			rockchip,pins =
 				/* i2s0_mclk_m0 */
-				<3 RK_PB4 1 &pcfg_pull_none>,
+				<3 RK_PB4 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s0m0_sclk: i2s0m0-sclk {
+			rockchip,pins =
 				/* i2s0_sclk_m0 */
-				<3 RK_PB5 1 &pcfg_pull_none>,
-				/* i2s0_sdi_m0 */
-				<3 RK_PB7 1 &pcfg_pull_none>,
-				/* i2s0_sdo_m0 */
+				<3 RK_PB5 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s0m0_sdi: i2s0m0-sdi {
+			rockchip,pins =
+				/* i2s0m0_sdi */
+				<3 RK_PB7 1 &pcfg_pull_none>;
+		};
+		/omit-if-no-ref/
+		i2s0m0_sdo: i2s0m0-sdo {
+			rockchip,pins =
+				/* i2s0m0_sdo */
 				<3 RK_PC0 1 &pcfg_pull_none>;
 		};
 
 		/omit-if-no-ref/
-		i2s0m1_pins: i2s0m1-pins {
+		i2s0m1_lrck: i2s0m1-lrck {
 			rockchip,pins =
 				/* i2s0_lrck_m1 */
-				<1 RK_PB6 1 &pcfg_pull_none>,
+				<1 RK_PB6 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s0m1_mclk: i2s0m1-mclk {
+			rockchip,pins =
 				/* i2s0_mclk_m1 */
-				<1 RK_PB4 1 &pcfg_pull_none>,
+				<1 RK_PB4 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s0m1_sclk: i2s0m1-sclk {
+			rockchip,pins =
 				/* i2s0_sclk_m1 */
-				<1 RK_PB5 1 &pcfg_pull_none>,
-				/* i2s0_sdi_m1 */
-				<1 RK_PB7 1 &pcfg_pull_none>,
-				/* i2s0_sdo_m1 */
+				<1 RK_PB5 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s0m1_sdi: i2s0m1-sdi {
+			rockchip,pins =
+				/* i2s0m1_sdi */
+				<1 RK_PB7 1 &pcfg_pull_none>;
+		};
+		/omit-if-no-ref/
+		i2s0m1_sdo: i2s0m1-sdo {
+			rockchip,pins =
+				/* i2s0m1_sdo */
 				<1 RK_PC0 1 &pcfg_pull_none>;
 		};
 	};
 
 	i2s1 {
 		/omit-if-no-ref/
-		i2s1_pins: i2s1-pins {
+		i2s1_lrck: i2s1-lrck {
 			rockchip,pins =
 				/* i2s1_lrck */
-				<4 RK_PA6 1 &pcfg_pull_none>,
+				<4 RK_PA6 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1_mclk: i2s1-mclk {
+			rockchip,pins =
 				/* i2s1_mclk */
-				<4 RK_PA4 1 &pcfg_pull_none>,
+				<4 RK_PA4 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1_sclk: i2s1-sclk {
+			rockchip,pins =
 				/* i2s1_sclk */
-				<4 RK_PA5 1 &pcfg_pull_none>,
+				<4 RK_PA5 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1_sdi0: i2s1-sdi0 {
+			rockchip,pins =
 				/* i2s1_sdi0 */
-				<4 RK_PB4 1 &pcfg_pull_none>,
+				<4 RK_PB4 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1_sdi1: i2s1-sdi1 {
+			rockchip,pins =
 				/* i2s1_sdi1 */
-				<4 RK_PB3 1 &pcfg_pull_none>,
+				<4 RK_PB3 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1_sdi2: i2s1-sdi2 {
+			rockchip,pins =
 				/* i2s1_sdi2 */
-				<4 RK_PA3 1 &pcfg_pull_none>,
+				<4 RK_PA3 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1_sdi3: i2s1-sdi3 {
+			rockchip,pins =
 				/* i2s1_sdi3 */
-				<4 RK_PA2 1 &pcfg_pull_none>,
+				<4 RK_PA2 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1_sdo0: i2s1-sdo0 {
+			rockchip,pins =
 				/* i2s1_sdo0 */
-				<4 RK_PA7 1 &pcfg_pull_none>,
+				<4 RK_PA7 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1_sdo1: i2s1-sdo1 {
+			rockchip,pins =
 				/* i2s1_sdo1 */
-				<4 RK_PB0 1 &pcfg_pull_none>,
+				<4 RK_PB0 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1_sdo2: i2s1-sdo2 {
+			rockchip,pins =
 				/* i2s1_sdo2 */
-				<4 RK_PB1 1 &pcfg_pull_none>,
+				<4 RK_PB1 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1_sdo3: i2s1-sdo3 {
+			rockchip,pins =
 				/* i2s1_sdo3 */
 				<4 RK_PB2 1 &pcfg_pull_none>;
 		};
diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
index 17f4962216c5..66d48e7fcbdf 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -1938,7 +1938,10 @@
 		resets = <&cru SRST_MRESETN_SAI_I2S0>, <&cru SRST_HRESETN_SAI_I2S0>;
 		reset-names = "m", "h";
 		pinctrl-names = "default";
-		pinctrl-0 = <&i2s0m0_pins>;
+		pinctrl-0 = <&i2s0m0_lrck
+			     &i2s0m0_sclk
+			     &i2s0m0_sdi
+			     &i2s0m0_sdo>;
 		#sound-dai-cells = <0>;
 		status = "disabled";
 	};
@@ -1968,7 +1971,16 @@
 		resets = <&cru SRST_MRESETN_SAI_I2S1>, <&cru SRST_HRESETN_SAI_I2S1>;
 		reset-names = "m", "h";
 		pinctrl-names = "default";
-		pinctrl-0 = <&i2s1_pins>;
+		pinctrl-0 = <&i2s1_sclk
+			     &i2s1_lrck
+			     &i2s1_sdi0
+			     &i2s1_sdi1
+			     &i2s1_sdi2
+			     &i2s1_sdi3
+			     &i2s1_sdo0
+			     &i2s1_sdo1
+			     &i2s1_sdo2
+			     &i2s1_sdo3>;
 		#sound-dai-cells = <0>;
 		status = "disabled";
 	};

From c5cdbfc2eb071349eaf00de3795f2c2c2bfe21fb Mon Sep 17 00:00:00 2001
From: Zou Dengming <marsow.zou@rock-chips.com>
Date: Mon, 15 May 2023 22:46:55 +0800
Subject: [PATCH 52/60] arm64: dts: rockchip: rk3528-evb: prepare bt sco
 settings

we don't directly add bt-sco cards because it may take some
i2s/pcm, which may use dma, but dmas may limit.
so we just prepare this settings, then if any one who want to
support bt-sco, he/she can just add dts in board-level dtsi.

For example diff in "rk3528-evb1-ddr4-v10.dtsi":

+&bt_sco {
+       status = "okay";
+};
+
+&bt_sound {
+       status = "okay";
+};
+
+&sai0{
+       status = "okay";
+};

The default pcm/i2s setting is:
Format: PCM, dsp_a, MSB first, short sync, rising edge and 1 bclk.
rockchip soc: master; Bt controller: slave

Change-Id: I64e76c2ae4b8449e2ee345587e080b3a70521ed9
Signed-off-by: Zou Dengming <marsow.zou@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3528-demo.dtsi | 26 +++++++++++++++++++
 arch/arm64/boot/dts/rockchip/rk3528-evb.dtsi  | 26 +++++++++++++++++++
 .../dts/rockchip/rk3528-evb3-lp4x-v10.dtsi    |  5 ++++
 3 files changed, 57 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3528-demo.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-demo.dtsi
index 548391f6da8b..94d2bcaeb017 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528-demo.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528-demo.dtsi
@@ -40,6 +40,27 @@
 		};
 	};
 
+	bt_sco: bt-sco {
+		status = "disabled";
+		compatible = "delta,dfbmcs320";
+		#sound-dai-cells = <0>;
+	};
+
+	bt_sound: bt-sound {
+		status = "disabled";
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "dsp_a";
+		simple-audio-card,bitclock-inversion = <0>;
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,name = "rockchip,bt";
+		simple-audio-card,cpu {
+			sound-dai = <&sai0>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&bt_sco>;
+		};
+	};
+
 	dc_12v: dc-12v {
 		compatible = "regulator-fixed";
 		regulator-name = "dc_12v";
@@ -369,6 +390,11 @@
 	>;
 };
 
+&sai0 {
+	pinctrl-0 = <&i2s0m0_lrck &i2s0m0_sclk &i2s0m0_sdi &i2s0m0_sdo>;
+	status = "disabled";
+};
+
 &sai2 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/rockchip/rk3528-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-evb.dtsi
index d316f3c45751..4d95d6276692 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528-evb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528-evb.dtsi
@@ -39,6 +39,27 @@
 		};
 	};
 
+	bt_sco: bt-sco {
+		status = "disabled";
+		compatible = "delta,dfbmcs320";
+		#sound-dai-cells = <0>;
+	};
+
+	bt_sound: bt-sound {
+		status = "disabled";
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "dsp_a";
+		simple-audio-card,bitclock-inversion = <0>;
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,name = "rockchip,bt";
+		simple-audio-card,cpu {
+			sound-dai = <&sai0>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&bt_sco>;
+		};
+	};
+
 	dc_12v: dc-12v {
 		compatible = "regulator-fixed";
 		regulator-name = "dc_12v";
@@ -530,6 +551,11 @@
 	>;
 };
 
+&sai0 {
+	pinctrl-0 = <&i2s0m1_lrck &i2s0m1_sclk &i2s0m1_sdi &i2s0m1_sdo>;
+	status = "disabled";
+};
+
 &sai2 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/rockchip/rk3528-evb3-lp4x-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-evb3-lp4x-v10.dtsi
index 153f9dc528f1..a427da4e2376 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528-evb3-lp4x-v10.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528-evb3-lp4x-v10.dtsi
@@ -85,6 +85,11 @@
 	status = "okay";
 };
 
+&sai0 {
+	pinctrl-0 = <&i2s0m0_lrck &i2s0m0_sclk &i2s0m0_sdi &i2s0m0_sdo>;
+	status = "disabled";
+};
+
 &uart2 {
 	status = "okay";
 	pinctrl-names = "default";

From eaf544c6d90912cbbcdeee4a014ae347b4e63082 Mon Sep 17 00:00:00 2001
From: Zhen Chen <chenzhen@rock-chips.com>
Date: Mon, 24 Apr 2023 10:48:30 +0800
Subject: [PATCH 53/60] Mali: bifrost: disable tiler heap reclaiming temporally

Comes from mail "230423: 15:04: ARM support: Yao: ".

This patch and fw_230426 can resolve the occurrence
of "Unhandled Page fault" and CS_FAULTs exceptions
in the stress test "Dvfs+Gl_retrace+Rockx+emmc".

In another mail, Yao said "before any further suggestion or conclusion from RD,
you could temporally WA the issue by disable tiler heap reclaim".

Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
Change-Id: If06aa8e207b05f1a277aae9a86d1ff76b9a9f93b
---
 .../bifrost/csf/mali_kbase_csf_tiler_heap_reclaim.c  | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/drivers/gpu/arm/bifrost/csf/mali_kbase_csf_tiler_heap_reclaim.c b/drivers/gpu/arm/bifrost/csf/mali_kbase_csf_tiler_heap_reclaim.c
index 069e827d16ff..6357e3518d87 100644
--- a/drivers/gpu/arm/bifrost/csf/mali_kbase_csf_tiler_heap_reclaim.c
+++ b/drivers/gpu/arm/bifrost/csf/mali_kbase_csf_tiler_heap_reclaim.c
@@ -344,14 +344,6 @@ void kbase_csf_tiler_heap_reclaim_mgr_init(struct kbase_device *kbdev)
 	reclaim->scan_objects = kbase_csf_tiler_heap_reclaim_scan_objects;
 	reclaim->seeks = HEAP_SHRINKER_SEEKS;
 	reclaim->batch = HEAP_SHRINKER_BATCH;
-
-#if !defined(CONFIG_MALI_VECTOR_DUMP)
-#if KERNEL_VERSION(6, 0, 0) > LINUX_VERSION_CODE
-	register_shrinker(reclaim);
-#else
-	register_shrinker(reclaim, "mali-csf-tiler-heap");
-#endif
-#endif
 }
 
 void kbase_csf_tiler_heap_reclaim_mgr_term(struct kbase_device *kbdev)
@@ -359,10 +351,6 @@ void kbase_csf_tiler_heap_reclaim_mgr_term(struct kbase_device *kbdev)
 	struct kbase_csf_scheduler *scheduler = &kbdev->csf.scheduler;
 	u8 prio;
 
-#if !defined(CONFIG_MALI_VECTOR_DUMP)
-	unregister_shrinker(&scheduler->reclaim_mgr.heap_reclaim);
-#endif
-
 	for (prio = KBASE_QUEUE_GROUP_PRIORITY_REALTIME; prio < KBASE_QUEUE_GROUP_PRIORITY_COUNT;
 	     prio++)
 		WARN_ON(!list_empty(&scheduler->reclaim_mgr.ctx_lists[prio]));

From fd4c1a5ee2fe81b039f7c17548c48ee9852cd9be Mon Sep 17 00:00:00 2001
From: Elaine Zhang <zhangqing@rock-chips.com>
Date: Tue, 6 Jun 2023 16:16:33 +0800
Subject: [PATCH 54/60] arm64: dts: rockchip: rk3588: Fixed the init frequency

Make sure that the init frequency is within the design range

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I1aea3638e0aa70e425410e71060ce89fa96e1869
---
 arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 7f4763dca331..13bb83867fd1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2371,7 +2371,8 @@
 			<&cru HCLK_PMU_CM0_ROOT>,
 			<&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
 			<&cru CLK_GPU>, <&cru CLK_SPDIF2_DP0>,
-			<&cru CLK_SPDIF5_DP1>;
+			<&cru CLK_SPDIF5_DP1>, <&cru CLK_HDMIRX_AUD>,
+			<&cru DCLK_DECOM>;
 		assigned-clock-rates =
 			<1100000000>, <786432000>,
 			<850000000>, <1188000000>,
@@ -2382,7 +2383,8 @@
 			<200000000>,
 			<375000000>, <150000000>,
 			<200000000>, <12000000>,
-			<12000000>;
+			<12000000>, <99000000>,
+			<20000000>;
 	};
 
 	i2c0: i2c@fd880000 {
@@ -3368,9 +3370,9 @@
 		interrupt-names = "irq_rkvenc0";
 		clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>, <&cru CLK_RKVENC0_CORE>;
 		clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
-		rockchip,normal-rates = <600000000>, <0>, <800000000>;
+		rockchip,normal-rates = <500000000>, <0>, <800000000>;
 		assigned-clocks = <&cru ACLK_RKVENC0>, <&cru CLK_RKVENC0_CORE>;
-		assigned-clock-rates = <600000000>, <800000000>;
+		assigned-clock-rates = <500000000>, <800000000>;
 		resets = <&cru SRST_A_RKVENC0>, <&cru SRST_H_RKVENC0>, <&cru SRST_RKVENC0_CORE>;
 		reset-names = "video_a", "video_h", "video_core";
 		rockchip,skip-pmu-idle-request;

From 1e135f352e4fb6b00b84924d0f636df530796862 Mon Sep 17 00:00:00 2001
From: Wu Liangqing <wlq@rock-chips.com>
Date: Wed, 7 Jun 2023 08:02:10 +0000
Subject: [PATCH 55/60] arm64: dts: rockchip: add rk3588-evb7-v11 board

Change-Id: If9788078dd3a428e7be8e102dff274a5aecd10a6
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/Makefile         |  4 ++--
 ...mx415.dtsi => rk3588-evb7-v11-imx415.dtsi} |  2 +-
 .../dts/rockchip/rk3588-evb7-v11-linux.dts    | 16 ++++++++++++++
 .../boot/dts/rockchip/rk3588-evb7-v11.dts     | 16 ++++++++++++++
 .../{rk3588-h0.dtsi => rk3588-evb7-v11.dtsi}  | 22 +++++++++++++------
 .../boot/dts/rockchip/rk3588-h0-v10-linux.dts | 16 --------------
 .../arm64/boot/dts/rockchip/rk3588-h0-v10.dts | 16 --------------
 7 files changed, 50 insertions(+), 42 deletions(-)
 rename arch/arm64/boot/dts/rockchip/{rk3588-h0-imx415.dtsi => rk3588-evb7-v11-imx415.dtsi} (98%)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-evb7-v11-linux.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-evb7-v11.dts
 rename arch/arm64/boot/dts/rockchip/{rk3588-h0.dtsi => rk3588-evb7-v11.dtsi} (98%)
 delete mode 100644 arch/arm64/boot/dts/rockchip/rk3588-h0-v10-linux.dts
 delete mode 100644 arch/arm64/boot/dts/rockchip/rk3588-h0-v10.dts

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 2b2df22ab2ba..f8df2cb4f742 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -167,8 +167,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v10-linux.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v10-rk1608-ipc-8x-linux.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v11-linux-ipc.dtb
-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h0-v10.dtb
-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h0-v10-linux.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-v11.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-v11-linux.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10-android.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10-ipc-4x-linux.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-h0-imx415.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11-imx415.dtsi
similarity index 98%
rename from arch/arm64/boot/dts/rockchip/rk3588-h0-imx415.dtsi
rename to arch/arm64/boot/dts/rockchip/rk3588-evb7-v11-imx415.dtsi
index f5389891113d..d5772ebb9d49 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-h0-imx415.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11-imx415.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
- * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
  *
  */
 
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11-linux.dts
new file mode 100644
index 000000000000..f4051df93d9f
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11-linux.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "rk3588-evb7-v11.dtsi"
+#include "rk3588-evb7-v11-imx415.dtsi"
+#include "rk3588-linux.dtsi"
+
+/ {
+	model = "Rockchip RK3588 EVB7 V11 Board";
+	compatible = "rockchip,rk3588-evb7-v11", "rockchip,rk3588";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11.dts
new file mode 100644
index 000000000000..24ef507c8b53
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "rk3588-evb7-v11.dtsi"
+#include "rk3588-evb7-v11-imx415.dtsi"
+#include "rk3588-android.dtsi"
+
+/ {
+	model = "Rockchip RK3588 EVB7 V11 Board";
+	compatible = "rockchip,rk3588-evb7-v11", "rockchip,rk3588";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-h0.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11.dtsi
similarity index 98%
rename from arch/arm64/boot/dts/rockchip/rk3588-h0.dtsi
rename to arch/arm64/boot/dts/rockchip/rk3588-evb7-v11.dtsi
index 6ffa01ff3df8..5bef2102f9dd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-h0.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11.dtsi
@@ -563,9 +563,9 @@
 &i2c6 {
 	status = "okay";
 
-	usbc0: fusb302@22 {
-		compatible = "fcs,fusb302";
-		reg = <0x22>;
+	usbc0: husb311@4e {
+		compatible = "hynetek,husb311";
+		reg = <0x4e>;
 		interrupt-parent = <&gpio3>;
 		interrupts = <RK_PB6 IRQ_TYPE_LEVEL_LOW>;
 		pinctrl-names = "default";
@@ -671,10 +671,6 @@
 	status = "okay";
 };
 
-&leds {
-	status = "disabled";
-};
-
 &mdio1 {
 	rgmii_phy: phy@1 {
 		compatible = "ethernet-phy-ieee802.3-c22";
@@ -752,6 +748,12 @@
 		};
 	};
 
+	leds {
+		work_leds_gpio: work-leds-gpio {
+			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
 	sdio-pwrseq {
 		wifi_enable_h: wifi-enable-h {
 			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -939,3 +941,9 @@
 &usbhost_dwc3_0 {
 	status = "disabled";
 };
+
+&work_led {
+	gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&work_leds_gpio>;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-h0-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-h0-v10-linux.dts
deleted file mode 100644
index 047c51448985..000000000000
--- a/arch/arm64/boot/dts/rockchip/rk3588-h0-v10-linux.dts
+++ /dev/null
@@ -1,16 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
- *
- */
-
-/dts-v1/;
-
-#include "rk3588-h0.dtsi"
-#include "rk3588-h0-imx415.dtsi"
-#include "rk3588-linux.dtsi"
-
-/ {
-	model = "Rockchip RK3588 H0 V10 Board";
-	compatible = "rockchip,rk3588-h0-v10", "rockchip,rk3588";
-};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-h0-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-h0-v10.dts
deleted file mode 100644
index 8037e39cdef9..000000000000
--- a/arch/arm64/boot/dts/rockchip/rk3588-h0-v10.dts
+++ /dev/null
@@ -1,16 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
- *
- */
-
-/dts-v1/;
-
-#include "rk3588-h0.dtsi"
-#include "rk3588-h0-imx415.dtsi"
-#include "rk3588-android.dtsi"
-
-/ {
-	model = "Rockchip RK3588 H0 V10 Board";
-	compatible = "rockchip,rk3588-h0-v10", "rockchip,rk3588";
-};

From 68a0cca2c3005b6f13d502539dbad191a11cfbb0 Mon Sep 17 00:00:00 2001
From: XiaoDong Huang <derrick.huang@rock-chips.com>
Date: Wed, 7 Jun 2023 15:33:14 +0800
Subject: [PATCH 56/60] soc: rockchip: pm_config: support sleep-pin-config

Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: I93f52766bfa1ce0cf97d826dc1cad5af0134a4c1
---
 drivers/soc/rockchip/rockchip_pm_config.c | 11 +++++++++++
 include/linux/rockchip/rockchip_sip.h     |  1 +
 2 files changed, 12 insertions(+)

diff --git a/drivers/soc/rockchip/rockchip_pm_config.c b/drivers/soc/rockchip/rockchip_pm_config.c
index eb4bbdff9685..639a0042b298 100644
--- a/drivers/soc/rockchip/rockchip_pm_config.c
+++ b/drivers/soc/rockchip/rockchip_pm_config.c
@@ -176,6 +176,7 @@ static int pm_config_probe(struct platform_device *pdev)
 	u32 sleep_debug_en = 0;
 	u32 apios_suspend = 0;
 	u32 io_ret_config = 0;
+	u32 sleep_pin_config[2] = {0};
 #ifndef MODULE
 	u32 virtual_poweroff_en = 0;
 #endif
@@ -259,6 +260,16 @@ static int pm_config_probe(struct platform_device *pdev)
 				 ret);
 	}
 
+	if (!of_property_read_u32_array(node,
+					"rockchip,sleep-pin-config",
+					sleep_pin_config, 2)) {
+		ret = sip_smc_set_suspend_mode(SLEEP_PIN_CONFIG, sleep_pin_config[0], sleep_pin_config[1]);
+		if (ret)
+			dev_warn(&pdev->dev,
+				 "sleep-pin-config failed (%d), check parameters or update trust\n",
+				 ret);
+	}
+
 #ifndef MODULE
 	if (!of_property_read_u32_array(node,
 					"rockchip,virtual-poweroff",
diff --git a/include/linux/rockchip/rockchip_sip.h b/include/linux/rockchip/rockchip_sip.h
index 3504da1755b3..a0ff5c7ed710 100644
--- a/include/linux/rockchip/rockchip_sip.h
+++ b/include/linux/rockchip/rockchip_sip.h
@@ -107,6 +107,7 @@
 #define SUSPEND_WFI_TIME_MS		0x08
 #define LINUX_PM_STATE			0x09
 #define SUSPEND_IO_RET_CONFIG		0x0a
+#define SLEEP_PIN_CONFIG		0x0b
 
 /* SIP_REMOTECTL_CFG call types */
 #define	REMOTECTL_SET_IRQ		0xf0

From 9004c277ca39716ccc020e044683e140149b50a8 Mon Sep 17 00:00:00 2001
From: XiaoDong Huang <derrick.huang@rock-chips.com>
Date: Wed, 7 Jun 2023 15:38:03 +0800
Subject: [PATCH 57/60] dt-bindings: suspend: rk3528: add sleep pin defines

Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: I6bffbb885c5d09bbf0c92db32112eac246f2bc56
---
 include/dt-bindings/suspend/rockchip-rk3528.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/include/dt-bindings/suspend/rockchip-rk3528.h b/include/dt-bindings/suspend/rockchip-rk3528.h
index 7f81bf8943fd..5f16a4682963 100644
--- a/include/dt-bindings/suspend/rockchip-rk3528.h
+++ b/include/dt-bindings/suspend/rockchip-rk3528.h
@@ -51,4 +51,17 @@
 #define RKPM_PWM1_M0_REGULATOR_EN	BIT(1)
 #define RKPM_PWM2_M0_REGULATOR_EN	BIT(2)
 
+/* sleep pin */
+#define RKPM_SLEEP_PIN0_EN		BIT(0)	/* GPIO4_C2 */
+#define RKPM_SLEEP_PIN1_EN		BIT(1)	/* GPIO4_B6 */
+#define RKPM_SLEEP_PIN2_EN		BIT(2)	/* GPIO0_A0 */
+#define RKPM_SLEEP_PIN3_EN		BIT(3)	/* GPIO0_A1 */
+#define RKPM_SLEEP_PIN4_EN		BIT(4)	/* GPIO0_A2 */
+#define RKPM_SLEEP_PIN5_EN		BIT(5)	/* GPIO0_A3 */
+#define RKPM_SLEEP_PIN6_EN		BIT(6)	/* GPIO0_A4 */
+#define RKPM_SLEEP_PIN7_EN		BIT(7)	/* GPIO0_A5 */
+
+#define RKPM_SLEEP_PIN0_ACT_LOW		BIT(0)	/* GPIO4_C2 */
+#define RKPM_SLEEP_PIN1_ACT_LOW		BIT(1)	/* GPIO4_B6 */
+#define RKPM_SLEEP_PIN2_7_ACT_LOW	0xfc	/* GPIO0_A0~5 */
 #endif

From 5cad0068f72465c2b9f31cb62af2072952236b26 Mon Sep 17 00:00:00 2001
From: Cai YiWei <cyw@rock-chips.com>
Date: Thu, 8 Jun 2023 09:58:53 +0800
Subject: [PATCH 58/60] media: rockchip: isp: fix isp32 and lite buf output err
 due to mi on/off

Change-Id: I7d78a12861c075e99f3005af5b8ffab2958a10b2
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
---
 .../media/platform/rockchip/isp/capture_v32.c    | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/media/platform/rockchip/isp/capture_v32.c b/drivers/media/platform/rockchip/isp/capture_v32.c
index 5a7a0c5b60c6..937ad6da1dcc 100644
--- a/drivers/media/platform/rockchip/isp/capture_v32.c
+++ b/drivers/media/platform/rockchip/isp/capture_v32.c
@@ -1052,15 +1052,24 @@ static void update_mi(struct rkisp_stream *stream)
 				/* isp no start and mi close, force to enable it */
 				if (!ISP3X_ISP_OUT_LINE(rkisp_read(dev, ISP3X_ISP_DEBUG2, true))) {
 					stream->ops->enable_mi(stream);
-					stream->is_pause = false;
 					stream_self_update(stream);
 					if (!stream->curr_buf) {
 						stream->curr_buf = stream->next_buf;
 						stream->next_buf = NULL;
 					}
+					/* maybe no next buf to preclose mi */
+					stream->ops->disable_mi(stream);
+				} else if (stream->is_pause) {
+					/* isp working and mi closed
+					 * config buf and enable mi, capture at next frame
+					 */
+					stream->ops->enable_mi(stream);
+					stream->is_pause = false;
 				}
-			}
-			if (stream->is_pause) {
+			} else if (stream->is_pause) {
+				/* isp working and mi no to close
+				 * config buf will auto update at frame end
+				 */
 				stream->ops->enable_mi(stream);
 				stream->is_pause = false;
 			}
@@ -1098,6 +1107,7 @@ static void update_mi(struct rkisp_stream *stream)
 			dev->tb_addr_idx++;
 	} else if (!stream->is_pause) {
 		stream->is_pause = true;
+		/* no next buf to preclose mi */
 		stream->ops->disable_mi(stream);
 		/* no buf, force to close mi */
 		if (!stream->curr_buf)

From d600ae58b7cb9bee2b7ec45d6fc8d83224d2b501 Mon Sep 17 00:00:00 2001
From: Weiwen Chen <cww@rock-chips.com>
Date: Thu, 8 Jun 2023 16:26:42 +0800
Subject: [PATCH 59/60] ARM: configs: rockchip: add uvc to rv1106-rndis.config

Signed-off-by: Weiwen Chen <cww@rock-chips.com>
Change-Id: I83de76ba4e7a0827f0bcfc4840db1c1b4adcacc7
---
 arch/arm/configs/rv1106-rndis.config | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/arch/arm/configs/rv1106-rndis.config b/arch/arm/configs/rv1106-rndis.config
index 098ef60900f1..7d2be8b38ccb 100644
--- a/arch/arm/configs/rv1106-rndis.config
+++ b/arch/arm/configs/rv1106-rndis.config
@@ -15,12 +15,11 @@ CONFIG_USB_SUPPORT=y
 # CONFIG_I2C_ROBOTFUZZ_OSIF is not set
 # CONFIG_I2C_TINY_USB is not set
 # CONFIG_LTE_GDM724X is not set
+# CONFIG_MDIO_MVUSB is not set
 # CONFIG_MEDIA_USB_SUPPORT is not set
 # CONFIG_MFD_DLN2 is not set
 # CONFIG_MFD_VIPERBOARD is not set
 # CONFIG_MISC_RTSX_USB is not set
-# CONFIG_MMC_USHC is not set
-# CONFIG_MMC_VUB300 is not set
 # CONFIG_MOST is not set
 # CONFIG_NOP_USB_XCEIV is not set
 # CONFIG_NVME_TARGET is not set
@@ -62,7 +61,7 @@ CONFIG_USB_CONFIGFS_F_FS=y
 # CONFIG_USB_CONFIGFS_F_UAC1 is not set
 # CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
 # CONFIG_USB_CONFIGFS_F_UAC2 is not set
-# CONFIG_USB_CONFIGFS_F_UVC is not set
+CONFIG_USB_CONFIGFS_F_UVC=y
 # CONFIG_USB_CONFIGFS_MASS_STORAGE is not set
 # CONFIG_USB_CONFIGFS_NCM is not set
 # CONFIG_USB_CONFIGFS_OBEX is not set
@@ -95,6 +94,7 @@ CONFIG_USB_DWC3_OF_SIMPLE=m
 # CONFIG_USB_FUSB300 is not set
 CONFIG_USB_F_FS=m
 CONFIG_USB_F_RNDIS=m
+CONFIG_USB_F_UVC=m
 CONFIG_USB_GADGET=m
 # CONFIG_USB_GADGETFS is not set
 # CONFIG_USB_GADGET_DEBUG is not set
@@ -129,8 +129,6 @@ CONFIG_USB_LIBCOMPOSITE=m
 # CONFIG_USB_LINK_LAYER_TEST is not set
 # CONFIG_USB_M66592 is not set
 # CONFIG_USB_MASS_STORAGE is not set
-# CONFIG_USB_MAX3420_UDC is not set
-# CONFIG_USB_MAX3421_HCD is not set
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MIDI_GADGET is not set
 # CONFIG_USB_MON is not set

From e0716c0140025007b43b1a07dc128c4d4ca5f367 Mon Sep 17 00:00:00 2001
From: Tao Huang <huangtao@rock-chips.com>
Date: Thu, 8 Jun 2023 19:04:04 +0800
Subject: [PATCH 60/60] media: i2c: lt7911uxc: Fix print format string

u64 format should be %llu.

Fixes: db473bd42390 ("media: i2c: lt7911uxc: update driver to V0.0X01.0X07")
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Iadd65d15d690222da7561a9ea67bd70082d79b45
---
 drivers/media/i2c/lt7911uxc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/media/i2c/lt7911uxc.c b/drivers/media/i2c/lt7911uxc.c
index a21235074f5f..a39f8f818a22 100644
--- a/drivers/media/i2c/lt7911uxc.c
+++ b/drivers/media/i2c/lt7911uxc.c
@@ -628,7 +628,7 @@ static int lt7911uxc_get_detected_timings(struct v4l2_subdev *sd,
 
 	v4l2_info(sd, "act:%dx%d, total:%dx%d, pixclk:%d, fps:%d\n",
 			hact, vact, htotal, vtotal, pixel_clock, fps);
-	v4l2_info(sd, "byte_clk:%u, mipi_clk:%u, mipi_data_rate:%u\n",
+	v4l2_info(sd, "byte_clk:%llu, mipi_clk:%llu, mipi_data_rate:%llu\n",
 			byte_clk, mipi_clk, mipi_data_rate);
 	v4l2_info(sd, "inerlaced:%d\n", bt->interlaced);