From 16776f1ef12db40ce2bed4fdcadfb036f571d305 Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Fri, 18 Mar 2022 09:20:22 +0800 Subject: [PATCH] phy: rockchip-samsung-hdptx-hdmi: Get actual frequency each time when enable dclk When HDMI0/1 are bound to the same VP, vop will only set one dclk rate, The frequency of another dclk will not be changed. But HDMI driver will set phy output frequency, The dclk core->rate does not correspond to the actual phy output frequency. So dclk core->rate need to be updated when enable dclk. Signed-off-by: Algea Cao Change-Id: I497bf9a01b8210c17b1c720839fc8f5d15dd0baf --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c index 94a82fa9acb6..f105b0519642 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c @@ -2070,6 +2070,7 @@ static int hdptx_phy_clk_enable(struct clk_hw *hw) } } + clk_get_rate(hdptx->dclk); hdptx->count++; return 0; @@ -2117,7 +2118,7 @@ static int rockchip_hdptx_phy_clk_register(struct rockchip_hdptx_phy *hdptx) init.parent_names = &parent_name; init.num_parents = 1; - init.flags = 0; + init.flags = CLK_GET_RATE_NOCACHE; if (!hdptx->id) init.name = "clk_hdmiphy_pixel0"; else