From 167ea3e2e95698077f5e3e0433d3467ac1610976 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Tue, 30 Nov 2021 19:45:51 +0800 Subject: [PATCH] drm/rockchip: vop2: Fix dclk_out rate calculate error in YUV420 output mode The K will be set 2 in YUV420 output mode, so we don't need to handle YUV420 for DisplayPort. Signed-off-by: Andy Yan Change-Id: I8f42536735e65c82705d58382f1db2b2994d741b --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 7780f9ebe172..ccdebef62f94 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -5221,11 +5221,9 @@ static int vop2_calc_if_clk(struct drm_crtc *crtc, const struct vop2_connector_i if_pixclk->rate = hdmi_edp_pixclk; if_dclk->rate = hdmi_edp_dclk; } else if (vcstate->output_type == DRM_MODE_CONNECTOR_DisplayPort) { - if (vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV420) - dclk_out_rate = v_pixclk >> 3; - else - dclk_out_rate = v_pixclk >> 2; - if_pixclk->rate = dclk_out_rate / K; + dclk_out_rate = v_pixclk >> 2; + dclk_out_rate = dclk_out_rate / K; + if_pixclk->rate = dclk_out_rate; } else if (vcstate->output_type == DRM_MODE_CONNECTOR_DSI) { if (vcstate->dsc_enable) { dclk_out_rate = dclk_core_rate / K;