From 173b9444910bb7d3983059ee02c0ddecf81a6f28 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 13 Nov 2023 16:01:48 +0800 Subject: [PATCH] clk: rockchip: avoid division by zero Signed-off-by: Elaine Zhang Change-Id: Ie28c61d3907d80c3d12087dea59a9567e183012d --- drivers/clk/rockchip/clk.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 66fd37b125e7..ab0444be582d 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -186,6 +186,14 @@ static void rockchip_fractional_approximation(struct clk_hw *hw, unsigned long p_rate, p_parent_rate; struct clk_hw *p_parent; + if (rate == 0) { + pr_warn("%s p_rate(%ld), rate(%ld), maybe invalid frequency setting!\n", + clk_hw_get_name(hw), *parent_rate, rate); + *m = 0; + *n = 1; + return; + } + p_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); if ((rate * 20 > p_rate) && (p_rate % rate != 0)) { p_parent = clk_hw_get_parent(clk_hw_get_parent(hw)); @@ -196,6 +204,14 @@ static void rockchip_fractional_approximation(struct clk_hw *hw, *parent_rate = p_parent_rate; } + if (*parent_rate == 0) { + pr_warn("%s p_rate(%ld), rate(%ld), maybe invalid frequency setting!\n", + clk_hw_get_name(hw), *parent_rate, rate); + *m = 0; + *n = 1; + return; + } + if (*parent_rate < rate * 20) { /* * Fractional frequency divider to do