From 179638095d6776efeca033508cfeb9c5a806a7a5 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Sat, 6 Feb 2021 09:20:18 +0800 Subject: [PATCH] phy: rockchip: naneng-combphy: Adjust 100M refclk parameter for PCIe Change-Id: I94321c0b6bb64cff279b79c44b54f273ee52c897 Signed-off-by: Shawn Lin --- .../rockchip/phy-rockchip-naneng-combphy.c | 21 ++++++++----------- 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 712d8e11496e..6ec10ca797b2 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -500,26 +500,23 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) case 100000000: param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); if (priv->mode == PHY_TYPE_PCIE) { + /* PLL KVCO tuning fine */ + val = readl(priv->mmio + (0x20 << 2)); + val &= ~(0x7 << 2); + val |= 0x2 << 2; + writel(val, priv->mmio + (0x20 << 2)); + /* Enable controlling random jitter, aka RMJ */ - val = readl(priv->mmio + (0xb << 2)); - val &= ~(0x7); - val |= 0x1 << 6 | 0x6; - writel(val, priv->mmio + (0xb << 2)); + writel(0x4, priv->mmio + (0xb << 2)); val = readl(priv->mmio + (0x5 << 2)); val &= ~(0x3 << 6); val |= 0x1 << 6; writel(val, priv->mmio + (0x5 << 2)); - val = readl(priv->mmio + (0x11 << 2)); - val &= ~(0x7f); - val |= 0x19; - writel(val, priv->mmio + (0x11 << 2)); + writel(0x32, priv->mmio + (0x11 << 2)); + writel(0xf0, priv->mmio + (0xa << 2)); - val = readl(priv->mmio + (0xa << 2)); - val &= ~(0xf << 4); - val |= 0x7 << 4; - writel(val, priv->mmio + (0xa << 2)); } break; default: