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1.suport emmc,2.Improve buffer performance.
This commit is contained in:
zhaoyifeng
@@ -1,11 +1,9 @@
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#
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# linux/drivers/nand/Makefile
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#
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# $Id: Makefile,v 1.2.4.1 2010/07/14 02:28:12 Administrator Exp $
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# $Id: Makefile,v 1.2 2010/12/27 08:46:52 Administrator Exp $
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#
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obj-$(CONFIG_MTD_NAND_RK29XX) += flash.o
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obj-$(CONFIG_MTD_NAND_RK29XX) += ftl.o
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obj-$(CONFIG_MTD_NAND_RK29XX) += rknand_base.o
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obj-$(CONFIG_MTD_NAND_RK29XX) += flash.o ftl.o rknand_base.o emmc.o
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obj-$(CONFIG_MTD_RKNAND_BUFFER) += rknand_buffer.o
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#obj-$(CONFIG_MTD_UBI) += ubi/
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@@ -189,4 +189,13 @@ int FtlPageRead(int Index, int nSec, void *buf);
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***************************************************************************/
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char GetSNSectorInfo(char * pbuf);
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extern int NandInit(void);
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extern int NandRead(unsigned int Index, unsigned int nSec, void * buf) ;
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extern int NandWriteImage(unsigned int Index, unsigned int nSec, void * buf);
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extern int NandWrite(unsigned int Index, unsigned int nSec, void * buf) ;
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extern int NandDeInit(void) ;
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extern unsigned int NandGetCapacity(void);
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extern void NandSetSysProtAddr(unsigned int SysImageWriteEndAdd);
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#endif
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733
drivers/mtd/rknand/emmc.uu
Normal file
733
drivers/mtd/rknand/emmc.uu
Normal file
@@ -0,0 +1,733 @@
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begin 644 emmc.o
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|
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|
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|
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|
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|
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|
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|
||||
'`P``*@(`````
|
||||
`
|
||||
end
|
||||
@@ -12,154 +12,517 @@ Revision: 1.00
|
||||
********************************************************************************/
|
||||
#ifndef _EPPHAL_H
|
||||
#define _EPPHAL_H
|
||||
#define read_XDATA32(address) (*((uint32 volatile*)(address)))
|
||||
#define write_XDATA32(address, value) (*((uint32 volatile*)(address)) = value)
|
||||
#define read_XDATA32(address) (*((uint32 volatile*)(address)))
|
||||
#define write_XDATA32(address, value) (*((uint32 volatile*)(address)) = value)
|
||||
|
||||
typedef enum _CLK_GATE
|
||||
{
|
||||
/* SCU CLK GATE 0 CON */
|
||||
CLK_GATE_CORE = 0,
|
||||
CLK_GATE_CORE_APB,
|
||||
CLK_GATE_CORE_ATB,
|
||||
CLK_GATE_CPU_AXI,
|
||||
CLK_GATE_CPU_AXI2,
|
||||
CLK_GATE_CPU_AHB,
|
||||
CLK_GATE_CPU_MATRIX1_AHB,
|
||||
CLK_GATE_CPU_APB,
|
||||
CLK_GATE_CPU_ATB,
|
||||
CLK_GATE_DMA0,
|
||||
CLK_GATE_DMA1,
|
||||
CLK_GATE_GIC,
|
||||
CLK_GATE_IMEM,
|
||||
CLK_GATE_EBROM = 14,
|
||||
CLK_GATE_I2S0,
|
||||
CLK_GATE_I2S1,
|
||||
CLK_GATE_SPDIF,
|
||||
CLK_GATE_DDR_PHY,
|
||||
CLK_GATE_DDR_REG,
|
||||
CLK_GATE_DDR_CPU,
|
||||
CLK_GATE_EFUSE,
|
||||
CLK_GATE_TZPC,
|
||||
CLK_GATE_TIMER0,
|
||||
CLK_GATE_GPIO0,
|
||||
CLK_GATE_UART0,
|
||||
CLK_GATE_I2C0,
|
||||
CLK_GATE_DEBUG,
|
||||
CLK_GATE_TPIU,
|
||||
CLK_GATE_RTC,
|
||||
CLK_GATE_PMU,
|
||||
CLK_GATE_GRF,
|
||||
|
||||
/* SCU CLK GATE 1 CON */
|
||||
CLK_GATE_PEIRPH_AXI = 32,
|
||||
CLK_GATE_PEIRPH_AHB,
|
||||
CLK_GATE_PEIRPH_APB,
|
||||
CLK_GATE_EMEM,
|
||||
CLK_GATE_USB,
|
||||
CLK_GATE_DMA2,
|
||||
CLK_GATE_DDR_PERIPH,
|
||||
CLK_GATE_PERIPH,
|
||||
|
||||
/* FIXME */
|
||||
CLK_GATE_SMC_AXI,
|
||||
CLK_GATE_SMC,
|
||||
CLK_GATE_MAC_AHB = 43,
|
||||
CLK_GATE_MAC_PHY,
|
||||
CLK_GATE_MAC_TX,
|
||||
CLK_GATE_MAC_RX,
|
||||
CLK_GATE_HIF,
|
||||
CLK_GATE_NANDC,
|
||||
CLK_GATE_HSADC_AHB,
|
||||
CLK_GATE_HSADC,
|
||||
CLK_GATE_SDMMC0_AHB,
|
||||
CLK_GATE_SDMMC0,
|
||||
CLK_GATE_SDMMC1_AHB,
|
||||
CLK_GATE_SDMMC1,
|
||||
CLK_GATE_EMMC_AHB,
|
||||
CLK_GATE_EMMC,
|
||||
CLK_GATE_USBOTG0,
|
||||
CLK_GATE_USBPHY0,
|
||||
CLK_GATE_USBOTG1,
|
||||
CLK_GATE_USBPHY1,
|
||||
CLK_GATE_UHOST_AHB,
|
||||
CLK_GATE_UHOST,
|
||||
CLK_GATE_PID_FILTER,
|
||||
|
||||
/* SCU CLK GATE 2 CON */
|
||||
CLK_GATE_UART1 = 64,
|
||||
CLK_GATE_UART2,
|
||||
CLK_GATE_UART3,
|
||||
CLK_GATE_TIMER1,
|
||||
CLK_GATE_TIMER2,
|
||||
CLK_GATE_TIMER3,
|
||||
CLK_GATE_GPIO1,
|
||||
CLK_GATE_GPIO2,
|
||||
CLK_GATE_GPIO3,
|
||||
CLK_GATE_GPIO4,
|
||||
CLK_GATE_GPIO5,
|
||||
CLK_GATE_GPIO6,
|
||||
CLK_GATE_I2C1,
|
||||
CLK_GATE_I2C2,
|
||||
CLK_GATE_I2C3,
|
||||
CLK_GATE_SPI0,
|
||||
CLK_GATE_SPI1,
|
||||
CLK_GATE_VIP_SLAVE = 82,
|
||||
CLK_GATE_WDT,
|
||||
CLK_GATE_SARADC,
|
||||
CLK_GATE_PWM,
|
||||
CLK_GATE_VIP_BUS,
|
||||
CLK_GATE_VIP_MATRIX,
|
||||
CLK_GATE_VIP,
|
||||
CLK_GATE_VIP_INPUT,
|
||||
CLK_GATE_JTAG,
|
||||
|
||||
/* CRU CLK GATE 3 CON */
|
||||
CLK_GATE_LCDC_AXI = 96,
|
||||
CLK_GATE_DDR_LCDC_AXI,
|
||||
CLK_GATE_LCDC_AHB,
|
||||
CLK_GATE_LCDC,
|
||||
CLK_GATE_IPP_AXI,
|
||||
CLK_GATE_IPP_AHB,
|
||||
CLK_GATE_EBOOK_AHB,
|
||||
CLK_GATE_EBOOK,
|
||||
CLK_GATE_DISPLAY_MATRIX_AXI,
|
||||
CLK_GATE_DISPLAY_MATRIX_AHB,
|
||||
CLK_GAET_VEPU_AXI,
|
||||
CLK_GATE_DDR_VEDU_AXI,
|
||||
CLK_GATE_VDPU_AXI,
|
||||
CLK_GATE_DDR_VDPU_AXI,
|
||||
CLK_GATE_GPU,
|
||||
CLK_GATE_GPU_AXI,
|
||||
CLK_GATE_DDR_GPU_AXI,
|
||||
CLK_GATE_GPU_AHB,
|
||||
CLK_GATE_VEPU_AHB,
|
||||
CLK_GATE_VDPU_AHB,
|
||||
CLK_GATE_CPU_VCODEC_AHB,
|
||||
CLK_GATE_CPU_DISPLAY_AHB,
|
||||
CLK_GATE_MAX
|
||||
}eCLK_GATE;
|
||||
|
||||
#define USB_OTG_INT_CH (1<<8)
|
||||
|
||||
//1<>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD>ṹ<EFBFBD><E1B9B9><EFBFBD><EFBFBD>
|
||||
#ifndef DRIVERS_INTC
|
||||
//INTC Registers
|
||||
typedef volatile struct tagINTC_STRUCT
|
||||
{
|
||||
uint32 IRQ_INTEN_L;
|
||||
uint32 IRQ_INTEN_H;
|
||||
uint32 IRQ_INTMASK_L;
|
||||
uint32 IRQ_INTMASK_H;
|
||||
uint32 IRQ_INTFORCE_L;
|
||||
uint32 IRQ_INTFORCE_H;
|
||||
uint32 IRQ_RAWSTATUS_L;
|
||||
uint32 IRQ_RAWSTATUS_H;
|
||||
uint32 IRQ_STATUS_L;
|
||||
uint32 IRQ_STATUS_H;
|
||||
uint32 IRQ_MASKSTATUS_L;
|
||||
uint32 IRQ_MASKSTATUS_H;
|
||||
uint32 IRQ_FINALSTATUS_L;
|
||||
uint32 IRQ_FINALSTATUS_H;
|
||||
uint32 RESERVED1[(0xc0-0x38)/4];
|
||||
uint32 FIQ_INTEN;
|
||||
uint32 FIQ_INTMASK;
|
||||
uint32 FIQ_INTFORCE;
|
||||
uint32 FIQ_RAWSTATUS;
|
||||
uint32 FIQ_STATUS;
|
||||
uint32 FIQ_FINALSTATUS;
|
||||
uint32 IRQ_PLEVEL;
|
||||
uint32 RESERVED2[(0xe8-0xdc)/4];
|
||||
uint32 IRQ_PN_OFFSET[40];
|
||||
uint32 RESERVED3[(0x3f8-0x188)/4];
|
||||
uint32 AHB_ICTL_COMP_VERSION;
|
||||
uint32 ICTL_COMP_TYPE;
|
||||
} INTC_REG, *pINTC_REG;
|
||||
//INTC Registers
|
||||
typedef volatile struct tagGICD_REG
|
||||
{
|
||||
uint32 ICDDCR ; //0x000
|
||||
uint32 ICDICTR ; //0x004
|
||||
uint32 ICDIIDR ; //0x008
|
||||
uint32 RESERVED0[29] ;
|
||||
uint32 ICDISR[4] ; // 0x080
|
||||
uint32 RESERVED1[28] ;
|
||||
uint32 ICDISER[4] ; // 0x100
|
||||
uint32 RESERVED2[28] ;
|
||||
uint32 ICDICER[4] ; //0x180
|
||||
uint32 RESERVED3[28] ;
|
||||
uint32 ICDISPR[4] ; //0x200
|
||||
uint32 RESERVED4[28] ;
|
||||
uint32 ICDICPR[4] ; //0x280
|
||||
uint32 RESERVED5[28] ;
|
||||
uint32 ICDIABR[4] ; //0x300
|
||||
uint32 RESERVED6[60] ;
|
||||
uint32 ICDIPR_SGI[4] ; // 0x400
|
||||
uint32 ICDIPR_PPI[4] ; // 0x410
|
||||
uint32 ICDIPR_SPI[18] ; //0x420
|
||||
uint32 RESERVED57[486] ;
|
||||
uint32 ICDICFR[7] ; //0xc00
|
||||
uint32 RESERVED8[185] ;
|
||||
uint32 ICDSGIR ; //0xf00
|
||||
}GICD_REG, *pGICD_REG;
|
||||
typedef volatile struct tagGICC_REG
|
||||
{
|
||||
uint32 ICCICR ; //0x00
|
||||
uint32 ICCPMR ; //0x04
|
||||
uint32 ICCBPR ; //0x08
|
||||
uint32 ICCIAR ; //0x0c
|
||||
uint32 ICCEOIR ; //0x10
|
||||
uint32 ICCRPR ; //0x14
|
||||
uint32 ICCHPIR ; //0x18
|
||||
uint32 ICCABPR ; //0x1c
|
||||
uint32 RESERVED0[55];
|
||||
uint32 ICCIIDR ; //0xfc
|
||||
}GICC_REG, *pGICC_REG;
|
||||
|
||||
//SCU Registers
|
||||
typedef volatile struct tagSCU_STRUCT
|
||||
{
|
||||
uint32 SCU_APLL_CON;
|
||||
uint32 SCU_DPLL_CON;
|
||||
uint32 SCU_CPLL_CON;
|
||||
uint32 SCU_MODE_CON;
|
||||
uint32 SCU_PMU_CON;
|
||||
uint32 SCU_CLKSEL0_CON;
|
||||
uint32 SCU_CLESEL1_CON;
|
||||
uint32 SCU_CLKGATE0_CON;
|
||||
uint32 SCU_CLKGATE1_CON;
|
||||
uint32 SCU_CLKGATE2_CON;
|
||||
uint32 SCU_SOFTRST_CON;
|
||||
uint32 SCU_CHIPCFG_CON;
|
||||
uint32 SCU_CPUPD;
|
||||
} SCU_REG, *pSCU_REG;
|
||||
|
||||
//REG FILE registers
|
||||
typedef volatile struct tagREG_FILE
|
||||
{
|
||||
uint32 CPU_APB_REG0;
|
||||
uint32 CPU_APB_REG1;
|
||||
uint32 CPU_APB_REG2;
|
||||
uint32 CPU_APB_REG3;
|
||||
uint32 CPU_APB_REG4;
|
||||
uint32 CPU_APB_REG5;
|
||||
uint32 CPU_APB_REG6;
|
||||
uint32 CPU_APB_REG7;
|
||||
uint32 IOMUX_A_CON;
|
||||
uint32 IOMUX_B_CON;
|
||||
uint32 GPIO0_AB_PU_CON;
|
||||
uint32 GPIO0_CD_PU_CON;
|
||||
uint32 GPIO1_AB_PU_CON;
|
||||
uint32 GPIO1_CD_PU_CON;
|
||||
uint32 OTGPHY_CON0;
|
||||
uint32 OTGPHY_CON1;
|
||||
} REG_FILE, *pREG_FILE;
|
||||
|
||||
/********************************************************************
|
||||
** <20>ṹ<EFBFBD><E1B9B9><EFBFBD><EFBFBD> *
|
||||
********************************************************************/
|
||||
//GRF Registers
|
||||
typedef volatile struct tagGRF_REG
|
||||
{
|
||||
uint32 CPU_APB_REG0;
|
||||
uint32 CPU_APB_REG1;
|
||||
uint32 CPU_APB_REG2;
|
||||
uint32 CPU_APB_REG3;
|
||||
uint32 CPU_APB_REG4;
|
||||
uint32 CPU_APB_REG5;
|
||||
uint32 CPU_APB_REG6;
|
||||
uint32 CPU_APB_REG7;
|
||||
uint32 IOMUX_A_CON;
|
||||
uint32 IOMUX_B_CON;
|
||||
uint32 GPIO0_AB_PU_CON;
|
||||
uint32 GPIO0_CD_PU_CON;
|
||||
uint32 GPIO1_AB_PU_CON;
|
||||
uint32 GPIO1_CD_PU_CON;
|
||||
uint32 OTGPHY_CON0;
|
||||
uint32 OTGPHY_CON1;
|
||||
}GRF_REG, *pGRF_REG,*pAPB_REG;
|
||||
|
||||
//GPIO Registers
|
||||
typedef volatile struct tagGPIO_STRUCT
|
||||
{
|
||||
uint32 GPIO_SWPORTA_DR;
|
||||
uint32 GPIO_SWPORTA_DDR;
|
||||
uint32 RESERVED1;
|
||||
uint32 GPIO_SWPORTB_DR;
|
||||
uint32 GPIO_SWPORTB_DDR;
|
||||
uint32 RESERVED2;
|
||||
uint32 GPIO_SWPORTC_DR;
|
||||
uint32 GPIO_SWPORTC_DDR;
|
||||
uint32 RESERVED3;
|
||||
uint32 GPIO_SWPORTD_DR;
|
||||
uint32 GPIO_SWPORTD_DDR;
|
||||
uint32 RESERVED4;
|
||||
uint32 GPIO_INTEN;
|
||||
uint32 GPIO_INTMASK;
|
||||
uint32 GPIO_INTTYPE_LEVEL;
|
||||
uint32 GPIO_INT_POLARITY;
|
||||
uint32 GPIO_INT_STATUS;
|
||||
uint32 GPIO_INT_RAWSTATUS;
|
||||
uint32 GPIO_DEBOUNCE;
|
||||
uint32 GPIO_PORTS_EOI;
|
||||
uint32 GPIO_EXT_PORTA;
|
||||
uint32 GPIO_EXT_PORTB;
|
||||
uint32 GPIO_EXT_PORTC;
|
||||
uint32 GPIO_EXT_PORTD;
|
||||
uint32 GPIO_LS_SYNC;
|
||||
}GPIO_REG,*pGPIO_REG;
|
||||
//SCU Registers
|
||||
typedef volatile struct tagCRU_REG
|
||||
{
|
||||
uint32 CRU_APLL_CON;//[3];//0:arm 1:ddr 2:codec
|
||||
uint32 CRU_DPLL_CON;
|
||||
uint32 CRU_CPLL_CON;
|
||||
uint32 CRU_PPLL_CON;
|
||||
uint32 CRU_MODE_CON;
|
||||
uint32 CRU_CLKSEL0_CON;
|
||||
uint32 CRU_CLKSEL1_CON;
|
||||
uint32 CRU_CLKSEL2_CON;
|
||||
uint32 CRU_CLKSEL3_CON;
|
||||
uint32 CRU_CLKSEL4_CON;
|
||||
uint32 CRU_CLKSEL5_CON;
|
||||
uint32 CRU_CLKSEL6_CON;
|
||||
uint32 CRU_CLKSEL7_CON;
|
||||
uint32 CRU_CLKSEL8_CON;
|
||||
uint32 CRU_CLKSEL9_CON;
|
||||
uint32 CRU_CLKSEL10_CON;
|
||||
uint32 CRU_CLKSEL11_CON;
|
||||
uint32 CRU_CLKSEL12_CON;
|
||||
uint32 CRU_CLKSEL13_CON;
|
||||
uint32 CRU_CLKSEL14_CON;
|
||||
uint32 CRU_CLKSEL15_CON;
|
||||
uint32 CRU_CLKSEL16_CON;
|
||||
uint32 CRU_CLKSEL17_CON;
|
||||
uint32 CRU_CLKGATE0_CON;
|
||||
uint32 CRU_CLKGATE1_CON;
|
||||
uint32 CRU_CLKGATE2_CON;
|
||||
uint32 CRU_CLKGATE3_CON;
|
||||
uint32 CRU_SOFTRST0_CON;
|
||||
uint32 CRU_SOFTRST1_CON;
|
||||
uint32 CRU_SOFTRST2_CON;
|
||||
}CRU_REG,*pCRU_REG;
|
||||
|
||||
//SDMMC0
|
||||
typedef enum
|
||||
{
|
||||
IOMUX_SDMMC_1BIT = 0,
|
||||
IOMUX_SDMMC_4BIT, //default
|
||||
IOMUX_SDMMC_8BIT,
|
||||
IOMUX_SDMMC_OTHER
|
||||
}eIOMUX_SDMMC;
|
||||
typedef enum _IRQ_NUM
|
||||
{
|
||||
INT_SGI0 ,
|
||||
INT_SGI1 ,
|
||||
INT_SGI2 ,
|
||||
INT_SGI3 ,
|
||||
INT_SGI4 ,
|
||||
INT_SGI5 ,
|
||||
INT_SGI6 ,
|
||||
INT_SGI7 ,
|
||||
INT_SGI8 ,
|
||||
INT_SGI9 ,
|
||||
INT_SGI10 ,
|
||||
INT_SGI11 ,
|
||||
INT_SGI12 ,
|
||||
INT_SGI13 ,
|
||||
INT_SGI14 ,
|
||||
INT_SGI15 ,
|
||||
INT_PPI0 ,
|
||||
INT_PPI1 ,
|
||||
INT_PPI2 ,
|
||||
INT_PPI3 ,
|
||||
INT_PPI4 ,
|
||||
INT_PPI5 ,
|
||||
INT_PPI6 ,
|
||||
INT_PPI7 ,
|
||||
INT_PPI8 ,
|
||||
INT_PPI9 ,
|
||||
INT_PPI10 ,
|
||||
INT_PPI11 ,
|
||||
INT_PPI12 ,
|
||||
INT_PPI13 ,
|
||||
INT_PPI14 ,
|
||||
INT_PPI15 ,
|
||||
|
||||
#endif
|
||||
INT_DMAC0_0 ,
|
||||
INT_DMAC0_1 ,
|
||||
INT_DMAC0_2 ,
|
||||
INT_DMAC0_3 ,
|
||||
INT_DMAC2_0 ,
|
||||
INT_DMAC2_1 ,
|
||||
INT_DMAC2_2 ,
|
||||
INT_DMAC2_3 ,
|
||||
INT_DMAC2_4 ,
|
||||
INT_GPU ,
|
||||
INT_VEPU ,
|
||||
INT_VDPU ,
|
||||
INT_VIP ,
|
||||
INT_LCDC ,
|
||||
INT_IPP ,
|
||||
INT_EBC ,
|
||||
INT_USB_OTG0 ,
|
||||
INT_USB_OTG1 ,
|
||||
INT_USB_Host ,
|
||||
INT_MAC ,
|
||||
INT_HIF0 ,
|
||||
INT_HIF1 ,
|
||||
INT_HSADC_TSI ,
|
||||
INT_SDMMC ,
|
||||
INT_SDIO ,
|
||||
INT_eMMC ,
|
||||
INT_SARADC ,
|
||||
INT_NandC ,
|
||||
INT_NandCRDY ,
|
||||
INT_SMC ,
|
||||
INT_PID_FILTER ,
|
||||
INT_I2S_PCM_8CH ,
|
||||
INT_I2S_PCM_2CH ,
|
||||
INT_SPDIF ,
|
||||
INT_UART0 ,
|
||||
INT_UART1 ,
|
||||
INT_UART2 ,
|
||||
INT_UART3 ,
|
||||
INT_SPI0 ,
|
||||
INT_SPI1 ,
|
||||
INT_I2C0 ,
|
||||
INT_I2C1 ,
|
||||
INT_I2C2 ,
|
||||
INT_I2C3 ,
|
||||
INT_TIMER0 ,
|
||||
INT_TIMER1 ,
|
||||
INT_TIMER2 ,
|
||||
INT_TIMER3 ,
|
||||
INT_PWM0 ,
|
||||
INT_PWM1 ,
|
||||
INT_PWM2 ,
|
||||
INT_PWM3 ,
|
||||
INT_WDT ,
|
||||
INT_RTC ,
|
||||
INT_PMU ,
|
||||
INT_GPIO0 ,
|
||||
INT_GPIO1 ,
|
||||
INT_GPIO2 ,
|
||||
INT_GPIO3 ,
|
||||
INT_GPIO4 ,
|
||||
INT_GPIO5 ,
|
||||
INT_GPIO6 ,
|
||||
INT_USB_AHB_ARB ,
|
||||
INT_PERI_AHB_ARB,
|
||||
INT_A8IRQ0 ,
|
||||
INT_A8IRQ1 ,
|
||||
INT_A8IRQ2 ,
|
||||
INT_A8IRQ3 ,
|
||||
INT_MAXNUM
|
||||
}eINT_NUM;
|
||||
|
||||
//1ȫ<31>ֱ<EFBFBD><D6B1><EFBFBD>
|
||||
#undef EXT
|
||||
#ifdef IN_EPPHAL
|
||||
#define EXT
|
||||
#else
|
||||
#define EXT extern
|
||||
#endif
|
||||
typedef enum _CRU_RST
|
||||
{
|
||||
//cru_rst_con0
|
||||
CRU_RST_ARMCORE = 0,
|
||||
CRU_RST_CPUSUBSYS_INT1AXI,
|
||||
CRU_RST_CPUSUBSYS_INT1AHB,
|
||||
CRU_RST_CPUSUBSYS_INT1APB,
|
||||
CRU_RST_CPUSUBSYS_INT1ATB,
|
||||
CRU_RST_CPUSUBSYS_INT2,
|
||||
CRU_RST_DMA0,
|
||||
CRU_RST_DMA1,
|
||||
CRU_RST_GIC,
|
||||
CRU_RST_INMEM,
|
||||
CRU_RST_TZPC=11,
|
||||
CRU_RST_ROM,
|
||||
CRU_RST_I2S0,
|
||||
CRU_RST_I2S1,
|
||||
CRU_RST_SPDIF,
|
||||
CRU_RST_UART0,
|
||||
CRU_RST_RTC,
|
||||
CRU_RST_DDRPHY,
|
||||
CRU_RST_DDRDLL_B0,
|
||||
CRU_RST_DDRDLL_B1,
|
||||
CRU_RST_DDRDLL_B2,
|
||||
CRU_RST_DDRDLL_B3,
|
||||
CRU_RST_DDRDLL_CMD,
|
||||
CRU_RST_DDR_CON,
|
||||
CRU_RST_ARMCORE_DEBUG,
|
||||
CRU_RST_DAP_DBG,
|
||||
CRU_RST_CPU_VODEC_A2A,
|
||||
CRU_RST_CPU_DISPLAY_A2A,
|
||||
CRU_RST_DAP_SYS,
|
||||
|
||||
//1<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ԭ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// cru_softrst1_con
|
||||
CRU_RST_PERIPH_INT1_AXI=32,
|
||||
CRU_RST_PERIPH_INT1_AHB,
|
||||
CRU_RST_PERIPH_INT1_APB,
|
||||
CRU_RST_PERIPH_EMEM=36,
|
||||
CRU_RST_PERIPH_USB,
|
||||
CRU_RST_DMA2,
|
||||
CRU_RST_MAC,
|
||||
CRU_RST_HIF,
|
||||
CRU_RST_NANDC,
|
||||
CRU_RST_SMC,
|
||||
CRU_RST_RESERVED1,
|
||||
CRU_RST_LSADC,
|
||||
CRU_RST_SDMMC0,
|
||||
CRU_RST_SDMMC1,
|
||||
CRU_RST_EMMC,
|
||||
CRU_RST_USBOTG0_AHB,
|
||||
CRU_RST_USBPHY0,
|
||||
CRU_RST_USBOTG0_CON,
|
||||
CRU_RST_USBOTG1_AHB,
|
||||
CRU_RST_USBPHY1,
|
||||
CRU_RST_USBOTG1_CON,
|
||||
CRU_RST_UHOST,
|
||||
CRU_RST_VIP,
|
||||
CRU_RST_VIP_AHB,
|
||||
CRU_RST_SPI0,
|
||||
CRU_RST_SPI1,
|
||||
CRU_RST_SARADC,
|
||||
CRU_RST_UART1,
|
||||
CRU_RST_UART2,
|
||||
CRU_RST_UART3,
|
||||
CRU_RST_PWM,
|
||||
|
||||
//CRU_SOFTRST2_CON
|
||||
CRU_RST_DISPLAY_AXI=64,
|
||||
CRU_RST_DISPLAY_AHB,
|
||||
CRU_RST_LCDC,
|
||||
CRU_RST_IPP,
|
||||
CRU_RST_EBOOK,
|
||||
CRU_RST_RESERVED2,
|
||||
CRU_RST_RESERVED3,
|
||||
CRU_RST_GPU,
|
||||
CRU_RST_DDR_REG,
|
||||
CRU_RST_DDR_CPU,
|
||||
CRU_RST_PERIPH_CPU_AXI,
|
||||
CRU_RST_DDR_PERIPH,
|
||||
CRU_RST_DDR_LCDC,
|
||||
CRU_RST_RESERVED4,
|
||||
CRU_RST_RESERVED5,
|
||||
CRU_RST_DDR_VCODEC,
|
||||
CRU_RST_DDR_GPU,
|
||||
CRU_RST_PID_FILTER,
|
||||
CRU_RST_VCODEC_AXI,
|
||||
CRU_RST_VCODEC_AHB,
|
||||
CRU_RST_TIMER0,
|
||||
CRU_RST_TIMER1,
|
||||
CRU_RST_TIMER2,
|
||||
CRU_RST_TIMER3,
|
||||
|
||||
CRU_RST_MAX
|
||||
}eCRU_RST;
|
||||
|
||||
//GRF Registers
|
||||
typedef volatile struct tagGRF_REG
|
||||
{
|
||||
uint32 GRF_GPIO0_DIR;
|
||||
uint32 GRF_GPIO1_DIR;
|
||||
uint32 GRF_GPIO2_DIR;
|
||||
uint32 GRF_GPIO3_DIR;
|
||||
uint32 GRF_GPIO4_DIR;
|
||||
uint32 GRF_GPIO5_DIR;
|
||||
uint32 GRF_GPIO0_DO;
|
||||
uint32 GRF_GPIO1_DO;
|
||||
uint32 GRF_GPIO2_DO;
|
||||
uint32 GRF_GPIO3_DO;
|
||||
uint32 GRF_GPIO4_DO;
|
||||
uint32 GRF_GPIO5_DO;
|
||||
uint32 GRF_GPIO0_EN;
|
||||
uint32 GRF_GPIO1_EN;
|
||||
uint32 GRF_GPIO2_EN;
|
||||
uint32 GRF_GPIO3_EN;
|
||||
uint32 GRF_GPIO4_EN;
|
||||
uint32 GRF_GPIO5_EN;
|
||||
uint32 GRF_GPIO0L_IOMUX;
|
||||
uint32 GRF_GPIO0H_IOMUX;
|
||||
uint32 GRF_GPIO1L_IOMUX;
|
||||
uint32 GRF_GPIO1H_IOMUX;
|
||||
uint32 GRF_GPIO2L_IOMUX;
|
||||
uint32 GRF_GPIO2H_IOMUX;
|
||||
uint32 GRF_GPIO3L_IOMUX;
|
||||
uint32 GRF_GPIO3H_IOMUX;
|
||||
uint32 GRF_GPIO4L_IOMUX;
|
||||
uint32 GRF_GPIO4H_IOMUX;
|
||||
uint32 GRF_GPIO5L_IOMUX;
|
||||
uint32 GRF_GPIO5H_IOMUX;
|
||||
uint32 GRF_GPIO0_PULL1;
|
||||
uint32 GRF_GPIO1_PULL1;
|
||||
uint32 GRF_GPIO2_PULL1;
|
||||
uint32 GRF_GPIO3_PULL1;
|
||||
uint32 GRF_GPIO4_PULL1;
|
||||
uint32 GRF_GPIO5_PULL1;
|
||||
uint32 GRF_GPIO6_PULL1;
|
||||
uint32 GRF_UOC0_CON0;
|
||||
uint32 GRF_UOC1_CON0;
|
||||
uint32 GRF_USB_CON;
|
||||
uint32 GRF_CPU_CON0;
|
||||
uint32 GRF_CPU_CON1;
|
||||
uint32 GRF_CPU_STATUS;
|
||||
uint32 GRF_MEM_CON;
|
||||
uint32 GRF_MEM_STATUS0;
|
||||
uint32 GRF_MEM_STATUS1;
|
||||
uint32 GRF_MEM_STATUS2;
|
||||
uint32 GRF_SOC_CON0;
|
||||
uint32 GRF_SOC_CON1;
|
||||
uint32 GRF_SOC_CON2;
|
||||
uint32 GRF_SOC_CON3;
|
||||
uint32 GRF_SOC_CON4;
|
||||
uint32 GRF_OS_REG0;
|
||||
uint32 GRF_OS_REG1;
|
||||
uint32 GRF_OS_REG2;
|
||||
uint32 GRF_OS_REG3;
|
||||
|
||||
}GRF_REG, *pGRF_REG,*pAPB_REG, *pREG_FILE;
|
||||
|
||||
//TIMER Registers
|
||||
typedef volatile struct tagTIMER_STRUCT
|
||||
{
|
||||
uint32 TIMER_LOAD_COUNT;
|
||||
uint32 TIMER_CURR_VALUE;
|
||||
uint32 TIMER_CTRL_REG;
|
||||
uint32 TIMER_EOI;
|
||||
uint32 TIMER_INT_STATUS;
|
||||
}TIMER_REG,*pTIMER_REG;
|
||||
|
||||
typedef volatile struct tagPMU_REG
|
||||
{
|
||||
uint32 PMU_WAKEUP_EN0;
|
||||
uint32 PMU_WAKEUP_EN1;
|
||||
uint32 PMU_WAKEUP_EN2;
|
||||
uint32 reserved1;
|
||||
uint32 PMU_PG_CON;
|
||||
uint32 PMU_MISC_CON;
|
||||
uint32 PMU_PLL_CNT;
|
||||
uint32 PMU_PD_ST;
|
||||
uint32 PMU_INT_ST;
|
||||
}PMU_REG,*pPMU_REG;
|
||||
|
||||
typedef struct tagSCU_CLK_INFO
|
||||
{
|
||||
uint32 armFreq; //ARM PLL FREQ
|
||||
uint32 dspFreq; //DSP PLL FREQ
|
||||
uint32 AuxFreq; //AUX PLL FREQ
|
||||
uint32 ahbDiv;
|
||||
uint32 apbDiv;
|
||||
uint32 armFreqLast;
|
||||
}SCU_CLK_INFO,*pSCU_CLK_INFO;
|
||||
|
||||
#define g_cruReg ((pCRU_REG)RK29_CRU_BASE)
|
||||
|
||||
extern void EnableIRQ(void);
|
||||
extern void DisableIRQ(void);
|
||||
extern void EnableOtgIntr(void);
|
||||
extern void DisableOtgIntr(void);
|
||||
extern void InterruptInit(void);
|
||||
#endif
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -19,10 +19,17 @@ Revision: 1.00
|
||||
#include <linux/string.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/delay.h>
|
||||
//#include <asm/arch-rockchip/hardware.h>
|
||||
#include <linux/irq.h>
|
||||
#include <mach/board.h>
|
||||
#include <mach/gpio.h>
|
||||
#include <asm/dma.h>
|
||||
#include <mach/rk29-dma-pl330.h>
|
||||
#include "typedef.h"
|
||||
#include <mach/rk29_iomap.h>
|
||||
#include <mach/iomux.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include "epphal.h"
|
||||
|
||||
//#include "epphal.h"
|
||||
#ifndef TRUE
|
||||
#define TRUE 1
|
||||
|
||||
@@ -26,6 +26,7 @@ extern int rknand_queue_read(int Index, int nSec, void *buf);
|
||||
extern int rknand_queue_write(int Index, int nSec, void *buf,int mode);
|
||||
extern int rknand_buffer_init(void);
|
||||
extern void rknand_buffer_shutdown(void);
|
||||
extern void rknand_buffer_sync(void);
|
||||
|
||||
#define DRIVER_NAME "rk29xxnand"
|
||||
const char rknand_base_version[] = "rknand_base.c version: 4.20 20101118";
|
||||
@@ -268,7 +269,7 @@ static int rk28xxnand_read(struct mtd_info *mtd, loff_t from, size_t len,
|
||||
if(sector)
|
||||
{
|
||||
{
|
||||
ret = FtlRead(2,LBA, sector, buf);
|
||||
ret = NandRead(LBA, sector, buf);
|
||||
}
|
||||
}
|
||||
rknand_release_device();
|
||||
@@ -290,11 +291,11 @@ static int rk28xxnand_write(struct mtd_info *mtd, loff_t from, size_t len,
|
||||
if(LBA < SysImageWriteEndAdd)//0x4E000)
|
||||
{
|
||||
printk(">>> FtlWriteImage: LBA=0x%08X sector=%d\n",LBA, sector);
|
||||
ret = FtlWriteImage(LBA&0xFFFFFFE0, sector, (void *)buf);// LBA align to 32
|
||||
ret = NandWriteImage(LBA&0xFFFFFFE0, sector, (void *)buf);// LBA align to 32
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = FtlWrite(2,LBA, sector, (void *)buf);
|
||||
ret = NandWrite(LBA, sector, (void *)buf);
|
||||
}
|
||||
}
|
||||
rknand_release_device();
|
||||
@@ -356,6 +357,9 @@ static int rk28xxnand_erase(struct mtd_info *mtd, struct erase_info *instr)
|
||||
static void rk28xxnand_sync(struct mtd_info *mtd)
|
||||
{
|
||||
NAND_DEBUG(NAND_DEBUG_LEVEL0,"rk28xxnand_sync: \n");
|
||||
#ifdef CONFIG_MTD_RKNAND_BUFFER
|
||||
rknand_buffer_sync();
|
||||
#endif
|
||||
}
|
||||
|
||||
static int rk28xxnand_init(struct rknand_info *nand_info)
|
||||
@@ -371,17 +375,13 @@ static int rk28xxnand_init(struct rknand_info *nand_info)
|
||||
rknand->pFlashCallBack = NULL;
|
||||
init_waitqueue_head(&rknand->wq);
|
||||
NAND_DEBUG(NAND_DEBUG_LEVEL0,"FTLInit ...: \n");
|
||||
#ifdef PAGE_REMAP
|
||||
if(FTLInit())
|
||||
#else
|
||||
if(FTLInit_WithoutPageRemap())
|
||||
#endif
|
||||
if(NandInit())
|
||||
{
|
||||
NAND_DEBUG(NAND_DEBUG_LEVEL0,"FTLInit Error: \n");
|
||||
return -ENXIO;
|
||||
}
|
||||
NAND_DEBUG(NAND_DEBUG_LEVEL0,"FTLInit OK: \n");
|
||||
mtd->size = (uint64_t)FtlGetCapacity(0xFF)*0x200;
|
||||
mtd->size = (uint64_t)NandGetCapacity()*0x200;
|
||||
//readflash modify rk28_partition_info
|
||||
|
||||
NAND_DEBUG(NAND_DEBUG_LEVEL0,"mtd->size: 0x%012llx\n",mtd->size);
|
||||
@@ -550,7 +550,7 @@ static int rknand_probe(struct platform_device *pdev)
|
||||
}
|
||||
}
|
||||
|
||||
FtlSetSysProtAddr(SysImageWriteEndAdd);
|
||||
NandSetSysProtAddr(SysImageWriteEndAdd);
|
||||
dev_set_drvdata(&pdev->dev, nand_info);
|
||||
|
||||
return 0;
|
||||
@@ -601,7 +601,8 @@ static int rknand_resume(struct platform_device *pdev)
|
||||
void rknand_shutdown(struct platform_device *pdev)
|
||||
{
|
||||
#ifdef CONFIG_MTD_RKNAND_BUFFER
|
||||
NAND_DEBUG(NAND_DEBUG_LEVEL0,"rknand_shutdown...\n");
|
||||
//NAND_DEBUG(NAND_DEBUG_LEVEL0,"rknand_shutdown...\n");
|
||||
printk("rknand_shutdown...\n");
|
||||
gpNandInfo->rknand.rknand_schedule_enable = 0;
|
||||
rknand_buffer_shutdown();
|
||||
#else
|
||||
@@ -611,12 +612,12 @@ void rknand_shutdown(struct platform_device *pdev)
|
||||
if (nand_info->state == FL_READY)
|
||||
{
|
||||
nand_info->state = FL_UNVALID;
|
||||
FtlClose();
|
||||
NandDeInit();
|
||||
rknand_release_device();
|
||||
}
|
||||
else
|
||||
{
|
||||
nand_info->pFlashCallBack = FtlClose;
|
||||
nand_info->pFlashCallBack = NandDeInit;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
@@ -626,7 +627,7 @@ static struct platform_driver rknand_driver = {
|
||||
//.remove = rknand_remove,
|
||||
.suspend = rknand_suspend,
|
||||
.resume = rknand_resume,
|
||||
// .shutdown = rknand_shutdown, // FIXME: temporarily disable by huangtao
|
||||
.shutdown = rknand_shutdown,
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
@@ -705,12 +706,12 @@ static int rknand_sys_shutdown(struct sys_device *dev)
|
||||
{
|
||||
//rknand_get_device(FL_UNVALID);
|
||||
nand_info->state = FL_UNVALID;
|
||||
FtlClose();
|
||||
NandDeInit();
|
||||
rknand_release_device();
|
||||
}
|
||||
else
|
||||
{//flash not ready,use call back
|
||||
nand_info->pFlashCallBack = FtlClose;
|
||||
nand_info->pFlashCallBack = NandDeInit;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
469
drivers/mtd/rknand/rknand_buffer.uu
Executable file → Normal file
469
drivers/mtd/rknand/rknand_buffer.uu
Executable file → Normal file
@@ -1,5 +1,5 @@
|
||||
begin 644 rknand_buffer.o
|
||||
M?T5,1@$!`0````````````$`*``!``````````````!$(@``````!30`````
|
||||
M?T5,1@$!`0````````````$`*``!``````````````!($@``````!30`````
|
||||
M`"@`$``-`"`PG^4"%:#C'""?Y1@0@^4!`(+@"""#Y0P`@^40((/E%!"#Y1[_
|
||||
M+^'X_W\``````#0PG^4$`)#E$""3Y0$`@.`"`%#A``!B@!@`@X4,P).5"!"3
|
||||
ME0P@8I`8((.5`B!AD`(`@)`4`(/E'O\OX?C_?P!<,)_E&!"3Y0``4>$(``"Z
|
||||
@@ -11,284 +11,193 @@ MH""?Y0!0H.'^___KF$"?Y9@0G^44()3E`&"%X`8`H.'^___K&""4Y800G^4`
|
||||
M8(;@!@"@X?[__^L,$)3E"""4Y10PE.4!(&+@:!"?Y0(@8^``8(;@!@"@X?[_
|
||||
M_^LT()3E5!"?Y0!@AN`&`*#A_O__ZR@@E.5$$)_E`&"&X`8`H.'^___K0""4
|
||||
MY300G^4`0(;@!`"@X?[__^L``(3@``!EX'"`O>@``````````/C_?P`$````
|
||||
M%@```"D```!`````50```&D````,`)_E`Q"@XP$@H.,`,*#C_O__ZA0`@``0
|
||||
M0"WI`,"@X0``D.4"`%#C"@``"A8`4.,.```*`0!0XP``X!,0@+T8!#"<Y0(`
|
||||
MH.,,$)SE$""<Y?[__^L#``#J!#"<Y0P0G.40()SE_O__ZP``H.,0@+WH!""<
|
||||
MY0P`G.40$)SE_O__ZP``H.,0@+WH\$\MZ1303>(-(*#A$Q"@XW]=PN,_4,7C
|
||||
M#`"5Y?[__^M8!)_E_O__ZX``#/$$,)7E`3"#X@0PA>4`,*#C$R"@XP0PC>4#
|
||||
M<*#A"""-Y?^1`.,L1)_E`6"@XRBTG^4"@*#C)*2?Y:T``.HT,)3E`0!3XR(`
|
||||
M`,HH,)3E``!3XQ\``!H$,)WE*R$`XP(`4^$;``#*-""4Y0PPE>4,((WE`&"#
|
||||
MY8``"/$$,)7E`3!#X@0PA>4`,)7E`@`3XP````K^___KK/__ZPPPG>4!`%/C
|
||||
M!0``&@0@G>5D`*#C`2""X@0@C>7^___K````ZO[__^N```SQ!#"5Y0$P@^($
|
||||
M,(7EAP``ZH``"/$$,)7E`3!#X@0PA>4`,)7E`@`3XP````K^___K%#"4Y0L`
|
||||
M4^$"``#:0#"4Y?\`4^,)``#*"#"=Y0``4^,&```*##"5Y0"`@^4`$*#C#`"5
|
||||
MY?[__^L`(*#C"""-Y10PE.4*`%/A#P``VD`PE.4)`%/A#```V@@PG>4``%/C
|
||||
M!```&@P`E>43$*#C_O__ZQ,@H.,(((WE=O__ZPPPE>4`8(/E'@"@X_[__^O<
|
||||
M`I_E_O__ZX``#/$$,)7E`3"#X@0PA>4H,)3E``!3XS(``!HX,)3E-!"4Y10@
|
||||
MD^4!$$'B)#"$Y300A.4X((3E@``(\00@E>4!($+B!""%Y0`@E>4"`!+C`@``
|
||||
M"@`PC>7^___K`#"=Y0,`H.$`,(WE6___ZX``#/$$()7E`2""X@0@A>5`()3E
|
||||
M`#"=Y0``4N,D<(3E2""4%40PA`44,((52#"$Y11P@^5`$)3E$""4Y0$0@>)`
|
||||
M$(3E$!"3Y00PD^6!-(/@`@!3X0,P8H`8,(2%#`"4E0@0E)4`(&*0&""$E0(@
|
||||
M89`",(.0%#"$Y1L``.HL,)3E*!"4Y10@D^4!$$'B*!"$Y2P@A.6```CQ!""5
|
||||
MY0$@0N($((7E`""5Y0(`$N,"```*`#"-Y?[__^L`,)WE`P"@X0`PC>4I___K
|
||||
M@``,\00@E>4!((+B!""%Y0`PG>48`)/E``!0XP````K^___K&?__ZW@!G^7^
|
||||
M___K`#"@XP0PC>7^___K``!0XT[__PJ```CQ#2"@X7\]PN,_,,/C!""3Y0$@
|
||||
M0N($((/E`#"3Y0(`$^,````*_O__ZS0!G^7^___K2P^@X_[__^L`$*#A'`&?
|
||||
MY?[__^L``%#C/0``"H``#/$-(*#A?SW"XS\PP^,$()/E`2""X@0@@^7D0)_E
|
||||
M`&"@XR(``.HX4)3E-""4Y04`H.$4,)7E`2!"XB10A.4T((3E.#"$Y?'^_^M`
|
||||
M,)3E)&"$Y0``4^-$4(0%2#"4%110@Q5(4(3E%&"%Y4`PE.40()3E`3"#XD`P
|
||||
MA.40$)7E!#"5Y8$T@^`"`%/A`Q!BX!@0A(4,`)25"!"4E100A(4`(&*0&""$
|
||||
ME0(@89`",(.0%#"$E30PE.4``%/CV?__&O[__^N```CQ#2"@X7\]PN,_,,/C
|
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end
|
||||
|
||||
Reference in New Issue
Block a user