diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.yaml b/Documentation/devicetree/bindings/spi/spi-rockchip.yaml index e76652b122c9..34f9d13de332 100644 --- a/Documentation/devicetree/bindings/spi/spi-rockchip.yaml +++ b/Documentation/devicetree/bindings/spi/spi-rockchip.yaml @@ -100,6 +100,15 @@ properties: description: Add this property to set the transmission method as CPU polling. type: boolean + rockchip,cs-inactive-disable: + description: Add this property to disable the cs inactive interrupt for spi + slave. + type: boolean + + ready-gpios: + description: GPIO spec for the spi slave ready signal. + maxItems: 1 + required: - compatible - reg diff --git a/arch/arm/configs/rockchip_linux_defconfig b/arch/arm/configs/rockchip_linux_defconfig index 7e1e923648b8..3c22896cd8dd 100644 --- a/arch/arm/configs/rockchip_linux_defconfig +++ b/arch/arm/configs/rockchip_linux_defconfig @@ -168,7 +168,6 @@ CONFIG_MD=y CONFIG_BLK_DEV_DM=y CONFIG_DM_CRYPT=y CONFIG_DM_THIN_PROVISIONING=y -CONFIG_DM_VERITY=y CONFIG_NETDEVICES=y CONFIG_TUN=y CONFIG_VETH=y @@ -414,11 +413,6 @@ CONFIG_DMADEVICES=y CONFIG_PL330_DMA=y CONFIG_STAGING=y CONFIG_ASHMEM=y -CONFIG_FIQ_DEBUGGER=y -CONFIG_FIQ_DEBUGGER_NO_SLEEP=y -CONFIG_FIQ_DEBUGGER_CONSOLE=y -CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y -CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y CONFIG_COMMON_CLK_RK808=y CONFIG_ROCKCHIP_IOMMU=y CONFIG_CPU_RK312X=y @@ -437,6 +431,11 @@ CONFIG_ROCKCHIP_PVTM=y CONFIG_ROCKCHIP_SUSPEND_MODE=y CONFIG_ROCKCHIP_SYSTEM_MONITOR=y CONFIG_ROCKCHIP_VENDOR_STORAGE_UPDATE_LOADER=y +CONFIG_FIQ_DEBUGGER=y +CONFIG_FIQ_DEBUGGER_NO_SLEEP=y +CONFIG_FIQ_DEBUGGER_CONSOLE=y +CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y +CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y CONFIG_PM_DEVFREQ=y CONFIG_DEVFREQ_GOV_PERFORMANCE=y CONFIG_DEVFREQ_GOV_POWERSAVE=y diff --git a/arch/arm/configs/rv1106-tee.config b/arch/arm/configs/rv1106-tee.config index 430a40d2ba4e..59472f91fcb3 100644 --- a/arch/arm/configs/rv1106-tee.config +++ b/arch/arm/configs/rv1106-tee.config @@ -1,13 +1,117 @@ CONFIG_ARM_PSCI=y +CONFIG_CRYPTO=y # CONFIG_FIQ_DEBUGGER_FIQ_GLUE is not set CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y +CONFIG_TEE=y CONFIG_ARM_CPU_SUSPEND=y +# CONFIG_ARM_CRYPTO is not set # CONFIG_ARM_HIGHBANK_CPUIDLE is not set # CONFIG_ARM_PSCI_CPUIDLE is not set CONFIG_ARM_PSCI_FW=y # CONFIG_ARM_SCMI_PROTOCOL is not set CONFIG_ARM_SMCCC_SOC_ID=y +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_AEGIS128 is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_AES_TI is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_BLAKE2B is not set +# CONFIG_CRYPTO_BLAKE2S is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_CFB is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_CMAC is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_CURVE25519 is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_CCREE is not set +# CONFIG_CRYPTO_DEV_ROCKCHIP is not set +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_DRBG_MENU is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_ECDH is not set +# CONFIG_CRYPTO_ECHAINIV is not set +# CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_ESSIV is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +# CONFIG_CRYPTO_HMAC is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_JITTERENTROPY is not set +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_LIB_CHACHA is not set +# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_MANAGER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEQIV is not set +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SM2 is not set +# CONFIG_CRYPTO_SM3 is not set +# CONFIG_CRYPTO_SM4 is not set +# CONFIG_CRYPTO_STREEBOG is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_USER is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_VMAC is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_XXHASH is not set +# CONFIG_CRYPTO_ZSTD is not set CONFIG_GLOB=y # CONFIG_GLOB_SELFTEST is not set CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y +CONFIG_HW_RANDOM_OPTEE=y +CONFIG_LIB_MEMNEQ=y +CONFIG_OPTEE=y +CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1 CONFIG_SOC_BUS=y diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index df573135b2ad..749423c7910d 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -88,8 +88,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo1-lp4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo4-ddr4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo4-ddr4-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb1-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb1-ddr4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb1-ddr4-v10-spi-nand-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb2-ddr3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb3-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb4-ddr4-v10.dtb @@ -103,6 +105,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-mcu-k350c4516t.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-rgb2lvds.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-rgb-FX070-DHM11BOE-A.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-rgb-k350c4516t.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-sii9022-rgb2hdmi.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-spdif.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-dual-camera.dtb @@ -161,6 +164,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux-spi-nand.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v12-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v12-linux-spi-nand.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-sd0-android.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-sd0-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-x0-android.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-x0-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-dsi-dsc-MV2100UZ1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-ipc-6x-linux.dtb diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index d3a5db8ef1d5..8a71ba608617 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -2696,27 +2696,27 @@ i2s0 { i2s0_8ch_mclk: i2s0-8ch-mclk { rockchip,pins = - <3 RK_PC1 2 &pcfg_pull_none>; + <3 RK_PC1 2 &pcfg_pull_none_smt>; }; i2s0_8ch_sclktx: i2s0-8ch-sclktx { rockchip,pins = - <3 RK_PC3 2 &pcfg_pull_none>; + <3 RK_PC3 2 &pcfg_pull_none_smt>; }; i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { rockchip,pins = - <3 RK_PB4 2 &pcfg_pull_none>; + <3 RK_PB4 2 &pcfg_pull_none_smt>; }; i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { rockchip,pins = - <3 RK_PC2 2 &pcfg_pull_none>; + <3 RK_PC2 2 &pcfg_pull_none_smt>; }; i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { rockchip,pins = - <3 RK_PB5 2 &pcfg_pull_none>; + <3 RK_PB5 2 &pcfg_pull_none_smt>; }; i2s0_8ch_sdo0: i2s0-8ch-sdo0 { @@ -2763,17 +2763,17 @@ i2s1 { i2s1_2ch_mclk: i2s1-2ch-mclk { rockchip,pins = - <2 RK_PC3 1 &pcfg_pull_none>; + <2 RK_PC3 1 &pcfg_pull_none_smt>; }; i2s1_2ch_sclk: i2s1-2ch-sclk { rockchip,pins = - <2 RK_PC2 1 &pcfg_pull_none>; + <2 RK_PC2 1 &pcfg_pull_none_smt>; }; i2s1_2ch_lrck: i2s1-2ch-lrck { rockchip,pins = - <2 RK_PC1 1 &pcfg_pull_none>; + <2 RK_PC1 1 &pcfg_pull_none_smt>; }; i2s1_2ch_sdi: i2s1-2ch-sdi { @@ -2790,17 +2790,17 @@ i2s2 { i2s2_2ch_mclk: i2s2-2ch-mclk { rockchip,pins = - <3 RK_PA1 2 &pcfg_pull_none>; + <3 RK_PA1 2 &pcfg_pull_none_smt>; }; i2s2_2ch_sclk: i2s2-2ch-sclk { rockchip,pins = - <3 RK_PA2 2 &pcfg_pull_none>; + <3 RK_PA2 2 &pcfg_pull_none_smt>; }; i2s2_2ch_lrck: i2s2-2ch-lrck { rockchip,pins = - <3 RK_PA3 2 &pcfg_pull_none>; + <3 RK_PA3 2 &pcfg_pull_none_smt>; }; i2s2_2ch_sdi: i2s2-2ch-sdi { diff --git a/arch/arm64/boot/dts/rockchip/px30s-dram-default-timing.dtsi b/arch/arm64/boot/dts/rockchip/px30s-dram-default-timing.dtsi index c0b4f5d4c4ca..aefe70a80786 100644 --- a/arch/arm64/boot/dts/rockchip/px30s-dram-default-timing.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30s-dram-default-timing.dtsi @@ -310,12 +310,12 @@ dram_dll_dis_freq = ; phy_dll_dis_freq = ; /* drv when odt on */ - phy_dq_drv_odten = <35>; + phy_dq_drv_odten = <44>; phy_ca_drv_odten = <38>; phy_clk_drv_odten = <47>; dram_dq_drv_odten = <40>; /* drv when odt off */ - phy_dq_drv_odtoff = <35>; + phy_dq_drv_odtoff = <44>; phy_ca_drv_odtoff = <38>; phy_clk_drv_odtoff = <47>; dram_dq_drv_odtoff = <40>; @@ -328,11 +328,11 @@ dram_dq_odt_en_freq = <800>; phy_odt_en_freq = <800>; /* slew rate when odt enable */ - phy_dq_sr_odten = <0x0>; + phy_dq_sr_odten = <0x7>; phy_ca_sr_odten = <0x1>; phy_clk_sr_odten = <0x1>; /* slew rate when odt disable */ - phy_dq_sr_odtoff = <0x0>; + phy_dq_sr_odtoff = <0x7>; phy_ca_sr_odtoff = <0x1>; phy_clk_sr_odtoff = <0x1>; /* ssmod setting*/ @@ -371,7 +371,7 @@ lp4_dq_vref_odten = <276>; lp4_ca_vref_odten = <380>; /* lp4 vref info when odt disable */ - phy_lp4_dq_vref_odtoff = <340>; + phy_lp4_dq_vref_odtoff = <420>; lp4_dq_vref_odtoff = <420>; lp4_ca_vref_odtoff = <420>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk1808.dtsi b/arch/arm64/boot/dts/rockchip/rk1808.dtsi index 67f93f0c9d01..297b41269efb 100644 --- a/arch/arm64/boot/dts/rockchip/rk1808.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk1808.dtsi @@ -2246,15 +2246,15 @@ i2s1 { i2s1_2ch_lrck: i2s1-2ch-lrck { rockchip,pins = - <3 RK_PA0 1 &pcfg_pull_none_2ma>; + <3 RK_PA0 1 &pcfg_pull_none_2ma_smt>; }; i2s1_2ch_sclk: i2s1-2ch-sclk { rockchip,pins = - <3 RK_PA1 1 &pcfg_pull_none_2ma>; + <3 RK_PA1 1 &pcfg_pull_none_2ma_smt>; }; i2s1_2ch_mclk: i2s1-2ch-mclk { rockchip,pins = - <3 RK_PA2 1 &pcfg_pull_none_2ma>; + <3 RK_PA2 1 &pcfg_pull_none_2ma_smt>; }; i2s1_2ch_sdo: i2s1-2ch-sdo { rockchip,pins = @@ -2281,11 +2281,11 @@ }; i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { rockchip,pins = - <3 RK_PB0 1 &pcfg_pull_none_2ma>; + <3 RK_PB0 1 &pcfg_pull_none_2ma_smt>; }; i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { rockchip,pins = - <3 RK_PB1 1 &pcfg_pull_none_2ma>; + <3 RK_PB1 1 &pcfg_pull_none_2ma_smt>; }; i2s0_8ch_sdo3: i2s0-8ch-sdo3 { rockchip,pins = @@ -2301,15 +2301,15 @@ }; i2s0_8ch_mclk: i2s0-8ch-mclk { rockchip,pins = - <3 RK_PB5 1 &pcfg_pull_none_2ma>; + <3 RK_PB5 1 &pcfg_pull_none_2ma_smt>; }; i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { rockchip,pins = - <3 RK_PB6 1 &pcfg_pull_none_2ma>; + <3 RK_PB6 1 &pcfg_pull_none_2ma_smt>; }; i2s0_8ch_sclktx: i2s0-8ch-sclktx { rockchip,pins = - <3 RK_PB7 1 &pcfg_pull_none_2ma>; + <3 RK_PB7 1 &pcfg_pull_none_2ma_smt>; }; i2s0_8ch_sdo0: i2s0-8ch-sdo0 { rockchip,pins = diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index 6d4c52c98d2e..119c84431d1f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -1840,17 +1840,17 @@ i2s_2ch_0 { i2s_2ch_0_mclk: i2s-2ch-0-mclk { rockchip,pins = - <4 RK_PB4 1 &pcfg_pull_none>; + <4 RK_PB4 1 &pcfg_pull_none_smt>; }; i2s_2ch_0_sclk: i2s-2ch-0-sclk { rockchip,pins = - <4 RK_PB5 1 &pcfg_pull_none>; + <4 RK_PB5 1 &pcfg_pull_none_smt>; }; i2s_2ch_0_lrck: i2s-2ch-0-lrck { rockchip,pins = - <4 RK_PB6 1 &pcfg_pull_none>; + <4 RK_PB6 1 &pcfg_pull_none_smt>; }; i2s_2ch_0_sdo: i2s-2ch-0-sdo { @@ -1867,27 +1867,27 @@ i2s_8ch_0 { i2s_8ch_0_mclk: i2s-8ch-0-mclk { rockchip,pins = - <2 RK_PA4 1 &pcfg_pull_none>; + <2 RK_PA4 1 &pcfg_pull_none_smt>; }; i2s_8ch_0_sclktx: i2s-8ch-0-sclktx { rockchip,pins = - <2 RK_PA5 1 &pcfg_pull_none>; + <2 RK_PA5 1 &pcfg_pull_none_smt>; }; i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx { rockchip,pins = - <2 RK_PA6 1 &pcfg_pull_none>; + <2 RK_PA6 1 &pcfg_pull_none_smt>; }; i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx { rockchip,pins = - <2 RK_PA7 1 &pcfg_pull_none>; + <2 RK_PA7 1 &pcfg_pull_none_smt>; }; i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx { rockchip,pins = - <2 RK_PB0 1 &pcfg_pull_none>; + <2 RK_PB0 1 &pcfg_pull_none_smt>; }; i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 { @@ -1934,27 +1934,27 @@ i2s_8ch_1_m0 { i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk { rockchip,pins = - <1 RK_PA2 2 &pcfg_pull_none>; + <1 RK_PA2 2 &pcfg_pull_none_smt>; }; i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx { rockchip,pins = - <1 RK_PA3 2 &pcfg_pull_none>; + <1 RK_PA3 2 &pcfg_pull_none_smt>; }; i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx { rockchip,pins = - <1 RK_PA4 2 &pcfg_pull_none>; + <1 RK_PA4 2 &pcfg_pull_none_smt>; }; i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx { rockchip,pins = - <1 RK_PA5 2 &pcfg_pull_none>; + <1 RK_PA5 2 &pcfg_pull_none_smt>; }; i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx { rockchip,pins = - <1 RK_PA6 2 &pcfg_pull_none>; + <1 RK_PA6 2 &pcfg_pull_none_smt>; }; i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 { @@ -1986,27 +1986,27 @@ i2s_8ch_1_m1 { i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk { rockchip,pins = - <1 RK_PB4 2 &pcfg_pull_none>; + <1 RK_PB4 2 &pcfg_pull_none_smt>; }; i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx { rockchip,pins = - <1 RK_PB5 2 &pcfg_pull_none>; + <1 RK_PB5 2 &pcfg_pull_none_smt>; }; i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx { rockchip,pins = - <1 RK_PB6 2 &pcfg_pull_none>; + <1 RK_PB6 2 &pcfg_pull_none_smt>; }; i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx { rockchip,pins = - <1 RK_PB7 2 &pcfg_pull_none>; + <1 RK_PB7 2 &pcfg_pull_none_smt>; }; i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx { rockchip,pins = - <1 RK_PC0 2 &pcfg_pull_none>; + <1 RK_PC0 2 &pcfg_pull_none_smt>; }; i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 { diff --git a/arch/arm64/boot/dts/rockchip/rk3308bs-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3308bs-pinctrl.dtsi index 90dc2c17c771..038ed00c25c8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308bs-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308bs-pinctrl.dtsi @@ -9,6 +9,11 @@ bias-disable; drive-strength-s = <4>; }; + pcfg_pull_none_0_4ma_smt: pcfg-pull-none-0-4ma-smt { + bias-disable; + drive-strength-s = <4>; + input-schmitt-enable; + }; pcfg_pull_up_0_4ma: pcfg-pull-up-0-4ma { bias-pull-up; drive-strength-s = <4>; @@ -127,17 +132,17 @@ i2s_2ch_0 { i2s_2ch_0_mclk: i2s-2ch-0-mclk { rockchip,pins = - <4 RK_PB4 1 &pcfg_pull_none>; + <4 RK_PB4 1 &pcfg_pull_none_smt>; }; i2s_2ch_0_sclk: i2s-2ch-0-sclk { rockchip,pins = - <4 RK_PB5 1 &pcfg_pull_none>; + <4 RK_PB5 1 &pcfg_pull_none_smt>; }; i2s_2ch_0_lrck: i2s-2ch-0-lrck { rockchip,pins = - <4 RK_PB6 1 &pcfg_pull_none_0_4ma>; + <4 RK_PB6 1 &pcfg_pull_none_0_4ma_smt>; }; i2s_2ch_0_sdo: i2s-2ch-0-sdo { @@ -154,27 +159,27 @@ i2s_8ch_0 { i2s_8ch_0_mclk: i2s-8ch-0-mclk { rockchip,pins = - <2 RK_PA4 1 &pcfg_pull_none_0_4ma>; + <2 RK_PA4 1 &pcfg_pull_none_0_4ma_smt>; }; i2s_8ch_0_sclktx: i2s-8ch-0-sclktx { rockchip,pins = - <2 RK_PA5 1 &pcfg_pull_none_0_4ma>; + <2 RK_PA5 1 &pcfg_pull_none_0_4ma_smt>; }; i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx { rockchip,pins = - <2 RK_PA6 1 &pcfg_pull_none_0_4ma>; + <2 RK_PA6 1 &pcfg_pull_none_0_4ma_smt>; }; i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx { rockchip,pins = - <2 RK_PA7 1 &pcfg_pull_none_0_4ma>; + <2 RK_PA7 1 &pcfg_pull_none_0_4ma_smt>; }; i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx { rockchip,pins = - <2 RK_PB0 1 &pcfg_pull_none_0_4ma>; + <2 RK_PB0 1 &pcfg_pull_none_0_4ma_smt>; }; i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 { @@ -222,27 +227,27 @@ i2s_8ch_1_m0 { i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk { rockchip,pins = - <1 RK_PA2 2 &pcfg_pull_none_0_4ma>; + <1 RK_PA2 2 &pcfg_pull_none_0_4ma_smt>; }; i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx { rockchip,pins = - <1 RK_PA3 2 &pcfg_pull_none_0_4ma>; + <1 RK_PA3 2 &pcfg_pull_none_0_4ma_smt>; }; i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx { rockchip,pins = - <1 RK_PA4 2 &pcfg_pull_none_0_4ma>; + <1 RK_PA4 2 &pcfg_pull_none_0_4ma_smt>; }; i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx { rockchip,pins = - <1 RK_PA5 2 &pcfg_pull_none_0_4ma>; + <1 RK_PA5 2 &pcfg_pull_none_0_4ma_smt>; }; i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx { rockchip,pins = - <1 RK_PA6 2 &pcfg_pull_none_0_4ma>; + <1 RK_PA6 2 &pcfg_pull_none_0_4ma_smt>; }; i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 { @@ -274,27 +279,27 @@ i2s_8ch_1_m1 { i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk { rockchip,pins = - <1 RK_PB4 2 &pcfg_pull_none_0_4ma>; + <1 RK_PB4 2 &pcfg_pull_none_0_4ma_smt>; }; i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx { rockchip,pins = - <1 RK_PB5 2 &pcfg_pull_none_0_4ma>; + <1 RK_PB5 2 &pcfg_pull_none_0_4ma_smt>; }; i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx { rockchip,pins = - <1 RK_PB6 2 &pcfg_pull_none_0_4ma>; + <1 RK_PB6 2 &pcfg_pull_none_0_4ma_smt>; }; i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx { rockchip,pins = - <1 RK_PB7 2 &pcfg_pull_none_0_4ma>; + <1 RK_PB7 2 &pcfg_pull_none_0_4ma_smt>; }; i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx { rockchip,pins = - <1 RK_PC0 2 &pcfg_pull_none_0_4ma>; + <1 RK_PC0 2 &pcfg_pull_none_0_4ma_smt>; }; i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dtsi index 31e3ae2cc471..ddd3dcd47e2c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dtsi @@ -175,6 +175,7 @@ wifi_chip_type = "ap6354"; sdio_vref = <1800>; WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */ + WIFI,poweren_gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-evb.dtsi index 5ef489c1a1ad..9b39d2f1b8f2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dtsi @@ -210,6 +210,7 @@ wifi_chip_type = "ap6354"; sdio_vref = <1800>; WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */ + WIFI,poweren_gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-excavator-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-excavator-sapphire.dtsi index 3c411c2a63b0..e17867f04d7b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-excavator-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-excavator-sapphire.dtsi @@ -70,6 +70,7 @@ wifi_chip_type = "ap6354"; sdio_vref = <1800>; WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */ + WIFI,poweren_gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-demo4-ddr4-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3528-demo4-ddr4-v10-linux.dts new file mode 100644 index 000000000000..cea751a81367 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-demo4-ddr4-v10-linux.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3528-demo4-ddr4-v10.dtsi" +#include "rk3528-linux.dtsi" + +/ { + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait"; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-evb1-ddr4-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3528-evb1-ddr4-v10-linux.dts index 787534404741..c173af57115b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-evb1-ddr4-v10-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-evb1-ddr4-v10-linux.dts @@ -7,6 +7,12 @@ #include "rk3528-evb1-ddr4-v10.dtsi" #include "rk3528-linux.dtsi" +/ { + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait"; + }; +}; + &sdmmc { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-evb1-ddr4-v10-spi-nand-linux.dts b/arch/arm64/boot/dts/rockchip/rk3528-evb1-ddr4-v10-spi-nand-linux.dts new file mode 100644 index 000000000000..5b87252cb480 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-evb1-ddr4-v10-spi-nand-linux.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3528-evb1-ddr4-v10.dtsi" +#include "rk3528-linux.dtsi" + +/ { + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw rootwait"; + }; +}; + +&sdmmc { + status = "disabled"; +}; + +&sfc { + status = "okay"; + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <75000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi index 2b8b2d38bf6b..b4b78b495f11 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi @@ -366,21 +366,21 @@ i2s0m0_lrck: i2s0m0-lrck { rockchip,pins = /* i2s0_lrck_m0 */ - <3 RK_PB6 1 &pcfg_pull_none>; + <3 RK_PB6 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s0m0_mclk: i2s0m0-mclk { rockchip,pins = /* i2s0_mclk_m0 */ - <3 RK_PB4 1 &pcfg_pull_none>; + <3 RK_PB4 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s0m0_sclk: i2s0m0-sclk { rockchip,pins = /* i2s0_sclk_m0 */ - <3 RK_PB5 1 &pcfg_pull_none>; + <3 RK_PB5 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ @@ -400,21 +400,21 @@ i2s0m1_lrck: i2s0m1-lrck { rockchip,pins = /* i2s0_lrck_m1 */ - <1 RK_PB6 1 &pcfg_pull_none>; + <1 RK_PB6 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s0m1_mclk: i2s0m1-mclk { rockchip,pins = /* i2s0_mclk_m1 */ - <1 RK_PB4 1 &pcfg_pull_none>; + <1 RK_PB4 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s0m1_sclk: i2s0m1-sclk { rockchip,pins = /* i2s0_sclk_m1 */ - <1 RK_PB5 1 &pcfg_pull_none>; + <1 RK_PB5 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ @@ -436,21 +436,21 @@ i2s1_lrck: i2s1-lrck { rockchip,pins = /* i2s1_lrck */ - <4 RK_PA6 1 &pcfg_pull_none>; + <4 RK_PA6 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1_mclk: i2s1-mclk { rockchip,pins = /* i2s1_mclk */ - <4 RK_PA4 1 &pcfg_pull_none>; + <4 RK_PA4 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1_sclk: i2s1-sclk { rockchip,pins = /* i2s1_sclk */ - <4 RK_PA5 1 &pcfg_pull_none>; + <4 RK_PA5 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-sii9022-rgb2hdmi.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-sii9022-rgb2hdmi.dts new file mode 100644 index 000000000000..bf760970077d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-sii9022-rgb2hdmi.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3562-evb1-lp4x-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk817.dtsi" + +/ { + model = "Rockchip RK3562 EVB1 LP4X V10 Board + RK EVB SII9022 RGB2HDMI DISPLAY Ext Board"; + compatible = "rockchip,rk3562-evb1-lp4x-v10-sii9022-rgb2hdmi", "rockchip,rk3562"; +}; + +&dsi { + status = "disabled"; +}; + +&dsi_in_vp0 { + status = "disabled"; +}; + +/* + * The pins of gmac0 and rgb are multiplexed + */ +&gmac0 { + status = "disabled"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c3m0_xfer>; + status = "okay"; + + sii9022: sii9022@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + pinctrl-names = "default"; + pinctrl-0 = <&sii902x_hdmi>; + interrupt-parent = <&gpio3>; + interrupts = ; + reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + enable-gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + bus-format = ; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in_rgb: endpoint { + remote-endpoint = <&rgb_out_sii9022>; + }; + }; + }; + }; +}; + +/* + * The pins of pcie2x1/pdm_codec and rgb are multiplexed + */ +&pcie2x1 { + status = "disabled"; +}; + +&pdm_codec { + status = "disabled"; +}; + +&pinctrl { + sii902x { + sii902x_hdmi: sii902x-hdmi { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&rgb { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&vo_pins>; + + ports { + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_sii9022: endpoint@0 { + reg = <0>; + remote-endpoint = <&sii9022_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp0 { + status = "okay"; +}; + +&route_rgb { + status = "disabled"; + connect = <&vp0_out_rgb>; +}; + +/* + * The pins of sai0/vcc_mipicsi0/u2phy_host and rgb are multiplexed + */ +&sai0 { + status = "disabled"; +}; + +&u2phy_host { + status = "disabled"; +}; + +&vcc5v0_usb_host { + status = "disabled"; +}; + +&vcc_mipicsi0 { + status = "disabled"; +}; + +&video_phy { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi index 66f58ec13e6a..5d4a5d33a0d1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi @@ -370,21 +370,21 @@ i2s0m0_lrck: i2s0m0-lrck { rockchip,pins = /* i2s0_lrck_m0 */ - <3 RK_PA4 1 &pcfg_pull_none>; + <3 RK_PA4 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s0m0_mclk: i2s0m0-mclk { rockchip,pins = /* i2s0_mclk_m0 */ - <3 RK_PA2 1 &pcfg_pull_none>; + <3 RK_PA2 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s0m0_sclk: i2s0m0-sclk { rockchip,pins = /* i2s0_sclk_m0 */ - <3 RK_PA3 1 &pcfg_pull_none>; + <3 RK_PA3 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ @@ -447,21 +447,21 @@ i2s0m1_lrck: i2s0m1-lrck { rockchip,pins = /* i2s0_lrck_m1 */ - <1 RK_PC4 3 &pcfg_pull_none>; + <1 RK_PC4 3 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s0m1_mclk: i2s0m1-mclk { rockchip,pins = /* i2s0_mclk_m1 */ - <1 RK_PC6 3 &pcfg_pull_none>; + <1 RK_PC6 3 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s0m1_sclk: i2s0m1-sclk { rockchip,pins = /* i2s0_sclk_m1 */ - <1 RK_PC5 3 &pcfg_pull_none>; + <1 RK_PC5 3 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ @@ -526,21 +526,21 @@ i2s1m0_lrck: i2s1m0-lrck { rockchip,pins = /* i2s1_lrck_m0 */ - <3 RK_PC6 2 &pcfg_pull_none>; + <3 RK_PC6 2 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1m0_mclk: i2s1m0-mclk { rockchip,pins = /* i2s1_mclk_m0 */ - <3 RK_PC4 2 &pcfg_pull_none>; + <3 RK_PC4 2 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1m0_sclk: i2s1m0-sclk { rockchip,pins = /* i2s1_sclk_m0 */ - <3 RK_PC5 2 &pcfg_pull_none>; + <3 RK_PC5 2 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ @@ -603,21 +603,21 @@ i2s1m1_lrck: i2s1m1-lrck { rockchip,pins = /* i2s1_lrck_m1 */ - <3 RK_PB4 1 &pcfg_pull_none>; + <3 RK_PB4 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1m1_mclk: i2s1m1-mclk { rockchip,pins = /* i2s1_mclk_m1 */ - <3 RK_PB2 1 &pcfg_pull_none>; + <3 RK_PB2 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1m1_sclk: i2s1m1-sclk { rockchip,pins = /* i2s1_sclk_m1 */ - <3 RK_PB3 1 &pcfg_pull_none>; + <3 RK_PB3 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ @@ -682,21 +682,21 @@ i2s2m0_lrck: i2s2m0-lrck { rockchip,pins = /* i2s2_lrck_m0 */ - <1 RK_PD6 1 &pcfg_pull_none>; + <1 RK_PD6 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s2m0_mclk: i2s2m0-mclk { rockchip,pins = /* i2s2_mclk_m0 */ - <2 RK_PA1 1 &pcfg_pull_none>; + <2 RK_PA1 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s2m0_sclk: i2s2m0-sclk { rockchip,pins = /* i2s2_sclk_m0 */ - <1 RK_PD5 1 &pcfg_pull_none>; + <1 RK_PD5 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ @@ -717,21 +717,21 @@ i2s2m1_lrck: i2s2m1-lrck { rockchip,pins = /* i2s2_lrck_m1 */ - <4 RK_PA1 3 &pcfg_pull_none>; + <4 RK_PA1 3 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s2m1_mclk: i2s2m1-mclk { rockchip,pins = /* i2s2_mclk_m1 */ - <3 RK_PD6 3 &pcfg_pull_none>; + <3 RK_PD6 3 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s2m1_sclk: i2s2m1-sclk { rockchip,pins = /* i2s2_sclk_m1 */ - <4 RK_PB1 4 &pcfg_pull_none>; + <4 RK_PB1 4 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi index 30d8cedfbdc7..a78bdf986a25 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi @@ -917,35 +917,35 @@ i2s1m0_lrckrx: i2s1m0-lrckrx { rockchip,pins = /* i2s1m0_lrckrx */ - <1 RK_PA6 1 &pcfg_pull_none>; + <1 RK_PA6 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1m0_lrcktx: i2s1m0-lrcktx { rockchip,pins = /* i2s1m0_lrcktx */ - <1 RK_PA5 1 &pcfg_pull_none>; + <1 RK_PA5 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1m0_mclk: i2s1m0-mclk { rockchip,pins = /* i2s1m0_mclk */ - <1 RK_PA2 1 &pcfg_pull_none>; + <1 RK_PA2 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1m0_sclkrx: i2s1m0-sclkrx { rockchip,pins = /* i2s1m0_sclkrx */ - <1 RK_PA4 1 &pcfg_pull_none>; + <1 RK_PA4 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1m0_sclktx: i2s1m0-sclktx { rockchip,pins = /* i2s1m0_sclktx */ - <1 RK_PA3 1 &pcfg_pull_none>; + <1 RK_PA3 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ @@ -1008,35 +1008,35 @@ i2s1m1_lrckrx: i2s1m1-lrckrx { rockchip,pins = /* i2s1m1_lrckrx */ - <4 RK_PA7 5 &pcfg_pull_none>; + <4 RK_PA7 5 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1m1_lrcktx: i2s1m1-lrcktx { rockchip,pins = /* i2s1m1_lrcktx */ - <3 RK_PD0 4 &pcfg_pull_none>; + <3 RK_PD0 4 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1m1_mclk: i2s1m1-mclk { rockchip,pins = /* i2s1m1_mclk */ - <3 RK_PC6 4 &pcfg_pull_none>; + <3 RK_PC6 4 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1m1_sclkrx: i2s1m1-sclkrx { rockchip,pins = /* i2s1m1_sclkrx */ - <4 RK_PA6 5 &pcfg_pull_none>; + <4 RK_PA6 5 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1m1_sclktx: i2s1m1-sclktx { rockchip,pins = /* i2s1m1_sclktx */ - <3 RK_PC7 4 &pcfg_pull_none>; + <3 RK_PC7 4 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ @@ -1099,35 +1099,35 @@ i2s1m2_lrckrx: i2s1m2-lrckrx { rockchip,pins = /* i2s1m2_lrckrx */ - <3 RK_PC5 5 &pcfg_pull_none>; + <3 RK_PC5 5 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1m2_lrcktx: i2s1m2-lrcktx { rockchip,pins = /* i2s1m2_lrcktx */ - <2 RK_PD2 5 &pcfg_pull_none>; + <2 RK_PD2 5 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1m2_mclk: i2s1m2-mclk { rockchip,pins = /* i2s1m2_mclk */ - <2 RK_PD0 5 &pcfg_pull_none>; + <2 RK_PD0 5 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1m2_sclkrx: i2s1m2-sclkrx { rockchip,pins = /* i2s1m2_sclkrx */ - <3 RK_PC3 5 &pcfg_pull_none>; + <3 RK_PC3 5 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1m2_sclktx: i2s1m2-sclktx { rockchip,pins = /* i2s1m2_sclktx */ - <2 RK_PD1 5 &pcfg_pull_none>; + <2 RK_PD1 5 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ @@ -1192,35 +1192,35 @@ i2s2m0_lrckrx: i2s2m0-lrckrx { rockchip,pins = /* i2s2m0_lrckrx */ - <2 RK_PC0 1 &pcfg_pull_none>; + <2 RK_PC0 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s2m0_lrcktx: i2s2m0-lrcktx { rockchip,pins = /* i2s2m0_lrcktx */ - <2 RK_PC3 1 &pcfg_pull_none>; + <2 RK_PC3 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s2m0_mclk: i2s2m0-mclk { rockchip,pins = /* i2s2m0_mclk */ - <2 RK_PC1 1 &pcfg_pull_none>; + <2 RK_PC1 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s2m0_sclkrx: i2s2m0-sclkrx { rockchip,pins = /* i2s2m0_sclkrx */ - <2 RK_PB7 1 &pcfg_pull_none>; + <2 RK_PB7 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s2m0_sclktx: i2s2m0-sclktx { rockchip,pins = /* i2s2m0_sclktx */ - <2 RK_PC2 1 &pcfg_pull_none>; + <2 RK_PC2 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ @@ -1241,35 +1241,35 @@ i2s2m1_lrckrx: i2s2m1-lrckrx { rockchip,pins = /* i2s2m1_lrckrx */ - <4 RK_PA5 5 &pcfg_pull_none>; + <4 RK_PA5 5 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s2m1_lrcktx: i2s2m1-lrcktx { rockchip,pins = /* i2s2m1_lrcktx */ - <4 RK_PA4 5 &pcfg_pull_none>; + <4 RK_PA4 5 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s2m1_mclk: i2s2m1-mclk { rockchip,pins = /* i2s2m1_mclk */ - <4 RK_PB6 5 &pcfg_pull_none>; + <4 RK_PB6 5 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s2m1_sclkrx: i2s2m1-sclkrx { rockchip,pins = /* i2s2m1_sclkrx */ - <4 RK_PC1 5 &pcfg_pull_none>; + <4 RK_PC1 5 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s2m1_sclktx: i2s2m1-sclktx { rockchip,pins = /* i2s2m1_sclktx */ - <4 RK_PB7 4 &pcfg_pull_none>; + <4 RK_PB7 4 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ @@ -1292,21 +1292,21 @@ i2s3m0_lrck: i2s3m0-lrck { rockchip,pins = /* i2s3m0_lrck */ - <3 RK_PA4 4 &pcfg_pull_none>; + <3 RK_PA4 4 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s3m0_mclk: i2s3m0-mclk { rockchip,pins = /* i2s3m0_mclk */ - <3 RK_PA2 4 &pcfg_pull_none>; + <3 RK_PA2 4 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s3m0_sclk: i2s3m0-sclk { rockchip,pins = /* i2s3m0_sclk */ - <3 RK_PA3 4 &pcfg_pull_none>; + <3 RK_PA3 4 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ @@ -1327,21 +1327,21 @@ i2s3m1_lrck: i2s3m1-lrck { rockchip,pins = /* i2s3m1_lrck */ - <4 RK_PC4 5 &pcfg_pull_none>; + <4 RK_PC4 5 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s3m1_mclk: i2s3m1-mclk { rockchip,pins = /* i2s3m1_mclk */ - <4 RK_PC2 5 &pcfg_pull_none>; + <4 RK_PC2 5 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s3m1_sclk: i2s3m1-sclk { rockchip,pins = /* i2s3m1_sclk */ - <4 RK_PC3 5 &pcfg_pull_none>; + <4 RK_PC3 5 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ diff --git a/arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0-android.dts b/arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0-android.dts new file mode 100644 index 000000000000..1f2f044955d5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0-android.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include "rk3568-toybrick-sd0.dtsi" +#include "rk3568-android.dtsi" +//#include "rk3568-toybrick-sd0-mipi-tx0.dtsi" +/delete-node/ &board_id; +/ { + model = "Rockchip RK3568 Toybrick SD0 Board"; + compatible = "rockchip,rk3568-toybrick-sd0-linux","rockchip,rk3568"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0-linux.dts b/arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0-linux.dts new file mode 100644 index 000000000000..f126babb116a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0-linux.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include "rk3568-toybrick-sd0.dtsi" +#include "rk3568-linux.dtsi" +//#include "rk3568-toybrick-sd0-mipi-tx0.dtsi" +/delete-node/ &board_id; +/ { + model = "Rockchip RK3568 Toybrick SD0 Board"; + compatible = "rockchip,rk3568-toybrick-sd0-linux","rockchip,rk3568"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0-mipi-tx0.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0-mipi-tx0.dtsi new file mode 100644 index 000000000000..7dbcf6439898 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0-mipi-tx0.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + compatible = "rockchip,rk3568-toybrick-sd0-mipi-tx0", "rockchip,rk3568"; +}; + +/* + * mipi_dphy0 needs to be enabled + * when dsi0 is enabled + */ +&backlight { + status = "okay"; + pwms = <&pwm14 0 25000 0>; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; +}; + +&i2c1 { + status = "okay"; + power-supply = <&vcc3v3_lcd0_n>; + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + status = "okay"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_pin>; + goodix,rst-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio4 RK_PC2 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&pwm14{ + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&video_phy0 { + status = "okay"; +}; + +&pinctrl { + touch { + touch_pin: touch-pin { + rockchip,pins = + <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>, + <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0.dtsi new file mode 100644 index 000000000000..13692175b129 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0.dtsi @@ -0,0 +1,607 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include "rk3568.dtsi" +#include "rk3568-toybrick.dtsi" + +/delete-node/ &adc_keys; + +/ { + compatible = "rockchip,rk3568-toybrick-sd0", "rockchip,rk3568"; + + bt-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion = <1>; + simple-audio-card,mclk-fs = <512>; + simple-audio-card,name = "rockchip,bt"; + #simple-audio-card,bitclock-master = <&sound2_master>; + #simple-audio-card,frame-master = <&sound2_master>; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; + sound2_master:simple-audio-card,codec { + #sound-dai-cells = <0>; + sound-dai = <&bt_sco>; + }; + }; + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_3v3: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "pcie30_3v3"; + regulator-min-microvolt = <100000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <100000 0x0 + 3300000 0x1>; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 2>; + }; + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_pcie: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_bu: vcc3v3-bu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-name = "vcc5v0_otg"; + }; +}; + +&bus_npu { + status = "okay"; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out>; + data-lanes = <1 2 3 4>; + }; + mipi_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&ov50c40_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>, <&cru CLK_MAC1_OUT>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>, <25000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + ð1m1_pins>; + + tx_delay = <0x47>; + rx_delay = <0x28>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&i2s2_2ch { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&i2c0 { + status = "okay"; + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + regulators { + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2s1_8ch { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdo0 + &i2s1m0_sdi0>; +}; + +&i2c5 { + status = "okay"; + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + imx415: imx415@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + // must be high at last + power-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + // must be high at last do at vcc_camera + //reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20-RK3568"; + //lens-focus = <&cam_ircut0>; + port { + imx415_out: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + aw8601: aw8601@c { + compatible = "awinic,aw8601"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <56>; + rockchip,vcm-rated-current = <96>; + rockchip,vcm-step-mode = <4>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + otp_eeprom: otp_eeprom@50 { + compatible = "rk,otp_eeprom"; + status = "okay"; + reg = <0x50>; + }; + + ov50c40: ov50c40@36 { + compatible = "ovti,ov50c40"; + reg = <0x36>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;// must be high at last + reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>;// must be high at last + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "HZGA06"; + rockchip,camera-module-lens-name = "ZE0082C1-RK3568"; + eeprom-ctrl = <&otp_eeprom>; + lens-focus = <&aw8601>; + port { + ov50c40_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&leds { + status = "okay"; + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + clocks = <&cru CLK_MAC1_OUT>; + }; +}; + +&pcie2x1 { + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8111_isolate>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&pcie30_3v3>; + status = "okay"; +}; + +&reserved_memory { + linux,cma { + compatible = "shared-dma-pool"; + inactive; + reusable; + reg = <0x0 0x10000000 0x0 0x08000000>; + linux,cma-default; + }; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy_out>; + }; + }; +}; + +&rockchip_suspend { + status = "disabled"; +}; + +&rknpu { + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&sdio_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <200>; + status = "okay"; +}; + +&sdmmc1 { + status = "disabled"; +}; + +&sdmmc2 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "disabled"; +}; + +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; +}; + +&wireless_bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_pin>; + BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pinctrl { + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrckrx: i2s1m0-lrckrx { + rockchip,pins = + /* i2s1m0_lrckrx */ + <1 RK_PA6 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_lrcktx: i2s1m0-lrcktx { + rockchip,pins = + /* i2s1m0_lrcktx */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins = + /* i2s1m0_mclk */ + <1 RK_PA2 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sclkrx: i2s1m0-sclkrx { + rockchip,pins = + /* i2s1m0_sclkrx */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sclktx: i2s1m0-sclktx { + rockchip,pins = + /* i2s1m0_sclktx */ + <1 RK_PA3 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins = + /* i2s1m0_sdi0 */ + <1 RK_PB3 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins = + /* i2s1m0_sdi1 */ + <1 RK_PB2 2 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins = + /* i2s1m0_sdi2 */ + <1 RK_PB1 2 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins = + /* i2s1m0_sdi3 */ + <1 RK_PB0 2 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins = + /* i2s1m0_sdo0 */ + <1 RK_PA7 1 &pcfg_pull_up_drv_level_4>; + }; + }; + + rtc { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rtl8111 { + rtl8111_isolate: rtl8111-isolate { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_pin: uart1-pin { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-toybrick-x0-android.dts b/arch/arm64/boot/dts/rockchip/rk3568-toybrick-x0-android.dts new file mode 100644 index 000000000000..795506d6677c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-toybrick-x0-android.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include "rk3568-toybrick-x0.dtsi" +#include "rk3568-android.dtsi" +/ { + compatible = "rockchip,rk3568-toybrick-x0-android","rockchip,rk3568"; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568-toybrick-x0-linux.dts b/arch/arm64/boot/dts/rockchip/rk3568-toybrick-x0-linux.dts new file mode 100644 index 000000000000..9abc800cd1b9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-toybrick-x0-linux.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include "rk3568-toybrick-x0.dtsi" +#include "rk3568-linux.dtsi" +/delete-node/ &board_id; +/ { + compatible = "rockchip,rk3568-toybrick-x0-linux","rockchip,rk3568"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-toybrick-x0.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-toybrick-x0.dtsi new file mode 100644 index 000000000000..c71eedafcaa2 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-toybrick-x0.dtsi @@ -0,0 +1,725 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include "rk3568.dtsi" +#include "rk3568-toybrick.dtsi" + +/delete-node/ &adc_keys; + +/ { + compatible = "rockchip,rk3568-toybrick", "rockchip,rk3568"; + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <1250000>; + }; + + mute-key { + linux,code = ; + label = "mute"; + press-threshold-microvolt = <850000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <400000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <20000>; + }; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + led@1 { + gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + label = "blue"; // Blue LED + retain-state-suspended; + }; + + led@2 { + gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; + label = "red"; // Red LED + retain-state-suspended; + }; + + led@3 { + gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + label = "green"; // Green LED + retain-state-suspended; + }; + }; + + pcie20_3v3: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "pcie20_3v3"; + regulator-min-microvolt = <100000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <100000 0x0 + 3300000 0x1>; + }; + + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_3v3: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "pcie30_3v3"; + regulator-min-microvolt = <100000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <100000 0x0 + 3300000 0x1>; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 1>; + }; + + rk809_sound_micarray: rk809-sound-micarray { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s1_8ch>; + }; + codec { + sound-dai = <&rk809_codec 0>; + }; + }; + simple-audio-card,dai-link@1 { + format = "i2s"; + cpu { + sound-dai = <&i2s1_8ch>; + }; + codec { + sound-dai = <&es7210>; + }; + }; + }; + + rt5672-sound { + compatible = "rockchip-rt5670"; + status = "disabled"; + dais { + dai0 { + audio-codec = <&rt5670>; + audio-controller = <&i2s1_8ch>; + format = "i2s"; + }; + dai1 { + audio-codec = <&rt5670>; + audio-controller = <&i2s1_8ch>; + format = "i2s"; + }; + dai2 { + audio-codec = <&es7210>; + audio-controller = <&i2s1_8ch>; + format = "i2s"; + }; + }; + }; + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + vcc3v3_bu: vcc3v3-bu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + mipi_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&gc8034_out>; + data-lanes = <1 2 3 4>; + }; + mipi_in_ucam2: endpoint@3 { + reg = <3>; + remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x37>; + rx_delay = <0x2e>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x47>; + rx_delay = <0x28>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&i2c3 { + status = "okay"; + rt5670: rt5670@1c { + status = "okay"; + #sound-dai-cell = <0>; + compatible = "realtek,rt5670"; + reg = <0x1c>; + }; + + es7210: es7210@40 { + #sound-dai-cells = <0>; + compatible = "MicArray_0"; + reg = <0x40>; + clocks = <&cru I2S1_MCLKOUT_RX>;//csqerr + clock-names = "mclk"; + }; + + es7210_1: es7210@42 { + compatible = "MicArray_1"; + reg = <0x42>; + }; +}; + +&i2c4 { + status = "okay"; + + gc8034: gc8034@37 { + compatible = "galaxycore,gc8034"; + reg = <0x37>; + clocks = <&cru CLK_CIF_OUT>;//CLK_CAM0_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + reset-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>; + rockchip,grf = <&grf>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + port { + gc8034_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + ov9750_1: ov9750_1@36 { + compatible = "ovti,ov9750"; + reg = <0x36>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + power-domains = <&power RK3568_PD_VI>; + reset-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT0854-FV1"; + rockchip,camera-module-lens-name = "CHT-842B-MD"; + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + + ov5695: ov5695@36 { + status = "okay"; + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + reset-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + gs_mxc6655xa: gs_mxc6655xa@15 { + status = "okay"; + compatible = "gs_mxc6655xa"; + pinctrl-names = "default"; + pinctrl-0 = <&mxc6655xa_irq_pin>; + reg = <0x15>; + irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + power-off-in-suspend = <1>; + layout = <1>; + }; + + mxc6655xa: mxc6655xa@15 { + status = "disabled"; + compatible = "gs_mxc6655xa"; + pinctrl-names = "default"; + pinctrl-0 = <&mxc6655xa_irq_pin>; + reg = <0x15>; + irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + power-off-in-suspend = <1>; + layout = <1>; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + + interrupt-parent = <&gpio0>; + interrupts = ; + }; +}; + +&i2s1_8ch { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_sclkrx + &i2s1m0_lrcktx + &i2s1m0_sclkrx + &i2s1m0_lrckrx + &i2s1m0_sdo0 + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3>; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&pcie30_3v3>; + status = "okay"; +}; + +&pwm7 { + status = "okay"; +}; + +&rk809_sound { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy_out>; + }; + }; +}; + +&sata2 { + status = "okay"; +}; + +&sdio_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <20>; + status = "okay"; +}; + +&sdmmc1 { + status = "disabled"; +}; + +&sdmmc2 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&vcc3v3_lcd1_n { + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "disabled"; +}; + +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + +&wireless_bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m0_rtsn>; + pinctrl-1 = <&uart8_pin>; + BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pinctrl { + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrckrx: i2s1m0-lrckrx { + rockchip,pins = + /* i2s1m0_lrckrx */ + <1 RK_PA6 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_lrcktx: i2s1m0-lrcktx { + rockchip,pins = + /* i2s1m0_lrcktx */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins = + /* i2s1m0_mclk */ + <1 RK_PA2 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sclkrx: i2s1m0-sclkrx { + rockchip,pins = + /* i2s1m0_sclkrx */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sclktx: i2s1m0-sclktx { + rockchip,pins = + /* i2s1m0_sclktx */ + <1 RK_PA3 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins = + /* i2s1m0_sdi0 */ + <1 RK_PB3 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins = + /* i2s1m0_sdi1 */ + <1 RK_PB2 2 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins = + /* i2s1m0_sdi2 */ + <1 RK_PB1 2 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins = + /* i2s1m0_sdi3 */ + <1 RK_PB0 2 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins = + /* i2s1m0_sdo0 */ + <1 RK_PA7 1 &pcfg_pull_up_drv_level_4>; + }; + }; + + leds_pin: leds-pin { + rockchip,pins = + <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>, + <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>, + <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + mxc6655xa { + mxc6655xa_irq_pin: mxc6655xa_irq_pin { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtc { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart8_pin: uart8-pin { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-toybrick.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-toybrick.dtsi new file mode 100644 index 000000000000..db4a86dc54b2 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-toybrick.dtsi @@ -0,0 +1,1862 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <297500>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <980000>; + }; + + back-key { + label = "back"; + linux,code = ; + press-threshold-microvolt = <1305500>; + }; + }; + + audiopwmout_diff: audiopwmout-diff { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,audiopwmout-diff"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&master>; + simple-audio-card,frame-master = <&master>; + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + master: simple-audio-card,codec { + sound-dai = <&dig_acodec>; + }; + }; + + /* + * extliux conf: extlinux.conf.${FLAG}.${BOARD_ID} + * dtb file: toybrick.dtb.${FLAG}.${BOARD_ID} + */ + board_id: board-id { + compatible = "board-id"; + io-channels = <&saradc 4>; + /* + * ID: adc-value/adc-io + * ------------------------- + * 0: adc-io is low level + * 1: 0 ~ 100 + * 2: 100 ~ 199 + * 3: 200 ~ 299 + * 4: 300 ~ 399 + * 5: 400 ~ 499 + * 6: 500 ~ 599 + * 7: 600 ~ 699 + * 8: 700 ~ 799 + * 9: 800 ~ 899 + * 10: 900 ~ 1024 + */ + adc-io = <29>;// GPIO0_D5 + thresholds = <100 200 300 400 500 600 700 800 900>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + backlight1: backlight1 { + compatible = "pwm-backlight"; + pwms = <&pwm5 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + bt-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-inversion = <1>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + #simple-audio-card,bitclock-master = <&sound2_master>; + #simple-audio-card,frame-master = <&sound2_master>; + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + sound2_master:simple-audio-card,codec { + #sound-dai-cells = <0>; + sound-dai = <&bt_sco>; + }; + }; + + bt_sco: bt-sco { + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <0>; + status = "okay"; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + }; + + spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + test-power { + status = "okay"; + }; + + vad_sound: vad-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3568-vad"; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>, <&vad>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-name = "vcc5v0_otg"; + }; + + vcc3v3_lcd0_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_lcd1_n: vcc3v3-lcd1-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd1_n"; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6398s"; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m0_rtsn>; + pinctrl-1 = <&uart8_pin>; + BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&can0 { + assigned-clocks = <&cru CLK_CAN0>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can0m1_pins>; + status = "disabled"; +}; + +&can1 { + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; + status = "disabled"; +}; + +&can2 { + assigned-clocks = <&cru CLK_CAN2>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can2m1_pins>; + status = "disabled"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&dsi0 { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi1 { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight1>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; + rockchip,phy-table = + <92812500 0x8009 0x0000 0x0270>, + <165000000 0x800b 0x0000 0x026d>, + <185625000 0x800b 0x0000 0x01ed>, + <297000000 0x800b 0x0000 0x01ad>, + <594000000 0x8029 0x0000 0x0088>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs452x"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_pin>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_pin>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; + +&i2c5 { + status = "okay"; + + mxc6655xa: mxc6655xa@15 { + status = "okay"; + compatible = "gs_mxc6655xa"; + pinctrl-names = "default"; + pinctrl-0 = <&mxc6655xa_irq_pin>; + reg = <0x15>; + irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + power-off-in-suspend = <1>; + layout = <1>; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&i2s3_2ch { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nand@0 { + reg = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + }; +}; + +/** + * Model: TB-RK3568X + * ----------------------------------------------------------- + * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. + * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; + * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages + * must be consistent with the software configuration correspondingly + * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration + * should also be configured to 1.8V accordingly; + * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration + * should also be configured to 3.3V accordingly; + * 3/ VCCIO2 voltage control selection (0xFDC20140) + * BIT[0]: 0x0: from GPIO_0A7 (default) + * BIT[0]: 0x1: from GRF + * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: + * L:VCCIO2 must supply 3.3V + * H:VCCIO2 must supply 1.8V + * | supply | domain | net | source | voltage | + * ----------------------------------------------------------- + * | pmuio1-supply | PMUIO1 | vcc3v3_pmu | LDO6 | 3.3V | + * | pmuio2-supply | PMUIO2 | vcc3v3_pmu | LDO6 | 3.3V | + * | vccio1-supply | VCCIO1 | vccio_acodec | LDO4 | 1.8V | + * | vccio2-supply | VCCIO2 | vccio_flash | vcc_1v8 | 1.8V | + * | vccio3-supply | VCCIO3 | vccio_sd | LDO5 | 3.3V | + * | vccio4-supply | VCCIO4 | vcc_1v8 | DCDC5 | 1.8V | + * | vccio5-supply | VCCIO5 | vcc_3v3 | SWITCH1 | 3.3V | + * | vccio6-supply | VCCIO6 | vcc_1v8 | DCDC5 | 1.8V | + * | vccio7-supply | VCCIO7 | vcc_3v3 | SWITCH1 | 3.3V | + * ----------------------------------------------------------- + */ +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + // vccio2-supply = <&vccio_flash>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&pwm5 { + status = "okay"; +}; + +&pwm7 { + status = "okay"; + + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pins>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_VOLUMEDOWN>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + supports-emmc; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sfc { + status = "okay"; +}; + +&spdif_8ch { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vad { + rockchip,audio-src = <&i2s1_8ch>; + rockchip,buffer-time-ms = <128>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + +&pinctrl { + + mxc6655xa { + mxc6655xa_irq_pin: mxc6655xa_irq_pin { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_pin: soc_slppin_pin { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_up>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_pin: touch-pin { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart8_pin: uart8-pin { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi index 431a5bbdb641..a10dad37f9cf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi @@ -558,6 +558,8 @@ &pcie3x4 { reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1>; status = "okay"; }; @@ -610,6 +612,12 @@ }; }; + pcie30x4 { + pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + rtl8111 { rtl8111_isolate: rtl8111-isolate { rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi index 03c9c36d0656..809c48754bf2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi @@ -385,6 +385,8 @@ &pcie3x4 { reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1>; status = "okay"; }; @@ -414,6 +416,12 @@ }; }; + pcie30x4 { + pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + sdio-pwrseq { wifi_enable_h: wifi-enable-h { rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi index 4213e54ab0b7..eca37c90b301 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi @@ -1044,6 +1044,8 @@ &pcie3x4 { reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1>; status = "okay"; }; @@ -1073,6 +1075,12 @@ }; }; + pcie30x4 { + pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + rtl8111 { rtl8111_isolate: rtl8111-isolate { rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4.dtsi index 8e783a98735c..07aaf22b1361 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4.dtsi @@ -230,9 +230,19 @@ num-lanes = <2>; reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1>; status = "okay"; }; +&pinctrl { + pcie30x4 { + pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + &pwm9 { pinctrl-0 = <&pwm9m2_pins>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi index 742d57254f3e..9e41ea8cfabf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi @@ -627,6 +627,8 @@ &pcie3x4 { reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1>; status = "okay"; }; @@ -679,6 +681,12 @@ }; }; + pcie30x4 { + pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + sdio-pwrseq { wifi_enable_h: wifi-enable-h { rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-linux.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-linux.dtsi index bfcde3f8e39a..12b815850b57 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-linux.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-linux.dtsi @@ -111,8 +111,3 @@ &rng { status = "okay"; }; - -/* Assign VOP_ACLK to 750MHZ for 8K */ -&vop { - assigned-clock-rates = <750000000>; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi index 5c345b2cde2d..925a81e45cd3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi @@ -426,6 +426,8 @@ &pcie3x4 { reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1>; status = "okay"; }; @@ -694,6 +696,13 @@ }; }; + pcie30x4 { + pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + rtc { rtc_int: rtc-int { rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vccio3-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vccio3-pinctrl.dtsi index 3756df74fc11..d1a1f2662134 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vccio3-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-vccio3-pinctrl.dtsi @@ -260,25 +260,34 @@ }; i2s2 { + /omit-if-no-ref/ + i2s2m0_idle: i2s2m0-idle { + rockchip,pins = + /* i2s2m0_lrck_gpio */ + <2 RK_PC0 0 &pcfg_pull_none>, + /* i2s2m0_sclk_gpio */ + <2 RK_PB7 0 &pcfg_pull_none>; + }; + /omit-if-no-ref/ i2s2m0_lrck: i2s2m0-lrck { rockchip,pins = /* i2s2m0_lrck */ - <2 RK_PC0 2 &pcfg_pull_none>; + <2 RK_PC0 2 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s2m0_mclk: i2s2m0-mclk { rockchip,pins = /* i2s2m0_mclk */ - <2 RK_PB6 2 &pcfg_pull_none>; + <2 RK_PB6 2 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s2m0_sclk: i2s2m0-sclk { rockchip,pins = /* i2s2m0_sclk */ - <2 RK_PB7 2 &pcfg_pull_none>; + <2 RK_PB7 2 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96722.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96722.dtsi new file mode 100644 index 000000000000..a17fb2a1eded --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96722.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + max96722_osc: max96722-oscillator { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <25000000>; + clock-output-names = "max96722-osc"; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_dphy0_in_max96722: endpoint@1 { + reg = <1>; + remote-endpoint = <&max96722_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m3_xfer>, <&max96722_errb>, <&max96722_lock>; + + max96722: max96722@29 { + compatible = "max96722"; + status = "okay"; + reg = <0x29>; + clock-names = "xvclk"; + clocks = <&max96722_osc 0>; + power-domains = <&power RK3588_PD_VI>; + rockchip,grf = <&sys_grf>; + power-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pocen-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + lock-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + link-mask = <0x0F>; + auto-init-deskew-mask = <0x03>; + frame-sync-period = <0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "max96722"; + rockchip,camera-module-lens-name = "max96722"; + + port { + max96722_out: endpoint { + remote-endpoint = <&mipi_dphy0_in_max96722>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in>; + }; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + /* parameters for do cif reset detecting: + * index0: monitor mode, + 0 for idle, + 1 for continue, + 2 for trigger, + 3 for hotplug (for nextchip) + * index1: the frame id to start timer, + min is 2 + * index2: frame num of monitoring cycle + * index3: err time for keep monitoring + after finding out err (ms) + * index4: csi2 err reference val for resetting + */ + rockchip,cif-monitor = <3 2 1 1000 5>; + + port { + cif_mipi2_in: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif { + status = "okay"; + rockchip,android-usb-camerahal-enable; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&pinctrl { + max96722 { + max96722_errb: max96722-errb { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + max96722_lock: max96722-lock { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v10.dts index 5f35db6bbc97..138d67b0a480 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v10.dts @@ -28,13 +28,13 @@ }; simple-audio-card,codec { - sound-dai = <&bt_sco>; + sound-dai = <&bt_sco 1>; }; }; bt_sco: bt-sco { compatible = "delta,dfbmcs320"; - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; status = "okay"; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dts b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dts index 30b3560f3485..8851802d9c88 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dts @@ -27,13 +27,13 @@ }; simple-audio-card,codec { - sound-dai = <&bt_sco>; + sound-dai = <&bt_sco 1>; }; }; bt_sco: bt-sco { compatible = "delta,dfbmcs320"; - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dtsi index e4e050ba5b42..bbec52d40db4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dtsi @@ -163,7 +163,7 @@ snps,reset-active-low; /* Reset time is 20ms, 100ms for rtl8211f */ snps,reset-delays-us = <0 20000 100000>; - pinctrl-names = "phydisb"; + pinctrl-names = "default"; pinctrl-0 = <&gmac0_miim &gmac0_tx_bus2 &gmac0_rx_bus2 diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dts b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dts index ae86128d0bf2..b80c003e7c64 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dts @@ -26,13 +26,13 @@ }; simple-audio-card,codec { - sound-dai = <&bt_sco>; + sound-dai = <&bt_sco 1>; }; }; bt_sco: bt-sco { compatible = "delta,dfbmcs320"; - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; status = "okay"; }; gpio-keys { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi index 60bb056ee26c..e08c45896e4c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi @@ -174,7 +174,7 @@ snps,reset-active-low; /* Reset time is 20ms, 100ms for rtl8211f */ snps,reset-delays-us = <0 20000 100000>; - pinctrl-names = "phydisb"; + pinctrl-names = "default"; pinctrl-0 = <&gmac0_miim &gmac0_tx_bus2 &gmac0_rx_bus2 diff --git a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi index 097c7ce386b7..7b084b273b27 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi @@ -7,37 +7,60 @@ #include "rk3588.dtsi" &cluster0_opp_table { - /delete-node/ opp-1608000000; - /delete-node/ opp-1704000000; - /delete-node/ opp-1800000000; + /* + * The Max frequency is 1296MHz in default normal mode. + * The Max frequency is 1704MHz in overdrive mode, + * but under the overdrive mode for a long time, + * the chipset may shorten the lifetime, + * especially in high temperature condition. + */ + /delete-node/ opp-j-m-1416000000; + /delete-node/ opp-j-m-1608000000; + /delete-node/ opp-j-m-1704000000; }; &cluster1_opp_table { - /delete-node/ opp-1800000000; - /delete-node/ opp-2016000000; - /delete-node/ opp-2208000000; - /delete-node/ opp-2256000000; - /delete-node/ opp-2304000000; - /delete-node/ opp-2352000000; - /delete-node/ opp-2400000000; + /* + * The Max frequency is 1608MHz in default normal mode. + * The Max frequency is 2016MHz in overdrive mode, + * but under the overdrive mode for a long time, + * the chipset may shorten the lifetime, + * especially in high temperature condition. + */ + /delete-node/ opp-j-m-1800000000; + /delete-node/ opp-j-m-2016000000; }; &cluster2_opp_table { - /delete-node/ opp-1800000000; - /delete-node/ opp-2016000000; - /delete-node/ opp-2208000000; - /delete-node/ opp-2256000000; - /delete-node/ opp-2304000000; - /delete-node/ opp-2352000000; - /delete-node/ opp-2400000000; + /* + * The Max frequency is 1608MHz in default normal mode. + * The Max frequency is 2016MHz in overdrive mode, + * but under the overdrive mode for a long time, + * the chipset may shorten the lifetime, + * especially in high temperature condition. + */ + /delete-node/ opp-j-m-1800000000; + /delete-node/ opp-j-m-2016000000; }; &gpu_opp_table { - /delete-node/ opp-900000000; - /delete-node/ opp-1000000000; + /* + * The Max frequency is 700MHz in default normal mode. + * The Max frequency is 850MHz in overdrive mode, + * but under the overdrive mode for a long time, + * the chipset may shorten the lifetime, + * especially in high temperature condition. + */ + /delete-node/ opp-j-850000000; }; &npu_opp_table { - /delete-node/ opp-900000000; - /delete-node/ opp-1000000000; + /* + * The Max frequency is 800MHz in default normal mode. + * The Max frequency is 950MHz in overdrive mode, + * but under the overdrive mode for a long time, + * the chipset may shorten the lifetime, + * especially in high temperature condition. + */ + /delete-node/ opp-j-m-950000000; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588m.dtsi b/arch/arm64/boot/dts/rockchip/rk3588m.dtsi index 1a30a0375033..38b9dbf38a21 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588m.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588m.dtsi @@ -5,23 +5,3 @@ */ #include "rk3588.dtsi" - -&cluster0_opp_table { - /delete-node/ opp-1800000000; -}; - -&cluster1_opp_table { - /delete-node/ opp-2208000000; - /delete-node/ opp-2256000000; - /delete-node/ opp-2304000000; - /delete-node/ opp-2352000000; - /delete-node/ opp-2400000000; -}; - -&cluster2_opp_table { - /delete-node/ opp-2208000000; - /delete-node/ opp-2256000000; - /delete-node/ opp-2304000000; - /delete-node/ opp-2352000000; - /delete-node/ opp-2400000000; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi index 6993ce6d82e5..c8a80600d439 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi @@ -1129,25 +1129,34 @@ }; i2s0 { + /omit-if-no-ref/ + i2s0_idle: i2s0-idle { + rockchip,pins = + /* i2s0_lrck_gpio */ + <1 RK_PC5 0 &pcfg_pull_none>, + /* i2s0_sclk_gpio */ + <1 RK_PC3 0 &pcfg_pull_none>; + }; + /omit-if-no-ref/ i2s0_lrck: i2s0-lrck { rockchip,pins = /* i2s0_lrck */ - <1 RK_PC5 1 &pcfg_pull_none>; + <1 RK_PC5 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s0_mclk: i2s0-mclk { rockchip,pins = /* i2s0_mclk */ - <1 RK_PC2 1 &pcfg_pull_none>; + <1 RK_PC2 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s0_sclk: i2s0-sclk { rockchip,pins = /* i2s0_sclk */ - <1 RK_PC3 1 &pcfg_pull_none>; + <1 RK_PC3 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ @@ -1212,21 +1221,21 @@ i2s1m0_lrck: i2s1m0-lrck { rockchip,pins = /* i2s1m0_lrck */ - <4 RK_PA2 3 &pcfg_pull_none>; + <4 RK_PA2 3 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1m0_mclk: i2s1m0-mclk { rockchip,pins = /* i2s1m0_mclk */ - <4 RK_PA0 3 &pcfg_pull_none>; + <4 RK_PA0 3 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1m0_sclk: i2s1m0-sclk { rockchip,pins = /* i2s1m0_sclk */ - <4 RK_PA1 3 &pcfg_pull_none>; + <4 RK_PA1 3 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ @@ -1288,21 +1297,21 @@ i2s1m1_lrck: i2s1m1-lrck { rockchip,pins = /* i2s1m1_lrck */ - <0 RK_PB7 1 &pcfg_pull_none>; + <0 RK_PB7 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1m1_mclk: i2s1m1-mclk { rockchip,pins = /* i2s1m1_mclk */ - <0 RK_PB5 1 &pcfg_pull_none>; + <0 RK_PB5 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s1m1_sclk: i2s1m1-sclk { rockchip,pins = /* i2s1m1_sclk */ - <0 RK_PB6 1 &pcfg_pull_none>; + <0 RK_PB6 1 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ @@ -1363,25 +1372,34 @@ }; i2s2 { + /omit-if-no-ref/ + i2s2m1_idle: i2s2m1-idle { + rockchip,pins = + /* i2s2m1_lrck_gpio */ + <3 RK_PB6 0 &pcfg_pull_none>, + /* i2s2m1_sclk_gpio */ + <3 RK_PB5 0 &pcfg_pull_none>; + }; + /omit-if-no-ref/ i2s2m1_lrck: i2s2m1-lrck { rockchip,pins = /* i2s2m1_lrck */ - <3 RK_PB6 3 &pcfg_pull_none>; + <3 RK_PB6 3 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s2m1_mclk: i2s2m1-mclk { rockchip,pins = /* i2s2m1_mclk */ - <3 RK_PB4 3 &pcfg_pull_none>; + <3 RK_PB4 3 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s2m1_sclk: i2s2m1-sclk { rockchip,pins = /* i2s2m1_sclk */ - <3 RK_PB5 3 &pcfg_pull_none>; + <3 RK_PB5 3 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ @@ -1400,25 +1418,34 @@ }; i2s3 { + /omit-if-no-ref/ + i2s3_idle: i2s3-idle { + rockchip,pins = + /* i2s3_lrck_gpio */ + <3 RK_PA2 0 &pcfg_pull_none>, + /* i2s3_sclk_gpio */ + <3 RK_PA1 0 &pcfg_pull_none>; + }; + /omit-if-no-ref/ i2s3_lrck: i2s3-lrck { rockchip,pins = /* i2s3_lrck */ - <3 RK_PA2 3 &pcfg_pull_none>; + <3 RK_PA2 3 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s3_mclk: i2s3-mclk { rockchip,pins = /* i2s3_mclk */ - <3 RK_PA0 3 &pcfg_pull_none>; + <3 RK_PA0 3 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ i2s3_sclk: i2s3-sclk { rockchip,pins = /* i2s3_sclk */ - <3 RK_PA1 3 &pcfg_pull_none>; + <3 RK_PA1 3 &pcfg_pull_none_smt>; }; /omit-if-no-ref/ @@ -1819,6 +1846,15 @@ <1 RK_PC4 3 &pcfg_pull_none>; }; + /omit-if-no-ref/ + pdm0m0_idle: pdm0m0-idle { + rockchip,pins = + /* pdm0m0_clk0_gpio */ + <1 RK_PC6 0 &pcfg_pull_none>, + /* pdm0m0_clk1_gpio */ + <1 RK_PC4 0 &pcfg_pull_none>; + }; + /omit-if-no-ref/ pdm0m0_sdi0: pdm0m0-sdi0 { rockchip,pins = @@ -1860,6 +1896,15 @@ <0 RK_PC4 2 &pcfg_pull_none>; }; + /omit-if-no-ref/ + pdm0m1_idle: pdm0m1-idle { + rockchip,pins = + /* pdm0m1_clk0_gpio */ + <0 RK_PC0 0 &pcfg_pull_none>, + /* pdm0m1_clk1_gpio */ + <0 RK_PC4 0 &pcfg_pull_none>; + }; + /omit-if-no-ref/ pdm0m1_sdi0: pdm0m1-sdi0 { rockchip,pins = @@ -1904,6 +1949,15 @@ <4 RK_PD4 2 &pcfg_pull_none>; }; + /omit-if-no-ref/ + pdm1m0_idle: pdm1m0-idle { + rockchip,pins = + /* pdm1m0_clk0_gpio */ + <4 RK_PD5 0 &pcfg_pull_none>, + /* pdm1m0_clk1_gpio */ + <4 RK_PD4 0 &pcfg_pull_none>; + }; + /omit-if-no-ref/ pdm1m0_sdi0: pdm1m0-sdi0 { rockchip,pins = @@ -1931,6 +1985,7 @@ /* pdm1m0_sdi3 */ <4 RK_PD0 2 &pcfg_pull_none>; }; + /omit-if-no-ref/ pdm1m1_clk: pdm1m1-clk { rockchip,pins = @@ -1945,6 +2000,15 @@ <1 RK_PB3 2 &pcfg_pull_none>; }; + /omit-if-no-ref/ + pdm1m1_idle: pdm1m1-idle { + rockchip,pins = + /* pdm1m1_clk0_gpio */ + <1 RK_PB4 0 &pcfg_pull_none>, + /* pdm1m1_clk1_gpio */ + <1 RK_PB3 0 &pcfg_pull_none>; + }; + /omit-if-no-ref/ pdm1m1_sdi0: pdm1m1-sdi0 { rockchip,pins = diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index b17929660e40..0c97ace62a95 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -346,6 +346,15 @@ rockchip,bit-set-to-disable; }; + mclkout_i2s1m1: mclkout-i2s1@fd58a000 { + compatible = "rockchip,clk-out"; + reg = <0 0xfd58a000 0 0x4>; + clocks = <&cru I2S1_8CH_MCLKOUT>; + #clock-cells = <0>; + clock-output-names = "i2s1m1_mclkout_to_io"; + rockchip,bit-shift = <6>; + }; + mclkout_i2s2: mclkout-i2s2@fd58c318 { compatible = "rockchip,clk-out"; reg = <0 0xfd58c318 0 0x4>; @@ -647,6 +656,16 @@ rockchip,supported-hw; rockchip,opp-shared-dsu; + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = < + 0 1365 0 + 1366 1387 1 + 1388 1409 2 + 1410 1431 3 + 1432 1453 4 + 1454 1475 5 + 1476 9999 6 + >; rockchip,pvtm-voltage-sel = < 0 1410 0 1411 1434 1 @@ -683,36 +702,37 @@ rockchip,high-temp = <85000>; rockchip,high-temp-max-freq = <1608000>; + /* RK3588 cluster0 OPPs */ opp-408000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <408000000>; opp-microvolt = <675000 675000 950000>, <675000 675000 950000>; clock-latency-ns = <40000>; }; opp-600000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <600000000>; opp-microvolt = <675000 675000 950000>, <675000 675000 950000>; clock-latency-ns = <40000>; }; opp-816000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <816000000>; opp-microvolt = <675000 675000 950000>, <675000 675000 950000>; clock-latency-ns = <40000>; }; opp-1008000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <675000 675000 950000>, <675000 675000 950000>; clock-latency-ns = <40000>; }; opp-1200000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <712500 712500 950000>, <712500 712500 950000>; @@ -731,7 +751,7 @@ clock-latency-ns = <40000>; }; opp-1416000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1416000000>; opp-microvolt = <762500 762500 950000>, <762500 762500 950000>; @@ -751,7 +771,7 @@ opp-suspend; }; opp-1608000000 { - opp-supported-hw = <0xfb 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1608000000>; opp-microvolt = <850000 850000 950000>, <850000 850000 950000>; @@ -769,25 +789,6 @@ <787500 787500 950000>; clock-latency-ns = <40000>; }; - opp-1704000000 { - opp-supported-hw = <0x02 0xffff>; - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <900000 900000 950000>, - <900000 900000 950000>; - opp-microvolt-L1 = <887500 887500 950000>, - <887500 887500 950000>; - opp-microvolt-L2 = <875000 875000 950000>, - <875000 875000 950000>; - opp-microvolt-L3 = <862500 862500 950000>, - <862500 862500 950000>; - opp-microvolt-L4 = <850000 850000 950000>, - <850000 850000 950000>; - opp-microvolt-L5 = <837500 837500 950000>, - <837500 837500 950000>; - opp-microvolt-L6 = <825000 825000 950000>, - <825000 825000 950000>; - clock-latency-ns = <40000>; - }; opp-1800000000 { opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1800000000>; @@ -807,6 +808,106 @@ <875000 875000 950000>; clock-latency-ns = <40000>; }; + + /* RK3588J/M cluster0 OPPs */ + opp-j-m-408000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-816000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1008000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1200000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-1296000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L0 = <775000 775000 950000>, + <775000 775000 950000>; + opp-microvolt-L1 = <762500 762500 950000>, + <762500 762500 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1416000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L0 = <787500 787500 950000>, + <787500 787500 950000>; + opp-microvolt-L1 = <775000 775000 950000>, + <775000 775000 950000>; + opp-microvolt-L2 = <762500 762500 950000>, + <762500 762500 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-j-m-1608000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <887500 887500 950000>, + <887500 887500 950000>; + opp-microvolt-L1 = <875000 875000 950000>, + <875000 875000 950000>; + opp-microvolt-L2 = <862500 862500 950000>, + <862500 862500 950000>; + opp-microvolt-L3 = <850000 850000 950000>, + <850000 850000 950000>; + opp-microvolt-L4 = <837500 837500 950000>, + <837500 837500 950000>; + opp-microvolt-L5 = <825000 825000 950000>, + <825000 825000 950000>; + opp-microvolt-L6 = <812500 812500 950000>, + <812500 812500 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1704000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <937500 937500 950000>, + <937500 937500 950000>; + opp-microvolt-L1 = <925000 925000 950000>, + <925000 925000 950000>; + opp-microvolt-L2 = <912500 912500 950000>, + <912500 912500 950000>; + opp-microvolt-L3 = <900000 900000 950000>, + <900000 900000 950000>; + opp-microvolt-L4 = <887500 887500 950000>, + <887500 887500 950000>; + opp-microvolt-L5 = <875000 875000 950000>, + <875000 875000 950000>; + opp-microvolt-L6 = <862500 862500 950000>, + <862500 862500 950000>; + clock-latency-ns = <40000>; + }; }; cluster1_opp_table: cluster1-opp-table { @@ -817,6 +918,17 @@ nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; rockchip,supported-hw; + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = < + 0 1539 0 + 1540 1564 1 + 1565 1589 2 + 1590 1614 3 + 1615 1644 4 + 1645 1674 5 + 1675 1704 6 + 1705 9999 7 + >; rockchip,pvtm-voltage-sel = < 0 1595 0 1596 1615 1 @@ -855,8 +967,9 @@ rockchip,high-temp = <85000>; rockchip,high-temp-max-freq = <2208000>; + /* RK3588 cluster1 OPPs */ opp-408000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <408000000>; opp-microvolt = <675000 675000 1000000>, <675000 675000 1000000>; @@ -864,35 +977,35 @@ opp-suspend; }; opp-600000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <600000000>; opp-microvolt = <675000 675000 1000000>, <675000 675000 1000000>; clock-latency-ns = <40000>; }; opp-816000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <816000000>; opp-microvolt = <675000 675000 1000000>, <675000 675000 1000000>; clock-latency-ns = <40000>; }; opp-1008000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <675000 675000 1000000>, <675000 675000 1000000>; clock-latency-ns = <40000>; }; opp-1200000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <675000 675000 1000000>, <675000 675000 1000000>; clock-latency-ns = <40000>; }; opp-1416000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1416000000>; opp-microvolt = <725000 725000 1000000>, <725000 725000 1000000>; @@ -911,7 +1024,7 @@ clock-latency-ns = <40000>; }; opp-1608000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1608000000>; opp-microvolt = <762500 762500 1000000>, <762500 762500 1000000>; @@ -930,7 +1043,7 @@ clock-latency-ns = <40000>; }; opp-1800000000 { - opp-supported-hw = <0xfb 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <850000 850000 1000000>, <850000 850000 1000000>; @@ -951,7 +1064,7 @@ clock-latency-ns = <40000>; }; opp-2016000000 { - opp-supported-hw = <0xfb 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <2016000000>; opp-microvolt = <925000 925000 1000000>, <925000 925000 1000000>; @@ -1020,6 +1133,114 @@ <1000000 1000000 1000000>; clock-latency-ns = <40000>; }; + + /* RK3588J/M cluster1 OPPs */ + opp-j-m-408000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-816000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1008000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1200000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1416000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L0 = <762500 762500 950000>, + <762500 762500 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-j-m-1608000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <787500 787500 950000>, + <787500 787500 950000>; + opp-microvolt-L2 = <775000 775000 950000>, + <775000 775000 950000>; + opp-microvolt-L3 = <762500 762500 950000>, + <762500 762500 950000>; + opp-microvolt-L4 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L5 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L6 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L7 = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1800000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <875000 875000 950000>, + <875000 875000 950000>; + opp-microvolt-L1 = <862500 862500 950000>, + <862500 862500 950000>; + opp-microvolt-L2 = <850000 850000 950000>, + <850000 850000 950000>; + opp-microvolt-L3 = <837500 837500 950000>, + <837500 837500 950000>; + opp-microvolt-L4 = <825000 825000 950000>, + <825000 825000 950000>; + opp-microvolt-L5 = <812500 812500 950000>, + <812500 812500 950000>; + opp-microvolt-L6 = <800000 800000 950000>, + <800000 800000 950000>; + opp-microvolt-L7 = <787500 787500 950000>, + <787500 787500 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-2016000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <950000 950000 950000>, + <950000 950000 950000>; + opp-microvolt-L1 = <950000 950000 950000>, + <950000 950000 950000>; + opp-microvolt-L2 = <937500 937500 950000>, + <937500 937500 950000>; + opp-microvolt-L3 = <925000 925000 950000>, + <925000 925000 950000>; + opp-microvolt-L4 = <912500 912500 950000>, + <912500 912500 950000>; + opp-microvolt-L5 = <900000 900000 950000>, + <900000 900000 950000>; + opp-microvolt-L6 = <887500 887500 950000>, + <887500 887500 950000>; + opp-microvolt-L7 = <875000 875000 950000>, + <875000 875000 950000>; + clock-latency-ns = <40000>; + }; }; cluster2_opp_table: cluster2-opp-table { @@ -1030,6 +1251,17 @@ nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; rockchip,supported-hw; + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = < + 0 1539 0 + 1540 1564 1 + 1565 1589 2 + 1590 1614 3 + 1615 1644 4 + 1645 1674 5 + 1675 1704 6 + 1705 9999 7 + >; rockchip,pvtm-voltage-sel = < 0 1595 0 1596 1615 1 @@ -1068,8 +1300,9 @@ rockchip,high-temp = <85000>; rockchip,high-temp-max-freq = <2208000>; + /* RK3588 cluster2 OPPs */ opp-408000000 { - opp-supported-hw = <0xff 0x0ffff>; + opp-supported-hw = <0xf9 0x0ffff>; opp-hz = /bits/ 64 <408000000>; opp-microvolt = <675000 675000 1000000>, <675000 675000 1000000>; @@ -1077,35 +1310,35 @@ opp-suspend; }; opp-600000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <600000000>; opp-microvolt = <675000 675000 1000000>, <675000 675000 1000000>; clock-latency-ns = <40000>; }; opp-816000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <816000000>; opp-microvolt = <675000 675000 1000000>, <675000 675000 1000000>; clock-latency-ns = <40000>; }; opp-1008000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <675000 675000 1000000>, <675000 675000 1000000>; clock-latency-ns = <40000>; }; opp-1200000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <675000 675000 1000000>, <675000 675000 1000000>; clock-latency-ns = <40000>; }; opp-1416000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1416000000>; opp-microvolt = <725000 725000 1000000>, <725000 725000 1000000>; @@ -1124,7 +1357,7 @@ clock-latency-ns = <40000>; }; opp-1608000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1608000000>; opp-microvolt = <762500 762500 1000000>, <762500 762500 1000000>; @@ -1143,7 +1376,7 @@ clock-latency-ns = <40000>; }; opp-1800000000 { - opp-supported-hw = <0xfb 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <850000 850000 1000000>, <850000 850000 1000000>; @@ -1164,7 +1397,7 @@ clock-latency-ns = <40000>; }; opp-2016000000 { - opp-supported-hw = <0xfb 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <2016000000>; opp-microvolt = <925000 925000 1000000>, <925000 925000 1000000>; @@ -1229,6 +1462,114 @@ <1000000 1000000 1000000>; clock-latency-ns = <40000>; }; + + /* RK3588J/M cluster2 OPPs */ + opp-j-m-408000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-816000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1008000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1200000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1416000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L0 = <762500 762500 950000>, + <762500 762500 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-j-m-1608000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <787500 787500 950000>, + <787500 787500 950000>; + opp-microvolt-L2 = <775000 775000 950000>, + <775000 775000 950000>; + opp-microvolt-L3 = <762500 762500 950000>, + <762500 762500 950000>; + opp-microvolt-L4 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L5 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L6 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L7 = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1800000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <875000 875000 950000>, + <875000 875000 950000>; + opp-microvolt-L1 = <862500 862500 950000>, + <862500 862500 950000>; + opp-microvolt-L2 = <850000 850000 950000>, + <850000 850000 950000>; + opp-microvolt-L3 = <837500 837500 950000>, + <837500 837500 950000>; + opp-microvolt-L4 = <825000 825000 950000>, + <825000 825000 950000>; + opp-microvolt-L5 = <812500 812500 950000>, + <812500 812500 950000>; + opp-microvolt-L6 = <800000 800000 950000>, + <800000 800000 950000>; + opp-microvolt-L7 = <787500 787500 950000>, + <787500 787500 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-2016000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <950000 950000 950000>, + <950000 950000 950000>; + opp-microvolt-L1 = <950000 950000 950000>, + <950000 950000 950000>; + opp-microvolt-L2 = <937500 937500 950000>, + <937500 937500 950000>; + opp-microvolt-L3 = <925000 925000 950000>, + <925000 925000 950000>; + opp-microvolt-L4 = <912500 912500 950000>, + <912500 912500 950000>; + opp-microvolt-L5 = <900000 900000 950000>, + <900000 900000 950000>; + opp-microvolt-L6 = <887500 887500 950000>, + <887500 887500 950000>; + opp-microvolt-L7 = <875000 875000 950000>, + <875000 875000 950000>; + clock-latency-ns = <40000>; + }; }; arm_pmu: arm-pmu { @@ -1379,8 +1720,10 @@ dmc_opp_table: dmc-opp-table { compatible = "operating-points-v2"; - nvmem-cells = <&log_leakage>, <&dmc_opp_info>; - nvmem-cell-names = "leakage", "opp-info"; + nvmem-cells = <&log_leakage>, <&dmc_opp_info>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; + rockchip,supported-hw; + rockchip,leakage-voltage-sel = < 1 31 0 32 44 1 @@ -1391,7 +1734,9 @@ rockchip,low-temp = <10000>; rockchip,low-temp-min-volt = <750000>; + /* RK3588 dmc OPPs */ opp-528000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <528000000>; opp-microvolt = <675000 675000 875000>, <725000 725000 750000>; @@ -1403,6 +1748,7 @@ <675000 675000 750000>; }; opp-1068000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1068000000>; opp-microvolt = <725000 725000 875000>, <737500 737500 750000>; @@ -1414,6 +1760,7 @@ <687500 687500 750000>; }; opp-1560000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1560000000>; opp-microvolt = <800000 800000 875000>, <750000 750000 750000>; @@ -1425,6 +1772,7 @@ <700000 700000 750000>; }; opp-2750000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <2750000000>; opp-microvolt = <875000 875000 875000>, <750000 750000 750000>; @@ -1435,6 +1783,44 @@ opp-microvolt-L3 = <825000 820000 875000>, <700000 700000 750000>; }; + + /* RK3588J/M dmc OPPs */ + opp-j-m-528000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <528000000>; + opp-microvolt = <750000 750000 875000>, + <750000 750000 750000>; + }; + opp-j-m-1068000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1068000000>; + opp-microvolt = <750000 750000 875000>, + <750000 750000 750000>; + }; + opp-j-m-1560000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1560000000>; + opp-microvolt = <800000 800000 875000>, + <750000 750000 750000>; + opp-microvolt-L1 = <775000 775000 875000>, + <750000 750000 750000>; + opp-microvolt-L2 = <750000 750000 875000>, + <750000 750000 750000>; + opp-microvolt-L3 = <750000 750000 875000>, + <750000 750000 750000>; + }; + opp-j-m-2750000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <2750000000>; + opp-microvolt = <875000 875000 875000>, + <750000 750000 750000>; + opp-microvolt-L1 = <850000 850000 875000>, + <750000 750000 750000>; + opp-microvolt-L2 = <837500 837500 875000>, + <750000 750000 750000>; + opp-microvolt-L3 = <825000 820000 875000>, + <750000 750000 750000>; + }; }; firmware { @@ -1912,6 +2298,15 @@ nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; rockchip,supported-hw; + rockchip,pvtm-hw = <0x04>; + rockchip,pvtm-voltage-sel-hw = < + 0 799 0 + 800 819 1 + 820 844 2 + 845 869 3 + 870 894 4 + 895 9999 5 + >; rockchip,pvtm-voltage-sel = < 0 815 0 816 835 1 @@ -1947,32 +2342,33 @@ rockchip,high-temp = <85000>; rockchip,high-temp-max-freq = <800000>; + /* RK3588 gpu OPPs */ opp-300000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <300000000>; opp-microvolt = <675000 675000 850000>, <675000 675000 850000>; }; opp-400000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <400000000>; opp-microvolt = <675000 675000 850000>, <675000 675000 850000>; }; opp-500000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <500000000>; opp-microvolt = <675000 675000 850000>, <675000 675000 850000>; }; opp-600000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <600000000>; opp-microvolt = <675000 675000 850000>, <675000 675000 850000>; }; opp-700000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <700000000>; opp-microvolt = <700000 700000 850000>, <700000 700000 850000>; @@ -1986,7 +2382,7 @@ <675000 675000 850000>; }; opp-800000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <800000000>; opp-microvolt = <750000 750000 850000>, <750000 750000 850000>; @@ -2002,7 +2398,7 @@ <700000 700000 850000>; }; opp-900000000 { - opp-supported-hw = <0xfb 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <900000000>; opp-microvolt = <800000 800000 850000>, <800000 800000 850000>; @@ -2018,7 +2414,95 @@ <737500 737500 850000>; }; opp-1000000000 { - opp-supported-hw = <0xfb 0xffff>; + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <850000 850000 850000>, + <850000 850000 850000>; + opp-microvolt-L1 = <837500 837500 850000>, + <837500 837500 850000>; + opp-microvolt-L2 = <825000 825000 850000>, + <825000 825000 850000>; + opp-microvolt-L3 = <812500 812500 850000>, + <812500 812500 850000>; + opp-microvolt-L4 = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L5 = <787500 787500 850000>, + <787500 787500 850000>; + }; + + /* RK3588J/M gpu OPPs */ + opp-j-m-300000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-400000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-500000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-700000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + /* RK3588J gpu OPPs */ + opp-j-850000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <850000000>; + opp-microvolt = <787500 787500 850000>, + <787500 787500 850000>; + opp-microvolt-L1 = <775000 775000 850000>, + <775000 775000 850000>; + opp-microvolt-L2 = <762500 762500 850000>, + <762500 762500 850000>; + opp-microvolt-L3 = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L4 = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L5 = <750000 750000 850000>, + <750000 750000 850000>; + }; + /* RK3588M gpu OPPs */ + opp-m-800000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-m-900000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L1 = <787500 787500 850000>, + <787500 787500 850000>; + opp-microvolt-L2 = <775000 775000 850000>, + <775000 775000 850000>; + opp-microvolt-L3 = <762500 762500 850000>, + <762500 762500 850000>; + opp-microvolt-L4 = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L5 = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-m-1000000000 { + opp-supported-hw = <0x02 0xffff>; opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <850000 850000 850000>, <850000 850000 850000>; @@ -2901,6 +3385,15 @@ nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; rockchip,supported-hw; + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = < + 0 799 0 + 800 819 1 + 820 844 2 + 845 869 3 + 870 894 4 + 895 9999 5 + >; rockchip,pvtm-voltage-sel = < 0 815 0 816 835 1 @@ -2937,8 +3430,9 @@ rockchip,high-temp = <85000>; rockchip,high-temp-max-freq = <800000>; + /* RK3588 npu OPPs */ opp-300000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <300000000>; opp-microvolt = <700000 700000 850000>, <700000 700000 850000>; @@ -2954,7 +3448,7 @@ <675000 675000 850000>; }; opp-400000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <400000000>; opp-microvolt = <700000 700000 850000>, <700000 700000 850000>; @@ -2970,7 +3464,7 @@ <675000 675000 850000>; }; opp-500000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <500000000>; opp-microvolt = <700000 700000 850000>, <700000 700000 850000>; @@ -2986,7 +3480,7 @@ <675000 675000 850000>; }; opp-600000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <600000000>; opp-microvolt = <700000 700000 850000>, <700000 700000 850000>; @@ -3002,7 +3496,7 @@ <675000 675000 850000>; }; opp-700000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <700000000>; opp-microvolt = <700000 700000 850000>, <700000 700000 850000>; @@ -3014,7 +3508,7 @@ <675000 675000 850000>; }; opp-800000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <800000000>; opp-microvolt = <750000 750000 850000>, <750000 750000 850000>; @@ -3028,7 +3522,7 @@ <700000 700000 850000>; }; opp-900000000 { - opp-supported-hw = <0xfb 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <900000000>; opp-microvolt = <800000 800000 850000>, <800000 800000 850000>; @@ -3044,7 +3538,7 @@ <737500 737500 850000>; }; opp-1000000000 { - opp-supported-hw = <0xfb 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <850000 850000 850000>, <850000 850000 850000>; @@ -3059,6 +3553,60 @@ opp-microvolt-L5 = <787500 787500 850000>, <787500 787500 850000>; }; + + /* RK3588J/M npu OPPs */ + opp-j-m-300000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-400000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-500000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-700000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-800000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-950000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <837500 837500 850000>, + <837500 837500 850000>; + opp-microvolt-L1 = <825000 825000 850000>, + <825000 825000 850000>; + opp-microvolt-L2 = <812500 812500 850000>, + <812500 812500 850000>; + opp-microvolt-L3 = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L4 = <787500 787500 850000>, + <787500 787500 850000>; + opp-microvolt-L5 = <775000 775000 850000>, + <775000 775000 850000>; + }; }; rknpu_mmu: iommu@fdab9000 { @@ -3960,7 +4508,7 @@ "dclk_src_vp1", "dclk_src_vp2"; assigned-clocks = <&cru ACLK_VOP>; - assigned-clock-rates = <500000000>; + assigned-clock-rates = <750000000>; resets = <&cru SRST_A_VOP>, <&cru SRST_H_VOP>, <&cru SRST_D_VOP0>, @@ -5030,17 +5578,16 @@ resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; reset-names = "tx-m", "rx-m"; rockchip,clk-trcm = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 + pinctrl-names = "default", "idle", "clk"; + pinctrl-0 = <&i2s0_sdi0 &i2s0_sdi1 &i2s0_sdi2 &i2s0_sdi3 &i2s0_sdo0 - &i2s0_sdo1 - &i2s0_sdo2 - &i2s0_sdo3>; + &i2s0_sdo1>; + pinctrl-1 = <&i2s0_idle>; + pinctrl-2 = <&i2s0_lrck + &i2s0_sclk>; #sound-dai-cells = <0>; status = "disabled"; }; @@ -5083,11 +5630,12 @@ dma-names = "tx", "rx"; power-domains = <&power RK3588_PD_AUDIO>; rockchip,clk-trcm = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2m1_lrck - &i2s2m1_sclk - &i2s2m1_sdi + pinctrl-names = "default", "idle", "clk"; + pinctrl-0 = <&i2s2m1_sdi &i2s2m1_sdo>; + pinctrl-1 = <&i2s2m1_idle>; + pinctrl-2 = <&i2s2m1_lrck + &i2s2m1_sclk>; #sound-dai-cells = <0>; status = "disabled"; }; @@ -5104,11 +5652,12 @@ dma-names = "tx", "rx"; power-domains = <&power RK3588_PD_AUDIO>; rockchip,clk-trcm = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s3_lrck - &i2s3_sclk - &i2s3_sdi + pinctrl-names = "default", "idle", "clk"; + pinctrl-0 = <&i2s3_sdi &i2s3_sdo>; + pinctrl-1 = <&i2s3_idle>; + pinctrl-2 = <&i2s3_lrck + &i2s3_sclk>; #sound-dai-cells = <0>; status = "disabled"; }; @@ -5120,13 +5669,14 @@ clock-names = "pdm_clk", "pdm_hclk"; dmas = <&dmac0 4>; dma-names = "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pdm0m0_clk - &pdm0m0_clk1 - &pdm0m0_sdi0 + pinctrl-names = "default", "idle", "clk"; + pinctrl-0 = <&pdm0m0_sdi0 &pdm0m0_sdi1 &pdm0m0_sdi2 &pdm0m0_sdi3>; + pinctrl-1 = <&pdm0m0_idle>; + pinctrl-2 = <&pdm0m0_clk + &pdm0m0_clk1>; #sound-dai-cells = <0>; status = "disabled"; }; @@ -5141,13 +5691,14 @@ dmas = <&dmac1 4>; dma-names = "rx"; power-domains = <&power RK3588_PD_AUDIO>; - pinctrl-names = "default"; - pinctrl-0 = <&pdm1m0_clk - &pdm1m0_clk1 - &pdm1m0_sdi0 + pinctrl-names = "default", "idle", "clk"; + pinctrl-0 = <&pdm1m0_sdi0 &pdm1m0_sdi1 &pdm1m0_sdi2 &pdm1m0_sdi3>; + pinctrl-1 = <&pdm1m0_idle>; + pinctrl-2 = <&pdm1m0_clk + &pdm1m0_clk1>; #sound-dai-cells = <0>; status = "disabled"; }; diff --git a/arch/arm64/configs/rockchip_defconfig b/arch/arm64/configs/rockchip_defconfig index 73aff1df33c6..bfd0b41c567d 100644 --- a/arch/arm64/configs/rockchip_defconfig +++ b/arch/arm64/configs/rockchip_defconfig @@ -689,6 +689,7 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_ROCKCHIP=y CONFIG_SND_SOC_ROCKCHIP_I2S=y CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y +CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES=y CONFIG_SND_SOC_ROCKCHIP_PDM=y CONFIG_SND_SOC_ROCKCHIP_SAI=y CONFIG_SND_SOC_ROCKCHIP_SPDIF=y diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c index 954386a2b500..47247893df5f 100644 --- a/drivers/ata/libahci.c +++ b/drivers/ata/libahci.c @@ -1508,7 +1508,7 @@ int ahci_do_softreset(struct ata_link *link, unsigned int *class, *class = ahci_dev_classify(ap); /* re-enable FBS if disabled before */ - if (fbs_disabled) + if (fbs_disabled || (!ata_is_host_link(link) && pp->fbs_supported)) ahci_enable_fbs(ap); return 0; diff --git a/drivers/devfreq/rockchip_dmc.c b/drivers/devfreq/rockchip_dmc.c index 2ec4339a7a97..e6a1be78b64a 100644 --- a/drivers/devfreq/rockchip_dmc.c +++ b/drivers/devfreq/rockchip_dmc.c @@ -3004,6 +3004,10 @@ static void rockchip_dmcfreq_parse_dt(struct rockchip_dmcfreq *dmcfreq) if (rockchip_get_rl_map_talbe(np, "vop-pn-msch-readlatency", &dmcfreq->info.vop_pn_rl_tbl)) dev_err(dev, "failed to get vop pn to msch rl\n"); + if (dmcfreq->video_4k_rate) + dmcfreq->info.vop_4k_rate = dmcfreq->video_4k_rate; + else if (dmcfreq->video_4k_10b_rate) + dmcfreq->info.vop_4k_rate = dmcfreq->video_4k_10b_rate; of_property_read_u32(np, "touchboost_duration", (u32 *)&dmcfreq->touchboostpulse_duration_val); diff --git a/drivers/devfreq/rockchip_dmc_common.c b/drivers/devfreq/rockchip_dmc_common.c index cacc7d02f6fc..bb658ebd644d 100644 --- a/drivers/devfreq/rockchip_dmc_common.c +++ b/drivers/devfreq/rockchip_dmc_common.c @@ -85,9 +85,9 @@ void rockchip_dmcfreq_vop_bandwidth_update(struct dmcfreq_vop_info *vop_info) if (!common_info) return; - dev_dbg(common_info->dev, "line bw=%u, frame bw=%u, pn=%u\n", + dev_dbg(common_info->dev, "line bw=%u, frame bw=%u, pn=%u, pn_4k=%u\n", vop_info->line_bw_mbyte, vop_info->frame_bw_mbyte, - vop_info->plane_num); + vop_info->plane_num, vop_info->plane_num_4k); if (!common_info->vop_pn_rl_tbl || !common_info->set_msch_readlatency) goto vop_bw_tbl; @@ -129,6 +129,9 @@ vop_frame_bw_tbl: } next: + if (vop_info->plane_num_4k && target < common_info->vop_4k_rate) + target = common_info->vop_4k_rate; + vop_last_rate = common_info->vop_req_rate; common_info->vop_req_rate = target; diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c index 817f98c45d63..eea85ec5d1f4 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c @@ -274,8 +274,6 @@ struct dw_mipi_dsi2 { struct rockchip_drm_sub_dev sub_dev; struct gpio_desc *te_gpio; - bool user_split_mode; - struct drm_property *user_split_mode_prop; }; static inline struct dw_mipi_dsi2 *host_to_dsi2(struct mipi_dsi_host *host) @@ -1218,21 +1216,6 @@ static int dw_mipi_dsi2_register_sub_dev(struct dw_mipi_dsi2 *dsi2, struct drm_connector *connector) { struct device *dev = dsi2->dev; - struct drm_property *prop; - int ret; - - prop = drm_property_create_bool(dsi2->drm_dev, DRM_MODE_PROP_IMMUTABLE, - "USER_SPLIT_MODE"); - if (!prop) { - ret = -EINVAL; - DRM_DEV_ERROR(dev, "create user split mode prop failed\n"); - goto connector_cleanup; - } - - dsi2->user_split_mode_prop = prop; - drm_object_attach_property(&connector->base, - dsi2->user_split_mode_prop, - dsi2->user_split_mode ? 1 : 0); dsi2->sub_dev.connector = connector; dsi2->sub_dev.of_node = dev->of_node; @@ -1240,11 +1223,6 @@ static int dw_mipi_dsi2_register_sub_dev(struct dw_mipi_dsi2 *dsi2, rockchip_drm_register_sub_dev(&dsi2->sub_dev); return 0; - -connector_cleanup: - connector->funcs->destroy(connector); - - return ret; } static int dw_mipi_dsi2_bind(struct device *dev, struct device *master, @@ -1562,7 +1540,6 @@ static int dw_mipi_dsi2_probe(struct platform_device *pdev) dsi2->id = id; dsi2->pdata = of_device_get_match_data(dev); platform_set_drvdata(pdev, dsi2); - dsi2->user_split_mode = device_property_read_bool(dev, "user-split-mode"); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); regs = devm_ioremap_resource(dev, res); diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index d97a5d61c29a..865a7f461b2b 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -201,7 +201,6 @@ struct rockchip_hdmi { u8 id; bool hpd_stat; bool is_hdmi_qp; - bool user_split_mode; unsigned long bus_format; unsigned long output_bus_format; @@ -219,7 +218,6 @@ struct rockchip_hdmi { struct drm_property *next_hdr_sink_data_property; struct drm_property *output_hdmi_dvi; struct drm_property *output_type_capacity; - struct drm_property *user_split_mode_prop; struct drm_property *allm_capacity; struct drm_property *allm_enable; @@ -2730,14 +2728,6 @@ dw_hdmi_rockchip_attach_properties(struct drm_connector *connector, drm_object_attach_property(&connector->base, prop, 0); } - prop = drm_property_create_bool(connector->dev, DRM_MODE_PROP_IMMUTABLE, - "USER_SPLIT_MODE"); - if (prop) { - hdmi->user_split_mode_prop = prop; - drm_object_attach_property(&connector->base, prop, - hdmi->user_split_mode ? 1 : 0); - } - prop = drm_property_create_bool(connector->dev, 0, "allm_capacity"); if (prop) { hdmi->allm_capacity = prop; @@ -2854,12 +2844,6 @@ dw_hdmi_rockchip_destroy_properties(struct drm_connector *connector, hdmi->output_type_capacity = NULL; } - if (hdmi->user_split_mode_prop) { - drm_property_destroy(connector->dev, - hdmi->user_split_mode_prop); - hdmi->user_split_mode_prop = NULL; - } - if (hdmi->allm_capacity) { drm_property_destroy(connector->dev, hdmi->allm_capacity); @@ -3001,9 +2985,6 @@ dw_hdmi_rockchip_get_property(struct drm_connector *connector, else *val = dw_hdmi_qp_get_output_type_cap(hdmi->hdmi_qp); return 0; - } else if (property == hdmi->user_split_mode_prop) { - *val = hdmi->user_split_mode; - return 0; } else if (property == hdmi->allm_capacity) { *val = !!(hdmi->add_func & SUPPORT_HDMI_ALLM); return 0; @@ -3516,12 +3497,6 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, if (!secondary->plat_data->first_screen) plat_data->first_screen = true; } - - if (device_property_read_bool(dev, "user-split-mode") || - device_property_read_bool(secondary->dev, "user-split-mode")) { - hdmi->user_split_mode = true; - secondary->user_split_mode = true; - } } if (!plat_data->first_screen) { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c index cf7a043dcbae..1921b526f58d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c @@ -1297,6 +1297,12 @@ static void rockchip_drm_debugfs_init(struct drm_minor *minor) } #endif +static const struct drm_prop_enum_list split_area[] = { + { ROCKCHIP_DRM_SPLIT_UNSET, "UNSET" }, + { ROCKCHIP_DRM_SPLIT_LEFT_SIDE, "LEFT" }, + { ROCKCHIP_DRM_SPLIT_RIGHT_SIDE, "RIGHT" }, +}; + static int rockchip_drm_create_properties(struct drm_device *dev) { struct drm_property *prop; @@ -1332,6 +1338,11 @@ static int rockchip_drm_create_properties(struct drm_device *dev) return -ENOMEM; private->connector_id_prop = prop; + prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM, "SPLIT_AREA", + split_area, + ARRAY_SIZE(split_area)); + private->split_area_prop = prop; + prop = drm_property_create_object(dev, DRM_MODE_PROP_ATOMIC | DRM_MODE_PROP_IMMUTABLE, "SOC_ID", DRM_MODE_OBJECT_CRTC); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h index f0723c37fcdf..2a7ff11bcb61 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h @@ -110,6 +110,12 @@ enum rockchip_color_bar_mode { ROCKCHIP_COLOR_BAR_VERTICAL = 2, }; +enum rockchip_drm_split_area { + ROCKCHIP_DRM_SPLIT_UNSET = 0, + ROCKCHIP_DRM_SPLIT_LEFT_SIDE = 1, + ROCKCHIP_DRM_SPLIT_RIGHT_SIDE = 2, +}; + struct rockchip_drm_sub_dev { struct list_head list; struct drm_connector *connector; @@ -260,6 +266,7 @@ struct rockchip_crtc_state { int afbdc_win_yoffset; int dsp_layer_sel; u32 output_if; + u32 output_if_left_panel; u32 bus_format; u32 bus_flags; int yuv_overlay; @@ -433,7 +440,7 @@ struct next_hdr_sink_data { * @wait_vact_end: wait the last active line. */ struct rockchip_crtc_funcs { - int (*loader_protect)(struct drm_crtc *crtc, bool on); + int (*loader_protect)(struct drm_crtc *crtc, bool on, void *data); int (*enable_vblank)(struct drm_crtc *crtc); void (*disable_vblank)(struct drm_crtc *crtc); size_t (*bandwidth)(struct drm_crtc *crtc, @@ -498,6 +505,7 @@ struct rockchip_drm_private { /* private connector prop */ struct drm_property *connector_id_prop; + struct drm_property *split_area_prop; const struct rockchip_crtc_funcs *crtc_funcs[ROCKCHIP_MAX_CRTC]; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c index e52362142bdb..0e8033412109 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c @@ -164,6 +164,7 @@ static int rockchip_drm_bandwidth_atomic_check(struct drm_device *dev, vop_bw_info->line_bw_mbyte = 0; vop_bw_info->frame_bw_mbyte = 0; vop_bw_info->plane_num = 0; + vop_bw_info->plane_num_4k = 0; for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) { funcs = priv->crtc_funcs[drm_crtc_index(crtc)]; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_logo.c b/drivers/gpu/drm/rockchip/rockchip_drm_logo.c index 4278a7bd9f23..357b20b9fdfb 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_logo.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_logo.c @@ -376,6 +376,69 @@ get_framebuffer_by_node(struct drm_device *drm_dev, struct device_node *node) return rockchip_drm_logo_fb_alloc(drm_dev, &mode_cmd, private->logo); } +static void of_parse_post_csc_info(struct device_node *route, struct rockchip_drm_mode_set *set) +{ + int val; + + if (!of_property_read_u32(route, "post-csc,enable", &val)) + set->csc.csc_enable = val; + else + set->csc.csc_enable = 0; + + if (!set->csc.csc_enable) + return; + + if (!of_property_read_u32(route, "post-csc,hue", &val)) + set->csc.hue = val; + else + set->csc.hue = 256; + + if (!of_property_read_u32(route, "post-csc,saturation", &val)) + set->csc.saturation = val; + else + set->csc.saturation = 256; + + if (!of_property_read_u32(route, "post-csc,contrast", &val)) + set->csc.contrast = val; + else + set->csc.contrast = 256; + + if (!of_property_read_u32(route, "post-csc,brightness", &val)) + set->csc.brightness = val; + else + set->csc.brightness = 256; + + if (!of_property_read_u32(route, "post-csc,r-gain", &val)) + set->csc.r_gain = val; + else + set->csc.r_gain = 256; + + if (!of_property_read_u32(route, "post-csc,g-gain", &val)) + set->csc.g_gain = val; + else + set->csc.g_gain = 256; + + if (!of_property_read_u32(route, "post-csc,b-gain", &val)) + set->csc.b_gain = val; + else + set->csc.b_gain = 256; + + if (!of_property_read_u32(route, "post-csc,r-offset", &val)) + set->csc.r_offset = val; + else + set->csc.r_offset = 256; + + if (!of_property_read_u32(route, "post-csc,g-offset", &val)) + set->csc.g_offset = val; + else + set->csc.g_offset = 256; + + if (!of_property_read_u32(route, "post-csc,b-offset", &val)) + set->csc.b_offset = val; + else + set->csc.b_offset = 256; +} + static struct rockchip_drm_mode_set * of_parse_display_resource(struct drm_device *drm_dev, struct device_node *route) { @@ -470,6 +533,8 @@ of_parse_display_resource(struct drm_device *drm_dev, struct device_node *route) else set->hue = 50; + of_parse_post_csc_info(route, set); + set->force_output = of_property_read_bool(route, "force-output"); if (!of_property_read_u32(route, "cubic_lut,offset", &val)) { @@ -746,7 +811,7 @@ static int setup_initial_state(struct drm_device *drm_dev, if (priv->crtc_funcs[pipe] && priv->crtc_funcs[pipe]->loader_protect) - priv->crtc_funcs[pipe]->loader_protect(crtc, true); + priv->crtc_funcs[pipe]->loader_protect(crtc, true, &set->csc); } if (!set->fb) { @@ -798,7 +863,7 @@ static int setup_initial_state(struct drm_device *drm_dev, error_crtc: if (priv->crtc_funcs[pipe] && priv->crtc_funcs[pipe]->loader_protect) - priv->crtc_funcs[pipe]->loader_protect(crtc, false); + priv->crtc_funcs[pipe]->loader_protect(crtc, false, NULL); error_conn: if (set->sub_dev->loader_protect) set->sub_dev->loader_protect(conn_state->best_encoder, false); @@ -994,11 +1059,12 @@ void rockchip_drm_show_logo(struct drm_device *drm_dev) unset); if (priv->crtc_funcs[pipe] && priv->crtc_funcs[pipe]->loader_protect) - priv->crtc_funcs[pipe]->loader_protect(crtc, true); + priv->crtc_funcs[pipe]->loader_protect(crtc, true, + &set->csc); priv->crtc_funcs[pipe]->crtc_close(crtc); if (priv->crtc_funcs[pipe] && priv->crtc_funcs[pipe]->loader_protect) - priv->crtc_funcs[pipe]->loader_protect(crtc, false); + priv->crtc_funcs[pipe]->loader_protect(crtc, false, NULL); } } diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_logo.h b/drivers/gpu/drm/rockchip/rockchip_drm_logo.h index 1b0b239e86d8..7e1b1d2dfdf4 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_logo.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_logo.h @@ -7,12 +7,15 @@ #ifndef ROCKCHIP_DRM_LOGO_H #define ROCKCHIP_DRM_LOGO_H +#include "rockchip_drm_vop.h" + struct rockchip_drm_mode_set { struct list_head head; struct drm_framebuffer *fb; struct rockchip_drm_sub_dev *sub_dev; struct drm_crtc *crtc; struct drm_display_mode *mode; + struct post_csc csc; int clock; int hdisplay; int vdisplay; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 9a1b1a608d80..7a64cb6b7e8f 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -2639,7 +2639,7 @@ static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc, spin_unlock_irqrestore(&drm->event_lock, flags); } -static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on) +static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on, void *data) { struct rockchip_drm_private *private = crtc->dev->dev_private; struct vop *vop = to_vop(crtc); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index b37da66dd403..4b0dc1621961 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -31,11 +31,15 @@ #define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023) #define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786) +/* register one connector */ #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0) +/* register one connector */ #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1) #define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2) /* MIPI DSI DataStream(cmd) mode on rk3588 */ #define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3) +/* register two connector */ +#define ROCKCHIP_OUTPUT_DUAL_CONNECTOR_SPLIT_MODE BIT(4) #define AFBDC_FMT_RGB565 0x0 #define AFBDC_FMT_U8U8U8U8 0x5 diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index c8e33eb00509..f274f75ad8f8 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -4362,8 +4362,11 @@ static void vop2_crtc_atomic_disable(struct drm_crtc *crtc, if (vp->output_if & VOP_OUTPUT_IF_eDP0) VOP_GRF_SET(vop2, grf, grf_edp0_en, 0); - if (vp->output_if & VOP_OUTPUT_IF_eDP1) + if (vp->output_if & VOP_OUTPUT_IF_eDP1) { VOP_GRF_SET(vop2, grf, grf_edp1_en, 0); + if (dual_channel) + VOP_CTRL_SET(vop2, edp_dual_en, 0); + } if (vp->output_if & VOP_OUTPUT_IF_HDMI0) { VOP_GRF_SET(vop2, grf, grf_hdmi0_dsc_en, 0); @@ -4373,8 +4376,16 @@ static void vop2_crtc_atomic_disable(struct drm_crtc *crtc, if (vp->output_if & VOP_OUTPUT_IF_HDMI1) { VOP_GRF_SET(vop2, grf, grf_hdmi1_dsc_en, 0); VOP_GRF_SET(vop2, grf, grf_hdmi1_en, 0); + if (dual_channel) + VOP_CTRL_SET(vop2, hdmi_dual_en, 0); } + if ((vcstate->output_if & VOP_OUTPUT_IF_DP1) && dual_channel) + VOP_CTRL_SET(vop2, dp_dual_en, 0); + + if ((vcstate->output_if & VOP_OUTPUT_IF_MIPI1) && dual_channel) + VOP_CTRL_SET(vop2, mipi_dual_en, 0); + VOP_MODULE_SET(vop2, vp, dual_channel_en, 0); VOP_MODULE_SET(vop2, vp, dual_channel_swap, 0); @@ -5878,7 +5889,58 @@ static void vop2_crtc_disable_line_flag_event(struct drm_crtc *crtc) spin_unlock_irqrestore(&vop2->irq_lock, flags); } -static int vop2_crtc_loader_protect(struct drm_crtc *crtc, bool on) +static int vop2_crtc_get_inital_acm_info(struct drm_crtc *crtc) +{ + struct vop2_video_port *vp = to_vop2_video_port(crtc); + struct vop2 *vop2 = vp->vop2; + struct post_acm *acm = &vp->acm_info; + s16 *lut_y; + s16 *lut_h; + s16 *lut_s; + u32 value; + int i; + + value = readl(vop2->acm_regs + RK3528_ACM_CTRL); + acm->acm_enable = value & 0x1; + value = readl(vop2->acm_regs + RK3528_ACM_DELTA_RANGE); + acm->y_gain = value & 0x3ff; + acm->h_gain = (value >> 10) & 0x3ff; + acm->s_gain = (value >> 20) & 0x3ff; + + lut_y = &acm->gain_lut_hy[0]; + lut_h = &acm->gain_lut_hy[ACM_GAIN_LUT_HY_LENGTH]; + lut_s = &acm->gain_lut_hy[ACM_GAIN_LUT_HY_LENGTH * 2]; + for (i = 0; i < ACM_GAIN_LUT_HY_LENGTH; i++) { + value = readl(vop2->acm_regs + RK3528_ACM_YHS_DEL_HY_SEG0 + (i << 2)); + lut_y[i] = value & 0xff; + lut_h[i] = (value >> 8) & 0xff; + lut_s[i] = (value >> 16) & 0xff; + } + + lut_y = &acm->gain_lut_hs[0]; + lut_h = &acm->gain_lut_hs[ACM_GAIN_LUT_HS_LENGTH]; + lut_s = &acm->gain_lut_hs[ACM_GAIN_LUT_HS_LENGTH * 2]; + for (i = 0; i < ACM_GAIN_LUT_HS_LENGTH; i++) { + value = readl(vop2->acm_regs + RK3528_ACM_YHS_DEL_HS_SEG0 + (i << 2)); + lut_y[i] = value & 0xff; + lut_h[i] = (value >> 8) & 0xff; + lut_s[i] = (value >> 16) & 0xff; + } + + lut_y = &acm->delta_lut_h[0]; + lut_h = &acm->delta_lut_h[ACM_DELTA_LUT_H_LENGTH]; + lut_s = &acm->delta_lut_h[ACM_DELTA_LUT_H_LENGTH * 2]; + for (i = 0; i < ACM_DELTA_LUT_H_LENGTH; i++) { + value = readl(vop2->acm_regs + RK3528_ACM_YHS_DEL_HGAIN_SEG0 + (i << 2)); + lut_y[i] = value & 0x3ff; + lut_h[i] = (value >> 12) & 0xff; + lut_s[i] = (value >> 20) & 0x3ff; + } + + return 0; +} + +static int vop2_crtc_loader_protect(struct drm_crtc *crtc, bool on, void *data) { struct vop2_video_port *vp = to_vop2_video_port(crtc); struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); @@ -5942,6 +6004,12 @@ static int vop2_crtc_loader_protect(struct drm_crtc *crtc, bool on) ext_pll->vp_mask |= BIT(vp->id); } drm_crtc_vblank_on(crtc); + if (is_vop3(vop2)) { + if (vp_data->feature & (VOP_FEATURE_POST_ACM)) + vop2_crtc_get_inital_acm_info(crtc); + if (data && (vp_data->feature & VOP_FEATURE_POST_CSC)) + memcpy(&vp->csc_info, data, sizeof(struct post_csc)); + } if (private->cubic_lut[vp->id].enable) { dma_addr_t cubic_lut_mst; struct loader_cubic_lut *cubic_lut = &private->cubic_lut[vp->id]; @@ -6350,9 +6418,9 @@ static size_t vop2_plane_line_bandwidth(struct drm_plane_state *pstate) bandwidth = bandwidth * src_width / dst_width; bandwidth = bandwidth * src_height / dst_height; - if (vskiplines == 2) + if (vskiplines == 2 && vpstate->afbc_en == 0) bandwidth /= 2; - else if (vskiplines == 4) + else if (vskiplines == 4 && vpstate->afbc_en == 0) bandwidth /= 4; return bandwidth; @@ -6446,9 +6514,12 @@ static size_t vop2_crtc_bandwidth(struct drm_crtc *crtc, act_w = drm_rect_width(&pstate->src) >> 16; act_h = drm_rect_height(&pstate->src) >> 16; + if (pstate->fb->format->is_yuv && (act_w >= 3840 || act_h >= 3840)) + vop_bw_info->plane_num_4k++; + bpp = rockchip_drm_get_bpp(pstate->fb->format); - vop_bw_info->frame_bw_mbyte += act_w * act_h / 1000 * bpp / 8 * fps / 1000; + vop_bw_info->frame_bw_mbyte += act_w * act_h / 1000 * bpp / 8 * fps / 1000 / afbc_fac; } sort(pbandwidth, cnt, sizeof(pbandwidth[0]), vop2_bandwidth_cmp, NULL); @@ -7257,6 +7328,11 @@ static void vop2_crtc_enable_dsc(struct drm_crtc *crtc, struct drm_crtc_state *o dsc->enabled = true; } +static inline bool vop2_mark_as_left_panel(struct rockchip_crtc_state *vcstate, u32 output_if) +{ + return vcstate->output_if_left_panel & output_if; +} + static void vop2_setup_dual_channel_if(struct drm_crtc *crtc) { struct vop2_video_port *vp = to_vop2_video_port(crtc); @@ -7267,13 +7343,17 @@ static void vop2_setup_dual_channel_if(struct drm_crtc *crtc) if (vcstate->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) VOP_MODULE_SET(vop2, vp, dual_channel_swap, 1); - if (vcstate->output_if & VOP_OUTPUT_IF_DP1) + if (vcstate->output_if & VOP_OUTPUT_IF_DP1 && + !vop2_mark_as_left_panel(vcstate, VOP_OUTPUT_IF_DP1)) VOP_CTRL_SET(vop2, dp_dual_en, 1); - else if (vcstate->output_if & VOP_OUTPUT_IF_eDP1) + else if (vcstate->output_if & VOP_OUTPUT_IF_eDP1 && + !vop2_mark_as_left_panel(vcstate, VOP_OUTPUT_IF_eDP1)) VOP_CTRL_SET(vop2, edp_dual_en, 1); - else if (vcstate->output_if & VOP_OUTPUT_IF_HDMI1) + else if (vcstate->output_if & VOP_OUTPUT_IF_HDMI1 && + !vop2_mark_as_left_panel(vcstate, VOP_OUTPUT_IF_HDMI1)) VOP_CTRL_SET(vop2, hdmi_dual_en, 1); - else if (vcstate->output_if & VOP_OUTPUT_IF_MIPI1) + else if (vcstate->output_if & VOP_OUTPUT_IF_MIPI1 && + !vop2_mark_as_left_panel(vcstate, VOP_OUTPUT_IF_MIPI1)) VOP_CTRL_SET(vop2, mipi_dual_en, 1); } @@ -7489,9 +7569,9 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_sta vop2_set_system_status(vop2); vop2_lock(vop2); - DRM_DEV_INFO(vop2->dev, "Update mode to %dx%d%s%d, type: %d(if:%x) for vp%d dclk: %d\n", + DRM_DEV_INFO(vop2->dev, "Update mode to %dx%d%s%d, type: %d(if:%x, flag:0x%x) for vp%d dclk: %d\n", hdisplay, adjusted_mode->vdisplay, interlaced ? "i" : "p", - vop2_get_vrefresh(vp, adjusted_mode), vcstate->output_type, vcstate->output_if, + vop2_get_vrefresh(vp, adjusted_mode), vcstate->output_type, vcstate->output_if, vcstate->output_flags, vp->id, adjusted_mode->crtc_clock * 1000); if (adjusted_mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) { @@ -7503,6 +7583,9 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_sta vop2->active_vp_mask |= BIT(splice_vp->id); } + if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CONNECTOR_SPLIT_MODE) + vcstate->output_flags |= ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; + if (vcstate->dsc_enable) { int k = 1; diff --git a/drivers/media/i2c/gc2093.c b/drivers/media/i2c/gc2093.c index 1aaa860cde82..44e7aa14b0f6 100644 --- a/drivers/media/i2c/gc2093.c +++ b/drivers/media/i2c/gc2093.c @@ -606,8 +606,7 @@ static int gc2093_set_ctrl(struct v4l2_ctrl *ctrl) (vts >> 8) & 0x3f); ret |= gc2093_write_reg(gc2093, GC2093_REG_VTS_L, vts & 0xff); - if (gc2093->cur_vts != gc2093->cur_mode->vts_def) - gc2093_modify_fps_info(gc2093); + gc2093_modify_fps_info(gc2093); dev_dbg(gc2093->dev, " set blank value 0x%x\n", ctrl->val); break; case V4L2_CID_HFLIP: diff --git a/drivers/media/i2c/max96712.c b/drivers/media/i2c/max96712.c index ae47b2db0113..cdeb8cc0ff97 100644 --- a/drivers/media/i2c/max96712.c +++ b/drivers/media/i2c/max96712.c @@ -17,6 +17,7 @@ * support for GMSL1 Link. * V1.5.00 only check max96712 chipid when probe. * enable stream out if not all link are locked. + * V1.6.00 serdes read /write api depend on i2c id index. * */ @@ -45,7 +46,7 @@ #include #include -#define DRIVER_VERSION KERNEL_VERSION(1, 0x05, 0x00) +#define DRIVER_VERSION KERNEL_VERSION(1, 0x06, 0x00) #ifndef V4L2_CID_DIGITAL_GAIN #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN @@ -63,48 +64,48 @@ #define MAX96717_CHIP_ID 0xBF #define MAX96717_REG_CHIP_ID 0x0D -#define MAX96712_REMOTE_CTRL 0x0003 -#define MAX96712_REMOTE_DISABLE 0xFF - /* max96712->link mask: link type = bit[7:4], link mask = bit[3:0] */ -#define MAX96712_GMSL_TYPE_LINK_A BIT(4) -#define MAX96712_GMSL_TYPE_LINK_B BIT(5) -#define MAX96712_GMSL_TYPE_LINK_C BIT(6) -#define MAX96712_GMSL_TYPE_LINK_D BIT(7) -#define MAX96712_GMSL_TYPE_MASK 0xF0 /* bit[7:4], GMSL link type: 0 = GMSL1, 1 = GMSL2 */ +#define MAXIM_GMSL_TYPE_LINK_A BIT(4) +#define MAXIM_GMSL_TYPE_LINK_B BIT(5) +#define MAXIM_GMSL_TYPE_LINK_C BIT(6) +#define MAXIM_GMSL_TYPE_LINK_D BIT(7) +#define MAXIM_GMSL_TYPE_MASK 0xF0 /* bit[7:4], GMSL link type: 0 = GMSL1, 1 = GMSL2 */ -#define MAX96712_LOCK_STATE_LINK_A BIT(0) -#define MAX96712_LOCK_STATE_LINK_B BIT(1) -#define MAX96712_LOCK_STATE_LINK_C BIT(2) -#define MAX96712_LOCK_STATE_LINK_D BIT(3) -#define MAX96712_LOCK_STATE_MASK 0x0F /* bit[3:0], GMSL link mask: 1 = disable, 1 = enable */ +#define MAXIM_GMSL_LOCK_LINK_A BIT(0) +#define MAXIM_GMSL_LOCK_LINK_B BIT(1) +#define MAXIM_GMSL_LOCK_LINK_C BIT(2) +#define MAXIM_GMSL_LOCK_LINK_D BIT(3) +#define MAXIM_GMSL_LOCK_MASK 0x0F /* bit[3:0], GMSL link mask: 1 = disable, 1 = enable */ -#define MAX96712_FORCE_ALL_CLOCK_EN 1 /* 1: enable, 0: disable */ - -#define REG_NULL 0xFFFF +#define MAXIM_FORCE_ALL_CLOCK_EN 1 /* 1: enable, 0: disable */ #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default" #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep" #define MAX96712_NAME "max96712" +#define REG_NULL 0xFFFF + /* register length: 8bit or 16bit */ -#define MAX96712_REG_LENGTH_08BIT 1 -#define MAX96712_REG_LENGTH_16BIT 2 +#define DEV_REG_LENGTH_08BITS 1 +#define DEV_REG_LENGTH_16BITS 2 /* register value: 8bit or 16bit or 24bit */ -#define MAX96712_REG_VALUE_08BIT 1 -#define MAX96712_REG_VALUE_16BIT 2 -#define MAX96712_REG_VALUE_24BIT 3 +#define DEV_REG_VALUE_08BITS 1 +#define DEV_REG_VALUE_16BITS 2 +#define DEV_REG_VALUE_24BITS 3 -#define MAX96712_I2C_ADDR (0x29) -#define MAX96715_I2C_ADDR (0x40) -#define MAX96717_I2C_ADDR (0x40) -#define CAMERA_I2C_ADDR (0x30) +/* i2c device default address */ +#define SER_I2C_ADDR (0x40) +#define CAM_I2C_ADDR (0x30) -#define MAX96712_GET_BIT(x, bit) ((x & (1 << bit)) >> bit) -#define MAX96712_GET_BIT_M_TO_N(x, m, n) \ - ((unsigned int)(x << (31 - (n))) >> ((31 - (n)) + (m))) +/* Maxim Serdes I2C Device ID */ +enum { + I2C_DEV_DES = 0, + I2C_DEV_SER, + I2C_DEV_CAM, + I2C_DEV_MAX +}; enum max96712_rx_rate { MAX96712_RX_RATE_3GBPS = 0, @@ -120,7 +121,7 @@ static const char *const max96712_supply_names[] = { #define MAX96712_NUM_SUPPLIES ARRAY_SIZE(max96712_supply_names) struct regval { - u16 i2c_addr; + u16 i2c_id; u16 reg_len; u16 reg; u8 val; @@ -144,6 +145,7 @@ struct max96712_mode { struct max96712 { struct i2c_client *client; + u16 i2c_addr[I2C_DEV_MAX]; struct clk *xvclk; struct gpio_desc *power_gpio; struct gpio_desc *reset_gpio; @@ -206,91 +208,93 @@ static struct rkmodule_csi_dphy_param rk3588_dcphy_param = { .reserved = {0}, }; +/* max96717 */ static const struct regval max96712_mipi_4lane_1920x1440_30fps[] = { // Link A/B/C/D all use GMSL2, and disabled - { 0x29, 2, 0x0006, 0xf0, 0x00, 0x00 }, // Link A/B/C/D: select GMSL2, Disabled + { I2C_DEV_DES, 2, 0x0006, 0xf0, 0x00, 0x00 }, // Link A/B/C/D: select GMSL2, Disabled // Disable MIPI CSI output - { 0x29, 2, 0x040B, 0x00, 0x00, 0x00 }, // CSI_OUT_EN=0, CSI output disabled + { I2C_DEV_DES, 2, 0x040B, 0x00, 0x00, 0x00 }, // CSI_OUT_EN=0, CSI output disabled // Increase CMU voltage - { 0x29, 2, 0x06C2, 0x10, 0x00, 0x0a }, // Increase CMU voltage to for wide temperature range + { I2C_DEV_DES, 2, 0x06C2, 0x10, 0x00, 0x0a }, // Increase CMU voltage to for wide temperature range // VGAHiGain - { 0x29, 2, 0x14D1, 0x03, 0x00, 0x00 }, // VGAHiGain - { 0x29, 2, 0x15D1, 0x03, 0x00, 0x00 }, // VGAHiGain - { 0x29, 2, 0x16D1, 0x03, 0x00, 0x00 }, // VGAHiGain - { 0x29, 2, 0x17D1, 0x03, 0x00, 0x0a }, // VGAHiGain + { I2C_DEV_DES, 2, 0x14D1, 0x03, 0x00, 0x00 }, // VGAHiGain + { I2C_DEV_DES, 2, 0x15D1, 0x03, 0x00, 0x00 }, // VGAHiGain + { I2C_DEV_DES, 2, 0x16D1, 0x03, 0x00, 0x00 }, // VGAHiGain + { I2C_DEV_DES, 2, 0x17D1, 0x03, 0x00, 0x0a }, // VGAHiGain // SSC Configuration - { 0x29, 2, 0x1445, 0x00, 0x00, 0x00 }, // Disable SSC - { 0x29, 2, 0x1545, 0x00, 0x00, 0x00 }, // Disable SSC - { 0x29, 2, 0x1645, 0x00, 0x00, 0x00 }, // Disable SSC - { 0x29, 2, 0x1745, 0x00, 0x00, 0x0a }, // Disable SSC + { I2C_DEV_DES, 2, 0x1445, 0x00, 0x00, 0x00 }, // Disable SSC + { I2C_DEV_DES, 2, 0x1545, 0x00, 0x00, 0x00 }, // Disable SSC + { I2C_DEV_DES, 2, 0x1645, 0x00, 0x00, 0x00 }, // Disable SSC + { I2C_DEV_DES, 2, 0x1745, 0x00, 0x00, 0x0a }, // Disable SSC // GMSL2 Link Video Pipe Selection - { 0x29, 2, 0x00F0, 0x62, 0x00, 0x00 }, // Phy A -> Pipe Z -> Pipe 0; Phy B -> Pipe Z -> Pipe 1 - { 0x29, 2, 0x00F1, 0xea, 0x00, 0x00 }, // Phy C -> Pipe Z -> Pipe 2; Phy D -> Pipe Z -> Pipe 3 - { 0x29, 2, 0x00F4, 0x0f, 0x00, 0x00 }, // Enable all 4 Pipes + { I2C_DEV_DES, 2, 0x00F0, 0x62, 0x00, 0x00 }, // Phy A -> Pipe Z -> Pipe 0; Phy B -> Pipe Z -> Pipe 1 + { I2C_DEV_DES, 2, 0x00F1, 0xea, 0x00, 0x00 }, // Phy C -> Pipe Z -> Pipe 2; Phy D -> Pipe Z -> Pipe 3 + { I2C_DEV_DES, 2, 0x00F4, 0x0f, 0x00, 0x00 }, // Enable all 4 Pipes // Send YUV422, FS, and FE from Video Pipe 0 to Controller 1 - { 0x29, 2, 0x090B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings - { 0x29, 2, 0x092D, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1; + { I2C_DEV_DES, 2, 0x090B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings + { I2C_DEV_DES, 2, 0x092D, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1; // For the following MSB 2 bits = VC, LSB 6 bits = DT - { 0x29, 2, 0x090D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit - { 0x29, 2, 0x090E, 0x1e, 0x00, 0x00 }, // DST0 VC = 0, DT = YUV422 8bit - { 0x29, 2, 0x090F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start - { 0x29, 2, 0x0910, 0x00, 0x00, 0x00 }, // DST1 VC = 0, DT = Frame Start - { 0x29, 2, 0x0911, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End - { 0x29, 2, 0x0912, 0x01, 0x00, 0x00 }, // DST2 VC = 0, DT = Frame End + { I2C_DEV_DES, 2, 0x090D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit + { I2C_DEV_DES, 2, 0x090E, 0x1e, 0x00, 0x00 }, // DST0 VC = 0, DT = YUV422 8bit + { I2C_DEV_DES, 2, 0x090F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start + { I2C_DEV_DES, 2, 0x0910, 0x00, 0x00, 0x00 }, // DST1 VC = 0, DT = Frame Start + { I2C_DEV_DES, 2, 0x0911, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End + { I2C_DEV_DES, 2, 0x0912, 0x01, 0x00, 0x00 }, // DST2 VC = 0, DT = Frame End // Send YUV422, FS, and FE from Video Pipe 1 to Controller 1 - { 0x29, 2, 0x094B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings - { 0x29, 2, 0x096D, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1; + { I2C_DEV_DES, 2, 0x094B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings + { I2C_DEV_DES, 2, 0x096D, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1; // For the following MSB 2 bits = VC, LSB 6 bits = DT - { 0x29, 2, 0x094D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit - { 0x29, 2, 0x094E, 0x5e, 0x00, 0x00 }, // DST0 VC = 1, DT = YUV422 8bit - { 0x29, 2, 0x094F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start - { 0x29, 2, 0x0950, 0x40, 0x00, 0x00 }, // DST1 VC = 1, DT = Frame Start - { 0x29, 2, 0x0951, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End - { 0x29, 2, 0x0952, 0x41, 0x00, 0x00 }, // DST2 VC = 1, DT = Frame End + { I2C_DEV_DES, 2, 0x094D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit + { I2C_DEV_DES, 2, 0x094E, 0x5e, 0x00, 0x00 }, // DST0 VC = 1, DT = YUV422 8bit + { I2C_DEV_DES, 2, 0x094F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start + { I2C_DEV_DES, 2, 0x0950, 0x40, 0x00, 0x00 }, // DST1 VC = 1, DT = Frame Start + { I2C_DEV_DES, 2, 0x0951, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End + { I2C_DEV_DES, 2, 0x0952, 0x41, 0x00, 0x00 }, // DST2 VC = 1, DT = Frame End // Send YUV422, FS, and FE from Video Pipe 2 to Controller 1 - { 0x29, 2, 0x098B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings - { 0x29, 2, 0x09AD, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1; + { I2C_DEV_DES, 2, 0x098B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings + { I2C_DEV_DES, 2, 0x09AD, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1; // For the following MSB 2 bits = VC, LSB 6 bits = DT - { 0x29, 2, 0x098D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit - { 0x29, 2, 0x098E, 0x9e, 0x00, 0x00 }, // DST0 VC = 2, DT = YUV422 8bit - { 0x29, 2, 0x098F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start - { 0x29, 2, 0x0990, 0x80, 0x00, 0x00 }, // DST1 VC = 2, DT = Frame Start - { 0x29, 2, 0x0991, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End - { 0x29, 2, 0x0992, 0x81, 0x00, 0x00 }, // DST2 VC = 2, DT = Frame End + { I2C_DEV_DES, 2, 0x098D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit + { I2C_DEV_DES, 2, 0x098E, 0x9e, 0x00, 0x00 }, // DST0 VC = 2, DT = YUV422 8bit + { I2C_DEV_DES, 2, 0x098F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start + { I2C_DEV_DES, 2, 0x0990, 0x80, 0x00, 0x00 }, // DST1 VC = 2, DT = Frame Start + { I2C_DEV_DES, 2, 0x0991, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End + { I2C_DEV_DES, 2, 0x0992, 0x81, 0x00, 0x00 }, // DST2 VC = 2, DT = Frame End // Send YUV422, FS, and FE from Video Pipe 3 to Controller 1 - { 0x29, 2, 0x09CB, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings - { 0x29, 2, 0x09ED, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1; + { I2C_DEV_DES, 2, 0x09CB, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings + { I2C_DEV_DES, 2, 0x09ED, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1; // For the following MSB 2 bits = VC, LSB 6 bits = DT - { 0x29, 2, 0x09CD, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit - { 0x29, 2, 0x09CE, 0xde, 0x00, 0x00 }, // DST0 VC = 3, DT = YUV422 8bit - { 0x29, 2, 0x09CF, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start - { 0x29, 2, 0x09D0, 0xc0, 0x00, 0x00 }, // DST1 VC = 3, DT = Frame Start - { 0x29, 2, 0x09D1, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End - { 0x29, 2, 0x09D2, 0xc1, 0x00, 0x00 }, // DST2 VC = 3, DT = Frame End + { I2C_DEV_DES, 2, 0x09CD, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit + { I2C_DEV_DES, 2, 0x09CE, 0xde, 0x00, 0x00 }, // DST0 VC = 3, DT = YUV422 8bit + { I2C_DEV_DES, 2, 0x09CF, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start + { I2C_DEV_DES, 2, 0x09D0, 0xc0, 0x00, 0x00 }, // DST1 VC = 3, DT = Frame Start + { I2C_DEV_DES, 2, 0x09D1, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End + { I2C_DEV_DES, 2, 0x09D2, 0xc1, 0x00, 0x00 }, // DST2 VC = 3, DT = Frame End // MIPI PHY Setting - { 0x29, 2, 0x08A0, 0x24, 0x00, 0x00 }, // DPHY0 enabled as clock, MIPI PHY Mode: 2x4 mode + { I2C_DEV_DES, 2, 0x08A0, 0x24, 0x00, 0x00 }, // DPHY0 enabled as clock, MIPI PHY Mode: 2x4 mode // Set Lane Mapping for 4-lane port A - { 0x29, 2, 0x08A3, 0xe4, 0x00, 0x00 }, // PHY1 D1->D3, D0->D2; PHY0 D1->D1, D0->D0 + { I2C_DEV_DES, 2, 0x08A3, 0xe4, 0x00, 0x00 }, // PHY1 D1->D3, D0->D2; PHY0 D1->D1, D0->D0 // Set 4 lane D-PHY, 2bit VC - { 0x29, 2, 0x090A, 0xc0, 0x00, 0x00 }, // MIPI PHY 0: 4 lanes, DPHY, 2bit VC - { 0x29, 2, 0x094A, 0xc0, 0x00, 0x00 }, // MIPI PHY 1: 4 lanes, DPHY, 2bit VC + { I2C_DEV_DES, 2, 0x090A, 0xc0, 0x00, 0x00 }, // MIPI PHY 0: 4 lanes, DPHY, 2bit VC + { I2C_DEV_DES, 2, 0x094A, 0xc0, 0x00, 0x00 }, // MIPI PHY 1: 4 lanes, DPHY, 2bit VC // Turn on MIPI PHYs - { 0x29, 2, 0x08A2, 0x34, 0x00, 0x00 }, // Enable MIPI PHY 0/1, t_lpx = 106.7ns + { I2C_DEV_DES, 2, 0x08A2, 0x34, 0x00, 0x00 }, // Enable MIPI PHY 0/1, t_lpx = 106.7ns // YUV422 8bit software override for all pipes since connected GMSL1 is under parallel mode - { 0x29, 2, 0x040B, 0x80, 0x00, 0x00 }, // pipe 0 bpp=0x10: Datatypes = 0x22, 0x1E, 0x2E - { 0x29, 2, 0x040E, 0x5e, 0x00, 0x00 }, // pipe 0 DT=0x1E: YUV422 8-bit - { 0x29, 2, 0x040F, 0x7e, 0x00, 0x00 }, // pipe 1 DT=0x1E: YUV422 8-bit - { 0x29, 2, 0x0410, 0x7a, 0x00, 0x00 }, // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit - { 0x29, 2, 0x0411, 0x90, 0x00, 0x00 }, // pipe 1 bpp=0x10: Datatypes = 0x22, 0x1E, 0x2E - { 0x29, 2, 0x0412, 0x40, 0x00, 0x00 }, // pipe 2 bpp=0x10, pipe 3 bpp=0x10: Datatypes = 0x22, 0x1E, 0x2E + { I2C_DEV_DES, 2, 0x040B, 0x80, 0x00, 0x00 }, // pipe 0 bpp=0x10: Datatypes = 0x22, 0x1E, 0x2E + { I2C_DEV_DES, 2, 0x040E, 0x5e, 0x00, 0x00 }, // pipe 0 DT=0x1E: YUV422 8-bit + { I2C_DEV_DES, 2, 0x040F, 0x7e, 0x00, 0x00 }, // pipe 1 DT=0x1E: YUV422 8-bit + { I2C_DEV_DES, 2, 0x0410, 0x7a, 0x00, 0x00 }, // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit + { I2C_DEV_DES, 2, 0x0411, 0x90, 0x00, 0x00 }, // pipe 1 bpp=0x10: Datatypes = 0x22, 0x1E, 0x2E + { I2C_DEV_DES, 2, 0x0412, 0x40, 0x00, 0x00 }, // pipe 2 bpp=0x10, pipe 3 bpp=0x10: Datatypes = 0x22, 0x1E, 0x2E // Enable all links and pipes - { 0x29, 2, 0x0003, 0xaa, 0x00, 0x00 }, // Enable Remote Control Channel Link A/B/C/D for Port 0 - { 0x29, 2, 0x0006, 0xff, 0x00, 0x64 }, // Enable all links and pipes + { I2C_DEV_DES, 2, 0x0003, 0xaa, 0x00, 0x00 }, // Enable Remote Control Channel Link A/B/C/D for Port 0 + { I2C_DEV_DES, 2, 0x0006, 0xff, 0x00, 0x64 }, // Enable all links and pipes // Serializer Setting - { 0x40, 2, 0x0302, 0x10, 0x00, 0x00 }, // improve CMU voltage performance to improve link robustness - { 0x40, 2, 0x1417, 0x00, 0x00, 0x00 }, // Errata - { 0x40, 2, 0x1432, 0x7f, 0x00, 0x00 }, - { 0x29, 2, REG_NULL, 0x00, 0x00, 0x00 }, + { I2C_DEV_SER, 2, 0x0302, 0x10, 0x00, 0x00 }, // improve CMU voltage performance to improve link robustness + { I2C_DEV_SER, 2, 0x1417, 0x00, 0x00, 0x00 }, // Errata + { I2C_DEV_SER, 2, 0x1432, 0x7f, 0x00, 0x00 }, + // End register setting + { I2C_DEV_DES, 2, REG_NULL, 0x00, 0x00, 0x00 }, }; static const struct max96712_mode supported_modes_4lane[] = { @@ -342,15 +346,17 @@ static const s64 link_freq_items[] = { MAX96712_LINK_FREQ_MHZ(1250), }; -static int max96712_write_reg(struct i2c_client *client, - u16 client_addr, u16 reg, u16 reg_len, u16 val_len, u32 val) +static int max96712_write_reg(struct max96712 *max96712, u8 i2c_id, + u16 reg, u16 reg_len, u16 val_len, u32 val) { + struct i2c_client *client = max96712->client; + u16 client_addr = max96712->i2c_addr[i2c_id]; u32 buf_i, val_i; u8 buf[6]; u8 *val_p; __be32 val_be; - dev_info(&client->dev, "addr(0x%02x) write reg(0x%04x, %d, 0x%02x)\n", \ + dev_info(&client->dev, "addr(0x%02x) write reg(0x%04x, %d, 0x%02x)\n", client_addr, reg, reg_len, val); if (val_len > 4) @@ -386,9 +392,11 @@ static int max96712_write_reg(struct i2c_client *client, return 0; } -static int max96712_read_reg(struct i2c_client *client, - u16 client_addr, u16 reg, u16 reg_len, u16 val_len, u8 *val) +static int max96712_read_reg(struct max96712 *max96712, u8 i2c_id, + u16 reg, u16 reg_len, u16 val_len, u8 *val) { + struct i2c_client *client = max96712->client; + u16 client_addr = max96712->i2c_addr[i2c_id]; struct i2c_msg msgs[2]; u8 *data_be_p; __be32 data_be = 0; @@ -426,34 +434,34 @@ static int max96712_read_reg(struct i2c_client *client, *val = be32_to_cpu(data_be); #if 0 - dev_info(&client->dev, "addr(0x%02x) read reg(0x%04x, %d, 0x%02x)\n", \ + dev_info(&client->dev, "addr(0x%02x) read reg(0x%04x, %d, 0x%02x)\n", client_addr, reg, reg_len, *val); #endif return 0; } -static int max96712_update_reg_bits(struct i2c_client *client, - u16 client_addr, u16 reg, u16 reg_len, u8 mask, u8 val) +static int max96712_update_reg_bits(struct max96712 *max96712, u8 i2c_id, + u16 reg, u16 reg_len, u8 mask, u8 val) { u8 value; - u32 val_len = MAX96712_REG_VALUE_08BIT; + u32 val_len = DEV_REG_VALUE_08BITS; int ret; - ret = max96712_read_reg(client, client_addr, reg, reg_len, val_len, &value); + ret = max96712_read_reg(max96712, i2c_id, reg, reg_len, val_len, &value); if (ret) return ret; value &= ~mask; value |= (val & mask); - ret = max96712_write_reg(client, client_addr, reg, reg_len, val_len, value); + ret = max96712_write_reg(max96712, i2c_id, reg, reg_len, val_len, value); if (ret) return ret; return 0; } -static int max96712_write_array(struct i2c_client *client, +static int max96712_write_array(struct max96712 *max96712, const struct regval *regs) { u32 i; @@ -461,13 +469,13 @@ static int max96712_write_array(struct i2c_client *client, for (i = 0; ret == 0 && regs[i].reg != REG_NULL; i++) { if (regs[i].mask != 0) - ret = max96712_update_reg_bits(client, regs[i].i2c_addr, + ret = max96712_update_reg_bits(max96712, regs[i].i2c_id, regs[i].reg, regs[i].reg_len, regs[i].mask, regs[i].val); else - ret = max96712_write_reg(client, regs[i].i2c_addr, + ret = max96712_write_reg(max96712, regs[i].i2c_id, regs[i].reg, regs[i].reg_len, - MAX96712_REG_VALUE_08BIT, regs[i].val); + DEV_REG_VALUE_08BITS, regs[i].val); if (regs[i].delay != 0) msleep(regs[i].delay); @@ -478,14 +486,13 @@ static int max96712_write_array(struct i2c_client *client, static int max96712_check_local_chipid(struct max96712 *max96712) { - struct i2c_client *client = max96712->client; struct device *dev = &max96712->client->dev; int ret; u8 id = 0; - ret = max96712_read_reg(client, MAX96712_I2C_ADDR, - MAX96712_REG_CHIP_ID, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, &id); + ret = max96712_read_reg(max96712, I2C_DEV_DES, + MAX96712_REG_CHIP_ID, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &id); if ((ret != 0) || (id != MAX96712_CHIP_ID)) { dev_err(dev, "Unexpected MAX96712 chip id(%02x), ret(%d)\n", id, ret); return -ENODEV; @@ -507,9 +514,9 @@ static int __maybe_unused max96712_check_remote_chipid(struct max96712 *max96712 id = 0; #if 0 // max96717 - ret = max96712_read_reg(max96712->client, MAX96717_I2C_ADDR, - MAX96717_REG_CHIP_ID, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, &id); + ret = max96712_read_reg(max96712, I2C_DEV_SER, + MAX96717_REG_CHIP_ID, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &id); if ((ret != 0) || (id != MAX96717_CHIP_ID)) { dev_err(dev, "Unexpected MAX96717 chip id(%02x), ret(%d)\n", id, ret); return -ENODEV; @@ -519,9 +526,9 @@ static int __maybe_unused max96712_check_remote_chipid(struct max96712 *max96712 #if 0 // max96715 - ret = max96712_read_reg(max96712->client, MAX96715_I2C_ADDR, - MAX96715_REG_CHIP_ID, MAX96712_REG_LENGTH_08BIT, - MAX96712_REG_VALUE_08BIT, &id); + ret = max96712_read_reg(max96712, I2C_DEV_SER, + MAX96715_REG_CHIP_ID, DEV_REG_LENGTH_08BITS, + DEV_REG_VALUE_08BITS, &id); if ((ret != 0) || (id != MAX96715_CHIP_ID)) { dev_err(dev, "Unexpected MAX96715 chip id(%02x), ret(%d)\n", id, ret); return -ENODEV; @@ -534,96 +541,95 @@ static int __maybe_unused max96712_check_remote_chipid(struct max96712 *max96712 static u8 max96712_get_link_lock_state(struct max96712 *max96712, u8 link_mask) { - struct i2c_client *client = max96712->client; struct device *dev = &max96712->client->dev; u8 lock = 0, lock_state = 0; u8 link_type = 0; - link_type = max96712->link_mask & MAX96712_GMSL_TYPE_MASK; + link_type = max96712->link_mask & MAXIM_GMSL_TYPE_MASK; - if (link_mask & MAX96712_LOCK_STATE_LINK_A) { - if (link_type & MAX96712_GMSL_TYPE_LINK_A) { + if (link_mask & MAXIM_GMSL_LOCK_LINK_A) { + if (link_type & MAXIM_GMSL_TYPE_LINK_A) { // GMSL2 LinkA - max96712_read_reg(client, MAX96712_I2C_ADDR, - 0x001a, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, &lock); + max96712_read_reg(max96712, I2C_DEV_DES, + 0x001a, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &lock); if (lock & BIT(3)) { - lock_state |= MAX96712_LOCK_STATE_LINK_A; + lock_state |= MAXIM_GMSL_LOCK_LINK_A; dev_info(dev, "GMSL2 LinkA locked\n"); } } else { // GMSL1 LinkA - max96712_read_reg(client, MAX96712_I2C_ADDR, - 0x0bcb, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, &lock); + max96712_read_reg(max96712, I2C_DEV_DES, + 0x0bcb, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &lock); if (lock & BIT(0)) { - lock_state |= MAX96712_LOCK_STATE_LINK_A; + lock_state |= MAXIM_GMSL_LOCK_LINK_A; dev_info(dev, "GMSL1 LinkA locked\n"); } } } - if (link_mask & MAX96712_LOCK_STATE_LINK_B) { - if (link_type & MAX96712_GMSL_TYPE_LINK_B) { + if (link_mask & MAXIM_GMSL_LOCK_LINK_B) { + if (link_type & MAXIM_GMSL_TYPE_LINK_B) { // GMSL2 LinkB - max96712_read_reg(client, MAX96712_I2C_ADDR, - 0x000a, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, &lock); + max96712_read_reg(max96712, I2C_DEV_DES, + 0x000a, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &lock); if (lock & BIT(3)) { - lock_state |= MAX96712_LOCK_STATE_LINK_B; + lock_state |= MAXIM_GMSL_LOCK_LINK_B; dev_info(dev, "GMSL2 LinkB locked\n"); } } else { // GMSL1 LinkB - max96712_read_reg(client, MAX96712_I2C_ADDR, - 0x0ccb, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, &lock); + max96712_read_reg(max96712, I2C_DEV_DES, + 0x0ccb, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &lock); if (lock & BIT(0)) { - lock_state |= MAX96712_LOCK_STATE_LINK_B; + lock_state |= MAXIM_GMSL_LOCK_LINK_B; dev_info(dev, "GMSL1 LinkB locked\n"); } } } - if (link_mask & MAX96712_LOCK_STATE_LINK_C) { - if (link_type & MAX96712_GMSL_TYPE_LINK_C) { + if (link_mask & MAXIM_GMSL_LOCK_LINK_C) { + if (link_type & MAXIM_GMSL_TYPE_LINK_C) { // GMSL2 LinkC - max96712_read_reg(client, MAX96712_I2C_ADDR, - 0x000b, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, &lock); + max96712_read_reg(max96712, I2C_DEV_DES, + 0x000b, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &lock); if (lock & BIT(3)) { - lock_state |= MAX96712_LOCK_STATE_LINK_C; + lock_state |= MAXIM_GMSL_LOCK_LINK_C; dev_info(dev, "GMSL2 LinkC locked\n"); } } else { // GMSL1 LinkC - max96712_read_reg(client, MAX96712_I2C_ADDR, - 0x0dcb, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, &lock); + max96712_read_reg(max96712, I2C_DEV_DES, + 0x0dcb, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &lock); if (lock & BIT(0)) { - lock_state |= MAX96712_LOCK_STATE_LINK_C; + lock_state |= MAXIM_GMSL_LOCK_LINK_C; dev_info(dev, "GMSL1 LinkC locked\n"); } } } - if (link_mask & MAX96712_LOCK_STATE_LINK_D) { - if (link_type & MAX96712_GMSL_TYPE_LINK_D) { + if (link_mask & MAXIM_GMSL_LOCK_LINK_D) { + if (link_type & MAXIM_GMSL_TYPE_LINK_D) { // GMSL2 LinkD - max96712_read_reg(client, MAX96712_I2C_ADDR, - 0x000c, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, &lock); + max96712_read_reg(max96712, I2C_DEV_DES, + 0x000c, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &lock); if (lock & BIT(3)) { - lock_state |= MAX96712_LOCK_STATE_LINK_D; + lock_state |= MAXIM_GMSL_LOCK_LINK_D; dev_info(dev, "GMSL2 LinkD locked\n"); } } else { // GMSL1 LinkD - max96712_read_reg(client, MAX96712_I2C_ADDR, - 0x0ecb, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, &lock); + max96712_read_reg(max96712, I2C_DEV_DES, + 0x0ecb, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &lock); if (lock & BIT(0)) { - lock_state |= MAX96712_LOCK_STATE_LINK_D; + lock_state |= MAXIM_GMSL_LOCK_LINK_D; dev_info(dev, "GMSL1 LinkD locked\n"); } } @@ -634,7 +640,6 @@ static u8 max96712_get_link_lock_state(struct max96712 *max96712, u8 link_mask) static int max96712_check_link_lock_state(struct max96712 *max96712) { - struct i2c_client *client = max96712->client; struct device *dev = &max96712->client->dev; u8 lock_state = 0, link_mask = 0, link_type = 0; int ret, i, time_ms; @@ -647,99 +652,99 @@ static int max96712_check_link_lock_state(struct max96712 *max96712) * CTRL0: Enable REG_ENABLE * CTRL2: Enable REG_MNL */ - max96712_update_reg_bits(client, MAX96712_I2C_ADDR, - 0x0017, MAX96712_REG_LENGTH_16BIT, BIT(2), BIT(2)); - max96712_update_reg_bits(client, MAX96712_I2C_ADDR, - 0x0019, MAX96712_REG_LENGTH_16BIT, BIT(4), BIT(4)); + max96712_update_reg_bits(max96712, I2C_DEV_DES, + 0x0017, DEV_REG_LENGTH_16BITS, BIT(2), BIT(2)); + max96712_update_reg_bits(max96712, I2C_DEV_DES, + 0x0019, DEV_REG_LENGTH_16BITS, BIT(4), BIT(4)); // CSI output disabled - max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x040B, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0x00); + max96712_write_reg(max96712, I2C_DEV_DES, + 0x040B, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x00); // All links select mode by link_type and disable at beginning. - link_type = max96712->link_mask & MAX96712_GMSL_TYPE_MASK; - max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x0006, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, link_type); + link_type = max96712->link_mask & MAXIM_GMSL_TYPE_MASK; + max96712_write_reg(max96712, I2C_DEV_DES, + 0x0006, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, link_type); // Link Rate if (max96712->rx_rate == MAX96712_RX_RATE_3GBPS) { // Link A ~ Link D Transmitter Rate: 187.5Mbps, Receiver Rate: 3Gbps - max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x0010, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0x11); - max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x0011, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0x11); + max96712_write_reg(max96712, I2C_DEV_DES, + 0x0010, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x11); + max96712_write_reg(max96712, I2C_DEV_DES, + 0x0011, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x11); } else { // Link A ~ Link D Transmitter Rate: 187.5Mbps, Receiver Rate: 6Gbps - max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x0010, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0x22); - max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x0011, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0x22); + max96712_write_reg(max96712, I2C_DEV_DES, + 0x0010, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x22); + max96712_write_reg(max96712, I2C_DEV_DES, + 0x0011, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x22); } // GMSL1: Enable HIM on deserializer on Link A/B/C/D - if ((link_type & MAX96712_GMSL_TYPE_LINK_A) == 0) { - max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x0B06, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0xEF); + if ((link_type & MAXIM_GMSL_TYPE_LINK_A) == 0) { + max96712_write_reg(max96712, I2C_DEV_DES, + 0x0B06, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xEF); } - if ((link_type & MAX96712_GMSL_TYPE_LINK_B) == 0) { - max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x0C06, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0xEF); + if ((link_type & MAXIM_GMSL_TYPE_LINK_B) == 0) { + max96712_write_reg(max96712, I2C_DEV_DES, + 0x0C06, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xEF); } - if ((link_type & MAX96712_GMSL_TYPE_LINK_C) == 0) { - max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x0D06, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0xEF); + if ((link_type & MAXIM_GMSL_TYPE_LINK_C) == 0) { + max96712_write_reg(max96712, I2C_DEV_DES, + 0x0D06, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xEF); } - if ((link_type & MAX96712_GMSL_TYPE_LINK_D) == 0) { - max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x0E06, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0xEF); + if ((link_type & MAXIM_GMSL_TYPE_LINK_D) == 0) { + max96712_write_reg(max96712, I2C_DEV_DES, + 0x0E06, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xEF); } // Link A ~ Link D One-Shot Reset depend on link_mask - link_mask = max96712->link_mask & MAX96712_LOCK_STATE_MASK; - max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x0018, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, link_mask); + link_mask = max96712->link_mask & MAXIM_GMSL_LOCK_MASK; + max96712_write_reg(max96712, I2C_DEV_DES, + 0x0018, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, link_mask); // Link A ~ Link D enable depend on link_type and link_mask - max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x0006, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, link_type | link_mask); + max96712_write_reg(max96712, I2C_DEV_DES, + 0x0006, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, link_type | link_mask); time_ms = 50; msleep(time_ms); for (i = 0; i < 20; i++) { - if ((lock_state & MAX96712_LOCK_STATE_LINK_A) == 0) - if (max96712_get_link_lock_state(max96712, MAX96712_LOCK_STATE_LINK_A)) { - lock_state |= MAX96712_LOCK_STATE_LINK_A; + if ((lock_state & MAXIM_GMSL_LOCK_LINK_A) == 0) + if (max96712_get_link_lock_state(max96712, MAXIM_GMSL_LOCK_LINK_A)) { + lock_state |= MAXIM_GMSL_LOCK_LINK_A; dev_info(dev, "LinkA locked time: %d ms\n", time_ms); } - if ((lock_state & MAX96712_LOCK_STATE_LINK_B) == 0) - if (max96712_get_link_lock_state(max96712, MAX96712_LOCK_STATE_LINK_B)) { - lock_state |= MAX96712_LOCK_STATE_LINK_B; + if ((lock_state & MAXIM_GMSL_LOCK_LINK_B) == 0) + if (max96712_get_link_lock_state(max96712, MAXIM_GMSL_LOCK_LINK_B)) { + lock_state |= MAXIM_GMSL_LOCK_LINK_B; dev_info(dev, "LinkB locked time: %d ms\n", time_ms); } - if ((lock_state & MAX96712_LOCK_STATE_LINK_C) == 0) - if (max96712_get_link_lock_state(max96712, MAX96712_LOCK_STATE_LINK_C)) { - lock_state |= MAX96712_LOCK_STATE_LINK_C; + if ((lock_state & MAXIM_GMSL_LOCK_LINK_C) == 0) + if (max96712_get_link_lock_state(max96712, MAXIM_GMSL_LOCK_LINK_C)) { + lock_state |= MAXIM_GMSL_LOCK_LINK_C; dev_info(dev, "LinkC locked time: %d ms\n", time_ms); } - if ((lock_state & MAX96712_LOCK_STATE_LINK_D) == 0) - if (max96712_get_link_lock_state(max96712, MAX96712_LOCK_STATE_LINK_D)) { - lock_state |= MAX96712_LOCK_STATE_LINK_D; + if ((lock_state & MAXIM_GMSL_LOCK_LINK_D) == 0) + if (max96712_get_link_lock_state(max96712, MAXIM_GMSL_LOCK_LINK_D)) { + lock_state |= MAXIM_GMSL_LOCK_LINK_D; dev_info(dev, "LinkD locked time: %d ms\n", time_ms); } @@ -770,7 +775,7 @@ static irqreturn_t max96712_hot_plug_detect_irq_handler(int irq, void *dev_id) struct device *dev = &max96712->client->dev; u8 lock_state = 0, link_mask = 0; - link_mask = max96712->link_mask & MAX96712_LOCK_STATE_MASK; + link_mask = max96712->link_mask & MAXIM_GMSL_LOCK_MASK; if (max96712->streaming) { lock_state = max96712_get_link_lock_state(max96712, link_mask); if (lock_state == link_mask) { @@ -783,21 +788,21 @@ static irqreturn_t max96712_hot_plug_detect_irq_handler(int irq, void *dev_id) return IRQ_HANDLED; } -static int __maybe_unused max96712_dphy_dpll_predef_set(struct i2c_client *client, - u32 link_freq_mhz) +static int max96712_dphy_dpll_predef_set(struct max96712 *max96712, u32 link_freq_mhz) { + struct device *dev = &max96712->client->dev; int ret = 0; u8 dpll_val = 0, dpll_lock = 0; u8 mipi_tx_phy_enable = 0; - ret = max96712_read_reg(client, MAX96712_I2C_ADDR, - 0x08A2, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, &mipi_tx_phy_enable); + ret = max96712_read_reg(max96712, I2C_DEV_DES, + 0x08A2, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &mipi_tx_phy_enable); if (ret) return ret; mipi_tx_phy_enable = (mipi_tx_phy_enable & 0xF0) >> 4; - dev_info(&client->dev, "DPLL predef set: mipi_tx_phy_enable = 0x%02x, link_freq_mhz = %d\n", + dev_info(dev, "DPLL predef set: mipi_tx_phy_enable = 0x%02x, link_freq_mhz = %d\n", mipi_tx_phy_enable, link_freq_mhz); // dphy max data rate is 2500MHz @@ -811,116 +816,117 @@ static int __maybe_unused max96712_dphy_dpll_predef_set(struct i2c_client *clien // MIPI PHY0 if (mipi_tx_phy_enable & BIT(0)) { // Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x1C00, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, - 0xf4); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x1C00, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xf4); // Set data rate and enable software override - ret |= max96712_update_reg_bits(client, MAX96712_I2C_ADDR, - 0x0415, MAX96712_REG_LENGTH_16BIT, 0x3F, dpll_val); + ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES, + 0x0415, DEV_REG_LENGTH_16BITS, 0x3F, dpll_val); // Release reset to DPLL (config_soft_rst_n = 1) - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x1C00, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0xf5); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x1C00, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xf5); } // MIPI PHY1 if (mipi_tx_phy_enable & BIT(1)) { // Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x1D00, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0xf4); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x1D00, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xf4); // Set data rate and enable software override - ret |= max96712_update_reg_bits(client, MAX96712_I2C_ADDR, - 0x0418, MAX96712_REG_LENGTH_16BIT, 0x3F, dpll_val); + ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES, + 0x0418, DEV_REG_LENGTH_16BITS, 0x3F, dpll_val); // Release reset to DPLL (config_soft_rst_n = 1) - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x1D00, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0xf5); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x1D00, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xf5); } // MIPI PHY2 if (mipi_tx_phy_enable & BIT(2)) { // Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x1E00, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0xf4); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x1E00, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xf4); // Set data rate and enable software override - ret |= max96712_update_reg_bits(client, MAX96712_I2C_ADDR, - 0x041B, MAX96712_REG_LENGTH_16BIT, 0x3F, dpll_val); + ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES, + 0x041B, DEV_REG_LENGTH_16BITS, 0x3F, dpll_val); // Release reset to DPLL (config_soft_rst_n = 1) - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x1E00, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0xf5); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x1E00, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xf5); } // MIPI PHY3 if (mipi_tx_phy_enable & BIT(3)) { // Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x1F00, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0xf4); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x1F00, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xf4); // Set data rate and enable software override - ret |= max96712_update_reg_bits(client, MAX96712_I2C_ADDR, - 0x041E, MAX96712_REG_LENGTH_16BIT, 0x3F, dpll_val); + ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES, + 0x041E, DEV_REG_LENGTH_16BITS, 0x3F, dpll_val); // Release reset to DPLL (config_soft_rst_n = 1) - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x1F00, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0xf5); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x1F00, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xf5); } if (ret) { - dev_err(&client->dev, "DPLL predef set error!\n"); + dev_err(dev, "DPLL predef set error!\n"); return ret; } ret = read_poll_timeout(max96712_read_reg, ret, !(ret < 0) && (dpll_lock & 0xF0), 1000, 10000, false, - client, MAX96712_I2C_ADDR, - 0x0400, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, &dpll_lock); + max96712, I2C_DEV_DES, + 0x0400, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &dpll_lock); if (ret < 0) { - dev_err(&client->dev, "DPLL is not locked, dpll_lock = 0x%02x\n", dpll_lock); + dev_err(dev, "DPLL is not locked, dpll_lock = 0x%02x\n", dpll_lock); return ret; } else { - dev_err(&client->dev, "DPLL is locked, dpll_lock = 0x%02x\n", dpll_lock); + dev_err(dev, "DPLL is locked, dpll_lock = 0x%02x\n", dpll_lock); return 0; } } -static int max96712_auto_init_deskew(struct i2c_client *client, u32 deskew_mask) +static int max96712_auto_init_deskew(struct max96712 *max96712, u32 deskew_mask) { + struct device *dev = &max96712->client->dev; int ret = 0; - dev_info(&client->dev, "Auto initial deskew: deskew_mask = 0x%02x\n", deskew_mask); + dev_info(dev, "Auto initial deskew: deskew_mask = 0x%02x\n", deskew_mask); // D-PHY Deskew Initial Calibration Control if (deskew_mask & BIT(0)) // MIPI PHY0 - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x0903, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0x80); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x0903, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x80); if (deskew_mask & BIT(1)) // MIPI PHY1 - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x0943, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0x80); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x0943, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x80); if (deskew_mask & BIT(2)) // MIPI PHY2 - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x0983, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0x80); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x0983, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x80); if (deskew_mask & BIT(3)) // MIPI PHY3 - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x09C3, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0x80); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x09C3, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x80); return ret; } -static int max96712_frame_sync_period(struct i2c_client *client, u32 period) +static int max96712_frame_sync_period(struct max96712 *max96712, u32 period) { + struct device *dev = &max96712->client->dev; u32 pclk, fsync_peroid; u8 fsync_peroid_h, fsync_peroid_m, fsync_peroid_l; int ret = 0; @@ -928,30 +934,30 @@ static int max96712_frame_sync_period(struct i2c_client *client, u32 period) if (period == 0) return 0; - dev_info(&client->dev, "Frame sync period = %d\n", period); + dev_info(dev, "Frame sync period = %d\n", period); -#if 1 // TODO: Sensor +#if 1 // TODO: Sensor slave mode // SC320AT slave mode enable - ret |= max96712_write_reg(client, 0x30, - 0x3222, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0x01); + ret |= max96712_write_reg(max96712, I2C_DEV_CAM, + 0x3222, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x01); // Increase the allowable error range of the trigger signal - ret |= max96712_write_reg(client, 0x30, - 0x32e2, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0x19); + ret |= max96712_write_reg(max96712, I2C_DEV_CAM, + 0x32e2, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x19); #endif // Master link Video 0 for frame sync generation - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x04A2, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0x00); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x04A2, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x00); // Disable Vsync-Fsync overlap window - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x04AA, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0x00); - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x04AB, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0x00); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x04AA, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x00); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x04AB, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x00); // Set FSYNC period to 25M/30 clock cycles. PCLK = 25MHz. Sync freq = 30Hz pclk = 25 * 1000 * 1000; @@ -959,72 +965,70 @@ static int max96712_frame_sync_period(struct i2c_client *client, u32 period) fsync_peroid_l = (fsync_peroid >> 0) & 0xFF; fsync_peroid_m = (fsync_peroid >> 8) & 0xFF; fsync_peroid_h = (fsync_peroid >> 16) & 0xFF; - dev_info(&client->dev, "Frame sync period: H = 0x%02x, M = 0x%02x, L = 0x%02x\n", + dev_info(dev, "Frame sync period: H = 0x%02x, M = 0x%02x, L = 0x%02x\n", fsync_peroid_h, fsync_peroid_m, fsync_peroid_l); // FSYNC_PERIOD_H - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x04A7, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, fsync_peroid_h); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x04A7, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, fsync_peroid_h); // FSYNC_PERIOD_M - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x04A6, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, fsync_peroid_m); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x04A6, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, fsync_peroid_m); // FSYNC_PERIOD_L - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x04A5, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, fsync_peroid_l); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x04A5, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, fsync_peroid_l); // FSYNC is GMSL2 type, use osc for fsync, include all links/pipes in fsync gen - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x04AF, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0xcf); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x04AF, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xcf); +#if 1 // TODO: Desrializer MFP // FSYNC_TX_ID: set 4 to match MFP4 on serializer side - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x04B1, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0x20); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x04B1, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x20); +#endif -#if 1 // TODO: Serializer +#if 1 // TODO: Serializer MFP // Enable GPIO_RX_EN on serializer MFP4 - ret |= max96712_write_reg(client, 0x40, - 0x02CA, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0x84); + ret |= max96712_write_reg(max96712, I2C_DEV_SER, + 0x02CA, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x84); #endif // MFP2, VS not gen internally, GPIO not used to gen fsync, manual mode - ret |= max96712_write_reg(client, MAX96712_I2C_ADDR, - 0x04A0, MAX96712_REG_LENGTH_16BIT, - MAX96712_REG_VALUE_08BIT, 0x04); + ret |= max96712_write_reg(max96712, I2C_DEV_DES, + 0x04A0, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x04); return ret; } -static int max96712_mipi_enable(struct i2c_client *client, bool enable) +static int max96712_mipi_enable(struct max96712 *max96712, bool enable) { int ret = 0; if (enable) { -#if MAX96712_FORCE_ALL_CLOCK_EN +#if MAXIM_FORCE_ALL_CLOCK_EN // Force all MIPI clocks running - ret |= max96712_update_reg_bits(client, - MAX96712_I2C_ADDR, - 0x08A0, MAX96712_REG_LENGTH_16BIT, BIT(7), BIT(7)); + ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES, + 0x08A0, DEV_REG_LENGTH_16BITS, BIT(7), BIT(7)); #endif // CSI output enabled - ret |= max96712_update_reg_bits(client, - MAX96712_I2C_ADDR, - 0x040B, MAX96712_REG_LENGTH_16BIT, BIT(1), BIT(1)); + ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES, + 0x040B, DEV_REG_LENGTH_16BITS, BIT(1), BIT(1)); } else { -#if MAX96712_FORCE_ALL_CLOCK_EN +#if MAXIM_FORCE_ALL_CLOCK_EN // Normal mode - ret |= max96712_update_reg_bits(client, - MAX96712_I2C_ADDR, - 0x08A0, MAX96712_REG_LENGTH_16BIT, BIT(7), 0x00); + ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES, + 0x08A0, DEV_REG_LENGTH_16BITS, BIT(7), 0x00); #endif // CSI output disabled - ret |= max96712_update_reg_bits(client, - MAX96712_I2C_ADDR, - 0x040B, MAX96712_REG_LENGTH_16BIT, BIT(1), 0x00); + ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES, + 0x040B, DEV_REG_LENGTH_16BITS, BIT(1), 0x00); } return ret; @@ -1229,9 +1233,9 @@ static long max96712_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) stream = *((u32 *)arg); if (stream) - ret = max96712_mipi_enable(max96712->client, true); + ret = max96712_mipi_enable(max96712, true); else - ret = max96712_mipi_enable(max96712->client, false); + ret = max96712_mipi_enable(max96712, false); break; case RKMODULE_GET_VICAP_RST_INFO: max96712_get_vicap_rst_inf( @@ -1408,26 +1412,26 @@ static int __max96712_start_stream(struct max96712 *max96712) if (max96712->hot_plug_irq > 0) enable_irq(max96712->hot_plug_irq); - ret = max96712_write_array(max96712->client, + ret = max96712_write_array(max96712, max96712->cur_mode->reg_list); if (ret) return ret; link_freq_idx = max96712->cur_mode->link_freq_idx; link_freq_mhz = (u32)div_s64(link_freq_items[link_freq_idx], 1000000L); - ret = max96712_dphy_dpll_predef_set(max96712->client, link_freq_mhz); + ret = max96712_dphy_dpll_predef_set(max96712, link_freq_mhz); if (ret) return ret; if (max96712->auto_init_deskew_mask != 0) { - ret = max96712_auto_init_deskew(max96712->client, + ret = max96712_auto_init_deskew(max96712, max96712->auto_init_deskew_mask); if (ret) return ret; } if (max96712->frame_sync_period != 0) { - ret = max96712_frame_sync_period(max96712->client, + ret = max96712_frame_sync_period(max96712, max96712->frame_sync_period); if (ret) return ret; @@ -1440,7 +1444,7 @@ static int __max96712_start_stream(struct max96712 *max96712) if (ret) return ret; - return max96712_mipi_enable(max96712->client, true); + return max96712_mipi_enable(max96712, true); } @@ -1449,7 +1453,7 @@ static int __max96712_stop_stream(struct max96712 *max96712) if (max96712->hot_plug_irq > 0) disable_irq(max96712->hot_plug_irq); - return max96712_mipi_enable(max96712->client, false); + return max96712_mipi_enable(max96712, false); } static int max96712_s_stream(struct v4l2_subdev *sd, int on) @@ -1823,8 +1827,19 @@ static int max96712_parse_dt(struct max96712 *max96712) struct device *dev = &max96712->client->dev; struct device_node *node = dev->of_node; u8 mipi_data_lanes = max96712->bus_cfg.bus.mipi_csi2.num_data_lanes; + u32 value = 0; int ret = 0; + /* serializer i2c address */ + ret = of_property_read_u32(node, "ser-i2c-addr", &value); + if (ret) { + max96712->i2c_addr[I2C_DEV_SER] = SER_I2C_ADDR; + } else { + dev_info(dev, "ser-i2c-addr property: %d\n", value); + max96712->i2c_addr[I2C_DEV_SER] = value; + } + dev_info(dev, "serializer i2c address: 0x%02x\n", max96712->i2c_addr[I2C_DEV_SER]); + /* max96712 link Receiver Rate: 3G or 6G */ ret = of_property_read_u32(node, "link-rx-rate", &max96712->rx_rate); @@ -1855,14 +1870,14 @@ static int max96712_parse_dt(struct max96712 *max96712) /* auto initial deskew mask */ ret = of_property_read_u32(node, "auto-init-deskew-mask", - &max96712->auto_init_deskew_mask); + &max96712->auto_init_deskew_mask); if (ret) max96712->auto_init_deskew_mask = 0x0F; // 0x0F: default enable all dev_info(dev, "auto init deskew mask: 0x%02x\n", max96712->auto_init_deskew_mask); /* FSYNC period config */ ret = of_property_read_u32(node, "frame-sync-period", - &max96712->frame_sync_period); + &max96712->frame_sync_period); if (ret) max96712->frame_sync_period = 0; // 0: disable (default) dev_info(dev, "frame sync period: %d\n", max96712->frame_sync_period); @@ -1911,6 +1926,11 @@ static int max96712_probe(struct i2c_client *client, max96712->client = client; i2c_set_clientdata(client, max96712); + /* i2c default address init */ + max96712->i2c_addr[I2C_DEV_DES] = client->addr; + max96712->i2c_addr[I2C_DEV_SER] = SER_I2C_ADDR; + max96712->i2c_addr[I2C_DEV_CAM] = CAM_I2C_ADDR; + endpoint = of_graph_get_next_endpoint(dev->of_node, NULL); if (!endpoint) { dev_err(dev, "Failed to get endpoint\n"); @@ -2023,19 +2043,23 @@ static int max96712_probe(struct i2c_client *client, if (!IS_ERR(max96712->lock_gpio)) { max96712->hot_plug_irq = gpiod_to_irq(max96712->lock_gpio); - if (max96712->hot_plug_irq < 0) + if (max96712->hot_plug_irq < 0) { dev_err(dev, "failed to get hot plug irq\n"); - - ret = devm_request_threaded_irq(dev, - max96712->hot_plug_irq, - NULL, - max96712_hot_plug_detect_irq_handler, - IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | IRQF_ONESHOT, - "max96712_hot_plug", - max96712); - if (ret) - dev_err(dev, "failed to request hot plug irq (%d)\n", ret); - disable_irq(max96712->hot_plug_irq); + } else { + ret = devm_request_threaded_irq(dev, + max96712->hot_plug_irq, + NULL, + max96712_hot_plug_detect_irq_handler, + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | IRQF_ONESHOT, + "max96712_hot_plug", + max96712); + if (ret) { + dev_err(dev, "failed to request hot plug irq (%d)\n", ret); + max96712->hot_plug_irq = -1; + } else { + disable_irq(max96712->hot_plug_irq); + } + } } pm_runtime_set_active(dev); diff --git a/drivers/media/i2c/max96722.c b/drivers/media/i2c/max96722.c index 5d1b9bb4b465..2f2f6d5f65cb 100644 --- a/drivers/media/i2c/max96722.c +++ b/drivers/media/i2c/max96722.c @@ -6,6 +6,7 @@ * * V0.0X01.0X00 first version. * V1.0X00.0X00 Support New Driver Framework. + * V1.0X01.0X00 serdes read /write api depend on i2c id index. * */ @@ -34,7 +35,7 @@ #include #include -#define DRIVER_VERSION KERNEL_VERSION(1, 0x00, 0x00) +#define DRIVER_VERSION KERNEL_VERSION(1, 0x01, 0x00) #ifndef V4L2_CID_DIGITAL_GAIN #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN @@ -55,49 +56,49 @@ #define MAX96717_CHIP_ID 0xBF #define MAX96717_REG_CHIP_ID 0x0D -#define MAX96722_REMOTE_CTRL 0x0003 -#define MAX96722_REMOTE_DISABLE 0xFF - /* max96722->link mask: link type = bit[7:4], link mask = bit[3:0] */ -#define MAX96722_GMSL_TYPE_LINK_A BIT(4) -#define MAX96722_GMSL_TYPE_LINK_B BIT(5) -#define MAX96722_GMSL_TYPE_LINK_C BIT(6) -#define MAX96722_GMSL_TYPE_LINK_D BIT(7) -#define MAX96722_GMSL_TYPE_MASK 0xF0 /* bit[7:4], GMSL link type: 0 = GMSL1, 1 = GMSL2 */ +#define MAXIM_GMSL_TYPE_LINK_A BIT(4) +#define MAXIM_GMSL_TYPE_LINK_B BIT(5) +#define MAXIM_GMSL_TYPE_LINK_C BIT(6) +#define MAXIM_GMSL_TYPE_LINK_D BIT(7) +#define MAXIM_GMSL_TYPE_MASK 0xF0 /* bit[7:4], GMSL link type: 0 = GMSL1, 1 = GMSL2 */ -#define MAX96722_LOCK_STATE_LINK_A BIT(0) -#define MAX96722_LOCK_STATE_LINK_B BIT(1) -#define MAX96722_LOCK_STATE_LINK_C BIT(2) -#define MAX96722_LOCK_STATE_LINK_D BIT(3) -#define MAX96722_LOCK_STATE_MASK 0x0F /* bit[3:0], GMSL link mask: 1 = disable, 1 = enable */ +#define MAXIM_GMSL_LOCK_LINK_A BIT(0) +#define MAXIM_GMSL_LOCK_LINK_B BIT(1) +#define MAXIM_GMSL_LOCK_LINK_C BIT(2) +#define MAXIM_GMSL_LOCK_LINK_D BIT(3) +#define MAXIM_GMSL_LOCK_MASK 0x0F /* bit[3:0], GMSL link mask: 1 = disable, 1 = enable */ -#define MAX96722_FORCE_ALL_CLOCK_EN 1 /* 1: enable, 0: disable */ - -#define REG_NULL 0xFFFF +#define MAXIM_FORCE_ALL_CLOCK_EN 1 /* 1: enable, 0: disable */ #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default" #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep" #define MAX96722_NAME "max96722" +#define REG_NULL 0xFFFF + /* register length: 8bit or 16bit */ -#define MAX96722_REG_LENGTH_08BIT 1 -#define MAX96722_REG_LENGTH_16BIT 2 +#define DEV_REG_LENGTH_08BITS 1 +#define DEV_REG_LENGTH_16BITS 2 /* register value: 8bit or 16bit or 24bit */ -#define MAX96722_REG_VALUE_08BIT 1 -#define MAX96722_REG_VALUE_16BIT 2 -#define MAX96722_REG_VALUE_24BIT 3 +#define DEV_REG_VALUE_08BITS 1 +#define DEV_REG_VALUE_16BITS 2 +#define DEV_REG_VALUE_24BITS 3 -#define MAX96722_I2C_ADDR (0x29) -#define MAX9295_I2C_ADDR (0x40) -#define MAX96715_I2C_ADDR (0x40) -#define MAX96717_I2C_ADDR (0x40) -#define CAMERA_I2C_ADDR (0x36) +/* i2c device default address */ +#define SER_I2C_ADDR (0x40) +#define CAM_I2C_ADDR (0x30) + +/* Maxim Serdes I2C Device ID */ +enum { + I2C_DEV_DES = 0, + I2C_DEV_SER, + I2C_DEV_CAM, + I2C_DEV_MAX +}; -#define MAX96722_GET_BIT(x, bit) ((x & (1 << bit)) >> bit) -#define MAX96722_GET_BIT_M_TO_N(x, m, n) \ - ((unsigned int)(x << (31 - (n))) >> ((31 - (n)) + (m))) static const char *const max96722_supply_names[] = { "avdd", /* Analog power */ @@ -108,7 +109,7 @@ static const char *const max96722_supply_names[] = { #define MAX96722_NUM_SUPPLIES ARRAY_SIZE(max96722_supply_names) struct regval { - u16 i2c_addr; + u16 i2c_id; u16 reg_len; u16 reg; u8 val; @@ -132,6 +133,7 @@ struct max96722_mode { struct max96722 { struct i2c_client *client; + u16 i2c_addr[I2C_DEV_MAX]; struct clk *xvclk; struct gpio_desc *power_gpio; struct gpio_desc *reset_gpio; @@ -196,119 +198,119 @@ static struct rkmodule_csi_dphy_param rk3588_dcphy_param = { /* Max96715 */ static const struct regval max96722_mipi_4lane_1280x800_30fps[] = { // Link A/B/C/D all use GMSL1, and disabled - { 0x29, 2, 0x0006, 0x00, 0x00, 0x00 }, // Link A/B/C/D: select GMSL1, Disabled + { I2C_DEV_DES, 2, 0x0006, 0x00, 0x00, 0x00 }, // Link A/B/C/D: select GMSL1, Disabled // Disable MIPI CSI output - { 0x29, 2, 0x040B, 0x00, 0x00, 0x00 }, // CSI_OUT_EN=0, CSI output disabled + { I2C_DEV_DES, 2, 0x040B, 0x00, 0x00, 0x00 }, // CSI_OUT_EN=0, CSI output disabled // Increase CMU voltage - { 0x29, 2, 0x06C2, 0x10, 0x00, 0x0a }, // Increase CMU voltage to for wide temperature range + { I2C_DEV_DES, 2, 0x06C2, 0x10, 0x00, 0x0a }, // Increase CMU voltage to for wide temperature range // VGAHiGain - { 0x29, 2, 0x14D1, 0x03, 0x00, 0x00 }, // VGAHiGain - { 0x29, 2, 0x15D1, 0x03, 0x00, 0x00 }, // VGAHiGain - { 0x29, 2, 0x16D1, 0x03, 0x00, 0x00 }, // VGAHiGain - { 0x29, 2, 0x17D1, 0x03, 0x00, 0x0a }, // VGAHiGain + { I2C_DEV_DES, 2, 0x14D1, 0x03, 0x00, 0x00 }, // VGAHiGain + { I2C_DEV_DES, 2, 0x15D1, 0x03, 0x00, 0x00 }, // VGAHiGain + { I2C_DEV_DES, 2, 0x16D1, 0x03, 0x00, 0x00 }, // VGAHiGain + { I2C_DEV_DES, 2, 0x17D1, 0x03, 0x00, 0x0a }, // VGAHiGain // SSC Configuration - { 0x29, 2, 0x1445, 0x00, 0x00, 0x00 }, // Disable SSC - { 0x29, 2, 0x1545, 0x00, 0x00, 0x00 }, // Disable SSC - { 0x29, 2, 0x1645, 0x00, 0x00, 0x00 }, // Disable SSC - { 0x29, 2, 0x1745, 0x00, 0x00, 0x0a }, // Disable SSC + { I2C_DEV_DES, 2, 0x1445, 0x00, 0x00, 0x00 }, // Disable SSC + { I2C_DEV_DES, 2, 0x1545, 0x00, 0x00, 0x00 }, // Disable SSC + { I2C_DEV_DES, 2, 0x1645, 0x00, 0x00, 0x00 }, // Disable SSC + { I2C_DEV_DES, 2, 0x1745, 0x00, 0x00, 0x0a }, // Disable SSC // GMSL1 configuration to match serializer - { 0x29, 2, 0x0B07, 0x84, 0x00, 0x00 }, // Enable HVEN and DBL (application specific) - { 0x29, 2, 0x0C07, 0x84, 0x00, 0x00 }, // Enable HVEN and DBL (application specific) - { 0x29, 2, 0x0D07, 0x84, 0x00, 0x00 }, // Enable HVEN and DBL (application specific) - { 0x29, 2, 0x0E07, 0x84, 0x00, 0x00 }, // Enable HVEN and DBL (application specific) - { 0x29, 2, 0x0B0F, 0x01, 0x00, 0x00 }, // Disable processing HS and DE signals(required when paring with GMSL1 parallel serializers) - { 0x29, 2, 0x0C0F, 0x01, 0x00, 0x00 }, // Disable processing HS and DE signals(required when paring with GMSL1 parallel serializers) - { 0x29, 2, 0x0D0F, 0x01, 0x00, 0x00 }, // Disable processing HS and DE signals(required when paring with GMSL1 parallel serializers) - { 0x29, 2, 0x0E0F, 0x01, 0x00, 0x00 }, // Disable processing HS and DE signals(required when paring with GMSL1 parallel serializers) + { I2C_DEV_DES, 2, 0x0B07, 0x84, 0x00, 0x00 }, // Enable HVEN and DBL (application specific) + { I2C_DEV_DES, 2, 0x0C07, 0x84, 0x00, 0x00 }, // Enable HVEN and DBL (application specific) + { I2C_DEV_DES, 2, 0x0D07, 0x84, 0x00, 0x00 }, // Enable HVEN and DBL (application specific) + { I2C_DEV_DES, 2, 0x0E07, 0x84, 0x00, 0x00 }, // Enable HVEN and DBL (application specific) + { I2C_DEV_DES, 2, 0x0B0F, 0x01, 0x00, 0x00 }, // Disable processing HS and DE signals(required when paring with GMSL1 parallel serializers) + { I2C_DEV_DES, 2, 0x0C0F, 0x01, 0x00, 0x00 }, // Disable processing HS and DE signals(required when paring with GMSL1 parallel serializers) + { I2C_DEV_DES, 2, 0x0D0F, 0x01, 0x00, 0x00 }, // Disable processing HS and DE signals(required when paring with GMSL1 parallel serializers) + { I2C_DEV_DES, 2, 0x0E0F, 0x01, 0x00, 0x00 }, // Disable processing HS and DE signals(required when paring with GMSL1 parallel serializers) // Send YUV422, FS, and FE from Video Pipe 0 to Controller 1 - { 0x29, 2, 0x090B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings - { 0x29, 2, 0x092D, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1; + { I2C_DEV_DES, 2, 0x090B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings + { I2C_DEV_DES, 2, 0x092D, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1; // For the following MSB 2 bits = VC, LSB 6 bits = DT - { 0x29, 2, 0x090D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit - { 0x29, 2, 0x090E, 0x1e, 0x00, 0x00 }, // DST0 VC = 0, DT = YUV422 8bit - { 0x29, 2, 0x090F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start - { 0x29, 2, 0x0910, 0x00, 0x00, 0x00 }, // DST1 VC = 0, DT = Frame Start - { 0x29, 2, 0x0911, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End - { 0x29, 2, 0x0912, 0x01, 0x00, 0x00 }, // DST2 VC = 0, DT = Frame End + { I2C_DEV_DES, 2, 0x090D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit + { I2C_DEV_DES, 2, 0x090E, 0x1e, 0x00, 0x00 }, // DST0 VC = 0, DT = YUV422 8bit + { I2C_DEV_DES, 2, 0x090F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start + { I2C_DEV_DES, 2, 0x0910, 0x00, 0x00, 0x00 }, // DST1 VC = 0, DT = Frame Start + { I2C_DEV_DES, 2, 0x0911, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End + { I2C_DEV_DES, 2, 0x0912, 0x01, 0x00, 0x00 }, // DST2 VC = 0, DT = Frame End // Send YUV422, FS, and FE from Video Pipe 1 to Controller 1 - { 0x29, 2, 0x094B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings - { 0x29, 2, 0x096D, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1; + { I2C_DEV_DES, 2, 0x094B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings + { I2C_DEV_DES, 2, 0x096D, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1; // For the following MSB 2 bits = VC, LSB 6 bits = DT - { 0x29, 2, 0x094D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit - { 0x29, 2, 0x094E, 0x5e, 0x00, 0x00 }, // DST0 VC = 1, DT = YUV422 8bit - { 0x29, 2, 0x094F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start - { 0x29, 2, 0x0950, 0x40, 0x00, 0x00 }, // DST1 VC = 1, DT = Frame Start - { 0x29, 2, 0x0951, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End - { 0x29, 2, 0x0952, 0x41, 0x00, 0x00 }, // DST2 VC = 1, DT = Frame End + { I2C_DEV_DES, 2, 0x094D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit + { I2C_DEV_DES, 2, 0x094E, 0x5e, 0x00, 0x00 }, // DST0 VC = 1, DT = YUV422 8bit + { I2C_DEV_DES, 2, 0x094F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start + { I2C_DEV_DES, 2, 0x0950, 0x40, 0x00, 0x00 }, // DST1 VC = 1, DT = Frame Start + { I2C_DEV_DES, 2, 0x0951, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End + { I2C_DEV_DES, 2, 0x0952, 0x41, 0x00, 0x00 }, // DST2 VC = 1, DT = Frame End // Send YUV422, FS, and FE from Video Pipe 2 to Controller 1 - { 0x29, 2, 0x098B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings - { 0x29, 2, 0x09AD, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1; + { I2C_DEV_DES, 2, 0x098B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings + { I2C_DEV_DES, 2, 0x09AD, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1; // For the following MSB 2 bits = VC, LSB 6 bits = DT - { 0x29, 2, 0x098D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit - { 0x29, 2, 0x098E, 0x9e, 0x00, 0x00 }, // DST0 VC = 2, DT = YUV422 8bit - { 0x29, 2, 0x098F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start - { 0x29, 2, 0x0990, 0x80, 0x00, 0x00 }, // DST1 VC = 2, DT = Frame Start - { 0x29, 2, 0x0991, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End - { 0x29, 2, 0x0992, 0x81, 0x00, 0x00 }, // DST2 VC = 2, DT = Frame End + { I2C_DEV_DES, 2, 0x098D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit + { I2C_DEV_DES, 2, 0x098E, 0x9e, 0x00, 0x00 }, // DST0 VC = 2, DT = YUV422 8bit + { I2C_DEV_DES, 2, 0x098F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start + { I2C_DEV_DES, 2, 0x0990, 0x80, 0x00, 0x00 }, // DST1 VC = 2, DT = Frame Start + { I2C_DEV_DES, 2, 0x0991, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End + { I2C_DEV_DES, 2, 0x0992, 0x81, 0x00, 0x00 }, // DST2 VC = 2, DT = Frame End // Send YUV422, FS, and FE from Video Pipe 3 to Controller 1 - { 0x29, 2, 0x09CB, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings - { 0x29, 2, 0x09ED, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1; + { I2C_DEV_DES, 2, 0x09CB, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings + { I2C_DEV_DES, 2, 0x09ED, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1; // For the following MSB 2 bits = VC, LSB 6 bits = DT - { 0x29, 2, 0x09CD, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit - { 0x29, 2, 0x09CE, 0xde, 0x00, 0x00 }, // DST0 VC = 3, DT = YUV422 8bit - { 0x29, 2, 0x09CF, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start - { 0x29, 2, 0x09D0, 0xc0, 0x00, 0x00 }, // DST1 VC = 3, DT = Frame Start - { 0x29, 2, 0x09D1, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End - { 0x29, 2, 0x09D2, 0xc1, 0x00, 0x00 }, // DST2 VC = 3, DT = Frame End + { I2C_DEV_DES, 2, 0x09CD, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit + { I2C_DEV_DES, 2, 0x09CE, 0xde, 0x00, 0x00 }, // DST0 VC = 3, DT = YUV422 8bit + { I2C_DEV_DES, 2, 0x09CF, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start + { I2C_DEV_DES, 2, 0x09D0, 0xc0, 0x00, 0x00 }, // DST1 VC = 3, DT = Frame Start + { I2C_DEV_DES, 2, 0x09D1, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End + { I2C_DEV_DES, 2, 0x09D2, 0xc1, 0x00, 0x00 }, // DST2 VC = 3, DT = Frame End // MIPI PHY Setting - { 0x29, 2, 0x08A0, 0x24, 0x00, 0x00 }, // DPHY0 enabled as clock, MIPI PHY Mode: 2x4 mode + { I2C_DEV_DES, 2, 0x08A0, 0x24, 0x00, 0x00 }, // DPHY0 enabled as clock, MIPI PHY Mode: 2x4 mode // Set Lane Mapping for 4-lane port A - { 0x29, 2, 0x08A3, 0xe4, 0x00, 0x00 }, // PHY1 D1->D3, D0->D2; PHY0 D1->D1, D0->D0 + { I2C_DEV_DES, 2, 0x08A3, 0xe4, 0x00, 0x00 }, // PHY1 D1->D3, D0->D2; PHY0 D1->D1, D0->D0 // Set 4 lane D-PHY, 2bit VC - { 0x29, 2, 0x090A, 0xc0, 0x00, 0x00 }, // MIPI PHY 0: 4 lanes, DPHY, 2bit VC - { 0x29, 2, 0x094A, 0xc0, 0x00, 0x00 }, // MIPI PHY 1: 4 lanes, DPHY, 2bit VC + { I2C_DEV_DES, 2, 0x090A, 0xc0, 0x00, 0x00 }, // MIPI PHY 0: 4 lanes, DPHY, 2bit VC + { I2C_DEV_DES, 2, 0x094A, 0xc0, 0x00, 0x00 }, // MIPI PHY 1: 4 lanes, DPHY, 2bit VC // Turn on MIPI PHYs - { 0x29, 2, 0x08A2, 0x34, 0x00, 0x00 }, // Enable MIPI PHY 0/1, t_lpx = 106.7ns + { I2C_DEV_DES, 2, 0x08A2, 0x34, 0x00, 0x00 }, // Enable MIPI PHY 0/1, t_lpx = 106.7ns // Enable software override for all pipes since GMSL1 data is parallel mode, bpp=8, dt=0x1e(yuv-8) - { 0x29, 2, 0x040B, 0x40, 0x00, 0x00 }, // pipe 0 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 - { 0x29, 2, 0x040C, 0x00, 0x00, 0x00 }, // pipe 0 and 1 VC software override: 0x00 - { 0x29, 2, 0x040D, 0x00, 0x00, 0x00 }, // pipe 2 and 3 VC software override: 0x00 - { 0x29, 2, 0x040E, 0x5e, 0x00, 0x00 }, // pipe 0 DT=0x1E: YUV422 8-bit - { 0x29, 2, 0x040F, 0x7e, 0x00, 0x00 }, // pipe 1 DT=0x1E: YUV422 8-bit - { 0x29, 2, 0x0410, 0x7a, 0x00, 0x00 }, // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit - { 0x29, 2, 0x0411, 0x48, 0x00, 0x00 }, // pipe 1 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 - { 0x29, 2, 0x0412, 0x20, 0x00, 0x00 }, // pipe 2 bpp=0x08, pipe 3 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 - { 0x29, 2, 0x0415, 0xc0, 0xc0, 0x00 }, // pipe 0/1 enable software overide - { 0x29, 2, 0x0418, 0xc0, 0xc0, 0x00 }, // pipe 2/3 enable software overide - { 0x29, 2, 0x041A, 0xf0, 0x00, 0x00 }, // pipe 0/1/2/3: Enable YUV8-/10-bit mux mode + { I2C_DEV_DES, 2, 0x040B, 0x40, 0x00, 0x00 }, // pipe 0 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + { I2C_DEV_DES, 2, 0x040C, 0x00, 0x00, 0x00 }, // pipe 0 and 1 VC software override: 0x00 + { I2C_DEV_DES, 2, 0x040D, 0x00, 0x00, 0x00 }, // pipe 2 and 3 VC software override: 0x00 + { I2C_DEV_DES, 2, 0x040E, 0x5e, 0x00, 0x00 }, // pipe 0 DT=0x1E: YUV422 8-bit + { I2C_DEV_DES, 2, 0x040F, 0x7e, 0x00, 0x00 }, // pipe 1 DT=0x1E: YUV422 8-bit + { I2C_DEV_DES, 2, 0x0410, 0x7a, 0x00, 0x00 }, // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit + { I2C_DEV_DES, 2, 0x0411, 0x48, 0x00, 0x00 }, // pipe 1 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + { I2C_DEV_DES, 2, 0x0412, 0x20, 0x00, 0x00 }, // pipe 2 bpp=0x08, pipe 3 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + { I2C_DEV_DES, 2, 0x0415, 0xc0, 0xc0, 0x00 }, // pipe 0/1 enable software overide + { I2C_DEV_DES, 2, 0x0418, 0xc0, 0xc0, 0x00 }, // pipe 2/3 enable software overide + { I2C_DEV_DES, 2, 0x041A, 0xf0, 0x00, 0x00 }, // pipe 0/1/2/3: Enable YUV8-/10-bit mux mode // Enable all links and pipes - { 0x29, 2, 0x0003, 0xaa, 0x00, 0x00 }, // Enable Remote Control Channel Link A/B/C/D for Port 0 - { 0x29, 2, 0x0006, 0x0f, 0x00, 0x64 }, // Enable all links and pipes + { I2C_DEV_DES, 2, 0x0003, 0xaa, 0x00, 0x00 }, // Enable Remote Control Channel Link A/B/C/D for Port 0 + { I2C_DEV_DES, 2, 0x0006, 0x0f, 0x00, 0x64 }, // Enable all links and pipes // Serializer Setting - { 0x40, 1, 0x04, 0x47, 0x00, 0x05 }, // main_control: Enable CLINK - { 0x40, 1, 0x07, 0x84, 0x00, 0x00 }, // Config SerDes: DBL=1, BWS=0, HIBW=0, PXL_CRC=0, HVEN=1 - { 0x40, 1, 0x67, 0xc4, 0x00, 0x00 }, // Double Alignment Mode: Align at each rising edge of HS - { 0x40, 1, 0x0F, 0xbf, 0x00, 0x00 }, // Enable Set GPO, GPO Output High - { 0x40, 1, 0x3F, 0x08, 0x00, 0x00 }, // Crossbar HS: DIN8 - { 0x40, 1, 0x40, 0x2d, 0x00, 0x00 }, // Crossbar VS: DIN13, INVERT_MUX_VS - { 0x40, 1, 0x20, 0x10, 0x00, 0x00 }, - { 0x40, 1, 0x21, 0x11, 0x00, 0x00 }, - { 0x40, 1, 0x22, 0x12, 0x00, 0x00 }, - { 0x40, 1, 0x23, 0x13, 0x00, 0x00 }, - { 0x40, 1, 0x24, 0x14, 0x00, 0x00 }, - { 0x40, 1, 0x25, 0x15, 0x00, 0x00 }, - { 0x40, 1, 0x26, 0x16, 0x00, 0x00 }, - { 0x40, 1, 0x27, 0x17, 0x00, 0x00 }, - { 0x40, 1, 0x30, 0x00, 0x00, 0x00 }, - { 0x40, 1, 0x31, 0x01, 0x00, 0x00 }, - { 0x40, 1, 0x32, 0x02, 0x00, 0x00 }, - { 0x40, 1, 0x33, 0x03, 0x00, 0x00 }, - { 0x40, 1, 0x34, 0x04, 0x00, 0x00 }, - { 0x40, 1, 0x35, 0x05, 0x00, 0x00 }, - { 0x40, 1, 0x36, 0x06, 0x00, 0x00 }, - { 0x40, 1, 0x37, 0x07, 0x00, 0x00 }, - { 0x40, 1, 0x04, 0x87, 0x00, 0x05 }, // main_control: Enable Serialization - { 0x29, 2, REG_NULL, 0x00, 0x00, 0x00 }, + { I2C_DEV_SER, 1, 0x04, 0x47, 0x00, 0x05 }, // main_control: Enable CLINK + { I2C_DEV_SER, 1, 0x07, 0x84, 0x00, 0x00 }, // Config SerDes: DBL=1, BWS=0, HIBW=0, PXL_CRC=0, HVEN=1 + { I2C_DEV_SER, 1, 0x67, 0xc4, 0x00, 0x00 }, // Double Alignment Mode: Align at each rising edge of HS + { I2C_DEV_SER, 1, 0x0F, 0xbf, 0x00, 0x00 }, // Enable Set GPO, GPO Output High + { I2C_DEV_SER, 1, 0x3F, 0x08, 0x00, 0x00 }, // Crossbar HS: DIN8 + { I2C_DEV_SER, 1, 0x40, 0x2d, 0x00, 0x00 }, // Crossbar VS: DIN13, INVERT_MUX_VS + { I2C_DEV_SER, 1, 0x20, 0x10, 0x00, 0x00 }, + { I2C_DEV_SER, 1, 0x21, 0x11, 0x00, 0x00 }, + { I2C_DEV_SER, 1, 0x22, 0x12, 0x00, 0x00 }, + { I2C_DEV_SER, 1, 0x23, 0x13, 0x00, 0x00 }, + { I2C_DEV_SER, 1, 0x24, 0x14, 0x00, 0x00 }, + { I2C_DEV_SER, 1, 0x25, 0x15, 0x00, 0x00 }, + { I2C_DEV_SER, 1, 0x26, 0x16, 0x00, 0x00 }, + { I2C_DEV_SER, 1, 0x27, 0x17, 0x00, 0x00 }, + { I2C_DEV_SER, 1, 0x30, 0x00, 0x00, 0x00 }, + { I2C_DEV_SER, 1, 0x31, 0x01, 0x00, 0x00 }, + { I2C_DEV_SER, 1, 0x32, 0x02, 0x00, 0x00 }, + { I2C_DEV_SER, 1, 0x33, 0x03, 0x00, 0x00 }, + { I2C_DEV_SER, 1, 0x34, 0x04, 0x00, 0x00 }, + { I2C_DEV_SER, 1, 0x35, 0x05, 0x00, 0x00 }, + { I2C_DEV_SER, 1, 0x36, 0x06, 0x00, 0x00 }, + { I2C_DEV_SER, 1, 0x37, 0x07, 0x00, 0x00 }, + { I2C_DEV_SER, 1, 0x04, 0x87, 0x00, 0x05 }, // main_control: Enable Serialization + { I2C_DEV_DES, 2, REG_NULL, 0x00, 0x00, 0x00 }, }; static const struct max96722_mode supported_modes_4lane[] = { @@ -360,9 +362,11 @@ static const s64 link_freq_items[] = { MAX96722_LINK_FREQ_MHZ(1250), }; -static int max96722_write_reg(struct i2c_client *client, - u16 client_addr, u16 reg, u16 reg_len, u16 val_len, u32 val) +static int max96722_write_reg(struct max96722 *max96722, u8 i2c_id, + u16 reg, u16 reg_len, u16 val_len, u32 val) { + struct i2c_client *client = max96722->client; + u16 client_addr = max96722->i2c_addr[i2c_id]; u32 buf_i, val_i; u8 buf[6]; u8 *val_p; @@ -404,9 +408,11 @@ static int max96722_write_reg(struct i2c_client *client, return 0; } -static int max96722_read_reg(struct i2c_client *client, - u16 client_addr, u16 reg, u16 reg_len, u16 val_len, u8 *val) +static int max96722_read_reg(struct max96722 *max96722, u8 i2c_id, + u16 reg, u16 reg_len, u16 val_len, u8 *val) { + struct i2c_client *client = max96722->client; + u16 client_addr = max96722->i2c_addr[i2c_id]; struct i2c_msg msgs[2]; u8 *data_be_p; __be32 data_be = 0; @@ -451,27 +457,27 @@ static int max96722_read_reg(struct i2c_client *client, return 0; } -static int max96722_update_reg_bits(struct i2c_client *client, - u16 client_addr, u16 reg, u16 reg_len, u8 mask, u8 val) +static int max96722_update_reg_bits(struct max96722 *max96722, u8 i2c_id, + u16 reg, u16 reg_len, u8 mask, u8 val) { u8 value; - u32 val_len = MAX96722_REG_VALUE_08BIT; + u32 val_len = DEV_REG_VALUE_08BITS; int ret; - ret = max96722_read_reg(client, client_addr, reg, reg_len, val_len, &value); + ret = max96722_read_reg(max96722, i2c_id, reg, reg_len, val_len, &value); if (ret) return ret; value &= ~mask; value |= (val & mask); - ret = max96722_write_reg(client, client_addr, reg, reg_len, val_len, value); + ret = max96722_write_reg(max96722, i2c_id, reg, reg_len, val_len, value); if (ret) return ret; return 0; } -static int max96722_write_array(struct i2c_client *client, +static int max96722_write_array(struct max96722 *max96722, const struct regval *regs) { u32 i; @@ -479,13 +485,13 @@ static int max96722_write_array(struct i2c_client *client, for (i = 0; ret == 0 && regs[i].reg != REG_NULL; i++) { if (regs[i].mask != 0) - ret = max96722_update_reg_bits(client, regs[i].i2c_addr, + ret = max96722_update_reg_bits(max96722, regs[i].i2c_id, regs[i].reg, regs[i].reg_len, regs[i].mask, regs[i].val); else - ret = max96722_write_reg(client, regs[i].i2c_addr, - regs[i].reg, regs[i].reg_len, - MAX96722_REG_VALUE_08BIT, regs[i].val); + ret = max96722_write_reg(max96722, regs[i].i2c_id, + regs[i].reg, regs[i].reg_len, + DEV_REG_VALUE_08BITS, regs[i].val); if (regs[i].delay != 0) msleep(regs[i].delay); @@ -496,14 +502,13 @@ static int max96722_write_array(struct i2c_client *client, static int max96722_check_local_chipid(struct max96722 *max96722) { - struct i2c_client *client = max96722->client; struct device *dev = &max96722->client->dev; int ret; u8 id = 0; - ret = max96722_read_reg(client, MAX96722_I2C_ADDR, - MAX96722_REG_CHIP_ID, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, &id); + ret = max96722_read_reg(max96722, I2C_DEV_DES, + MAX96722_REG_CHIP_ID, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &id); if ((ret != 0) || (id != MAX96722_CHIP_ID)) { dev_err(dev, "Unexpected MAX96722 chip id(%02x), ret(%d)\n", id, ret); return -ENODEV; @@ -525,9 +530,9 @@ static int __maybe_unused max96722_check_remote_chipid(struct max96722 *max96722 id = 0; #if 0 // max96717 - ret = max96722_read_reg(max96722->client, MAX96717_I2C_ADDR, - MAX96717_REG_CHIP_ID, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, &id); + ret = max96722_read_reg(max96722, I2C_DEV_SER, + MAX96717_REG_CHIP_ID, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &id); if ((ret != 0) || (id != MAX96717_CHIP_ID)) { dev_err(dev, "Unexpected MAX96717 chip id(%02x), ret(%d)\n", id, ret); return -ENODEV; @@ -537,9 +542,9 @@ static int __maybe_unused max96722_check_remote_chipid(struct max96722 *max96722 #if 0 // max9295 - ret = max96722_read_reg(max96722->client, MAX9295_I2C_ADDR, - MAX9295_REG_CHIP_ID, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, &id); + ret = max96722_read_reg(max96722, I2C_DEV_SER, + MAX9295_REG_CHIP_ID, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &id); if ((ret != 0) || (id != MAX9295_CHIP_ID)) { dev_err(dev, "Unexpected MAX9295 chip id(%02x), ret(%d)\n", id, ret); return -ENODEV; @@ -549,9 +554,9 @@ static int __maybe_unused max96722_check_remote_chipid(struct max96722 *max96722 #if 0 // max96715 - ret = max96722_read_reg(max96722->client, MAX96715_I2C_ADDR, - MAX96715_REG_CHIP_ID, MAX96722_REG_LENGTH_08BIT, - MAX96722_REG_VALUE_08BIT, &id); + ret = max96722_read_reg(max96722, I2C_DEV_SER, + MAX96715_REG_CHIP_ID, DEV_REG_LENGTH_08BITS, + DEV_REG_VALUE_08BITS, &id); if ((ret != 0) || (id != MAX96715_CHIP_ID)) { dev_err(dev, "Unexpected MAX96715 chip id(%02x), ret(%d)\n", id, ret); return -ENODEV; @@ -564,96 +569,95 @@ static int __maybe_unused max96722_check_remote_chipid(struct max96722 *max96722 static u8 max96722_get_link_lock_state(struct max96722 *max96722, u8 link_mask) { - struct i2c_client *client = max96722->client; struct device *dev = &max96722->client->dev; u8 lock = 0, lock_state = 0; u8 link_type = 0; - link_type = max96722->link_mask & MAX96722_GMSL_TYPE_MASK; + link_type = max96722->link_mask & MAXIM_GMSL_TYPE_MASK; - if (link_mask & MAX96722_LOCK_STATE_LINK_A) { - if (link_type & MAX96722_GMSL_TYPE_LINK_A) { + if (link_mask & MAXIM_GMSL_LOCK_LINK_A) { + if (link_type & MAXIM_GMSL_TYPE_LINK_A) { // GMSL2 LinkA - max96722_read_reg(client, MAX96722_I2C_ADDR, - 0x001a, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, &lock); + max96722_read_reg(max96722, I2C_DEV_DES, + 0x001a, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &lock); if (lock & BIT(3)) { - lock_state |= MAX96722_LOCK_STATE_LINK_A; + lock_state |= MAXIM_GMSL_LOCK_LINK_A; dev_info(dev, "GMSL2 LinkA locked\n"); } } else { // GMSL1 LinkA - max96722_read_reg(client, MAX96722_I2C_ADDR, - 0x0bcb, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, &lock); + max96722_read_reg(max96722, I2C_DEV_DES, + 0x0bcb, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &lock); if (lock & BIT(0)) { - lock_state |= MAX96722_LOCK_STATE_LINK_A; + lock_state |= MAXIM_GMSL_LOCK_LINK_A; dev_info(dev, "GMSL1 LinkA locked\n"); } } } - if (link_mask & MAX96722_LOCK_STATE_LINK_B) { - if (link_type & MAX96722_GMSL_TYPE_LINK_B) { + if (link_mask & MAXIM_GMSL_LOCK_LINK_B) { + if (link_type & MAXIM_GMSL_TYPE_LINK_B) { // GMSL2 LinkB - max96722_read_reg(client, MAX96722_I2C_ADDR, - 0x000a, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, &lock); + max96722_read_reg(max96722, I2C_DEV_DES, + 0x000a, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &lock); if (lock & BIT(3)) { - lock_state |= MAX96722_LOCK_STATE_LINK_B; + lock_state |= MAXIM_GMSL_LOCK_LINK_B; dev_info(dev, "GMSL2 LinkB locked\n"); } } else { // GMSL1 LinkB - max96722_read_reg(client, MAX96722_I2C_ADDR, - 0x0ccb, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, &lock); + max96722_read_reg(max96722, I2C_DEV_DES, + 0x0ccb, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &lock); if (lock & BIT(0)) { - lock_state |= MAX96722_LOCK_STATE_LINK_B; + lock_state |= MAXIM_GMSL_LOCK_LINK_B; dev_info(dev, "GMSL1 LinkB locked\n"); } } } - if (link_mask & MAX96722_LOCK_STATE_LINK_C) { - if (link_type & MAX96722_GMSL_TYPE_LINK_C) { + if (link_mask & MAXIM_GMSL_LOCK_LINK_C) { + if (link_type & MAXIM_GMSL_TYPE_LINK_C) { // GMSL2 LinkC - max96722_read_reg(client, MAX96722_I2C_ADDR, - 0x000b, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, &lock); + max96722_read_reg(max96722, I2C_DEV_DES, + 0x000b, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &lock); if (lock & BIT(3)) { - lock_state |= MAX96722_LOCK_STATE_LINK_C; + lock_state |= MAXIM_GMSL_LOCK_LINK_C; dev_info(dev, "GMSL2 LinkC locked\n"); } } else { // GMSL1 LinkC - max96722_read_reg(client, MAX96722_I2C_ADDR, - 0x0dcb, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, &lock); + max96722_read_reg(max96722, I2C_DEV_DES, + 0x0dcb, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &lock); if (lock & BIT(0)) { - lock_state |= MAX96722_LOCK_STATE_LINK_C; + lock_state |= MAXIM_GMSL_LOCK_LINK_C; dev_info(dev, "GMSL1 LinkC locked\n"); } } } - if (link_mask & MAX96722_LOCK_STATE_LINK_D) { - if (link_type & MAX96722_GMSL_TYPE_LINK_D) { + if (link_mask & MAXIM_GMSL_LOCK_LINK_D) { + if (link_type & MAXIM_GMSL_TYPE_LINK_D) { // GMSL2 LinkD - max96722_read_reg(client, MAX96722_I2C_ADDR, - 0x000c, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, &lock); + max96722_read_reg(max96722, I2C_DEV_DES, + 0x000c, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &lock); if (lock & BIT(3)) { - lock_state |= MAX96722_LOCK_STATE_LINK_D; + lock_state |= MAXIM_GMSL_LOCK_LINK_D; dev_info(dev, "GMSL2 LinkD locked\n"); } } else { // GMSL1 LinkD - max96722_read_reg(client, MAX96722_I2C_ADDR, - 0x0ecb, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, &lock); + max96722_read_reg(max96722, I2C_DEV_DES, + 0x0ecb, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &lock); if (lock & BIT(0)) { - lock_state |= MAX96722_LOCK_STATE_LINK_D; + lock_state |= MAXIM_GMSL_LOCK_LINK_D; dev_info(dev, "GMSL1 LinkD locked\n"); } } @@ -664,7 +668,6 @@ static u8 max96722_get_link_lock_state(struct max96722 *max96722, u8 link_mask) static int max96722_check_link_lock_state(struct max96722 *max96722) { - struct i2c_client *client = max96722->client; struct device *dev = &max96722->client->dev; u8 lock_state = 0, link_mask = 0, link_type = 0; int ret, i, time_ms; @@ -677,89 +680,89 @@ static int max96722_check_link_lock_state(struct max96722 *max96722) * CTRL0: Enable REG_ENABLE * CTRL2: Enable REG_MNL */ - max96722_update_reg_bits(client, MAX96722_I2C_ADDR, - 0x0017, MAX96722_REG_LENGTH_16BIT, BIT(2), BIT(2)); - max96722_update_reg_bits(client, MAX96722_I2C_ADDR, - 0x0019, MAX96722_REG_LENGTH_16BIT, BIT(4), BIT(4)); + max96722_update_reg_bits(max96722, I2C_DEV_DES, + 0x0017, DEV_REG_LENGTH_16BITS, BIT(2), BIT(2)); + max96722_update_reg_bits(max96722, I2C_DEV_DES, + 0x0019, DEV_REG_LENGTH_16BITS, BIT(4), BIT(4)); // CSI output disabled - max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x040B, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0x00); + max96722_write_reg(max96722, I2C_DEV_DES, + 0x040B, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x00); // All links select mode by link_type and disable at beginning. - link_type = max96722->link_mask & MAX96722_GMSL_TYPE_MASK; - max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x0006, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, link_type); + link_type = max96722->link_mask & MAXIM_GMSL_TYPE_MASK; + max96722_write_reg(max96722, I2C_DEV_DES, + 0x0006, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, link_type); // Link Rate // Link A ~ Link D Transmitter Rate: 187.5Mbps, Receiver Rate: 3Gbps - max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x0010, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0x11); - max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x0011, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0x11); + max96722_write_reg(max96722, I2C_DEV_DES, + 0x0010, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x11); + max96722_write_reg(max96722, I2C_DEV_DES, + 0x0011, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x11); // GMSL1: Enable HIM on deserializer on Link A/B/C/D - if ((link_type & MAX96722_GMSL_TYPE_LINK_A) == 0) { - max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x0B06, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0xEF); + if ((link_type & MAXIM_GMSL_TYPE_LINK_A) == 0) { + max96722_write_reg(max96722, I2C_DEV_DES, + 0x0B06, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xEF); } - if ((link_type & MAX96722_GMSL_TYPE_LINK_B) == 0) { - max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x0C06, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0xEF); + if ((link_type & MAXIM_GMSL_TYPE_LINK_B) == 0) { + max96722_write_reg(max96722, I2C_DEV_DES, + 0x0C06, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xEF); } - if ((link_type & MAX96722_GMSL_TYPE_LINK_C) == 0) { - max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x0D06, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0xEF); + if ((link_type & MAXIM_GMSL_TYPE_LINK_C) == 0) { + max96722_write_reg(max96722, I2C_DEV_DES, + 0x0D06, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xEF); } - if ((link_type & MAX96722_GMSL_TYPE_LINK_D) == 0) { - max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x0E06, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0xEF); + if ((link_type & MAXIM_GMSL_TYPE_LINK_D) == 0) { + max96722_write_reg(max96722, I2C_DEV_DES, + 0x0E06, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xEF); } // Link A ~ Link D One-Shot Reset depend on link_mask - link_mask = max96722->link_mask & MAX96722_LOCK_STATE_MASK; - max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x0018, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, link_mask); + link_mask = max96722->link_mask & MAXIM_GMSL_LOCK_MASK; + max96722_write_reg(max96722, I2C_DEV_DES, + 0x0018, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, link_mask); // Link A ~ Link D enable depend on link_type and link_mask - max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x0006, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, link_type | link_mask); + max96722_write_reg(max96722, I2C_DEV_DES, + 0x0006, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, link_type | link_mask); time_ms = 50; msleep(time_ms); for (i = 0; i < 20; i++) { - if ((lock_state & MAX96722_LOCK_STATE_LINK_A) == 0) - if (max96722_get_link_lock_state(max96722, MAX96722_LOCK_STATE_LINK_A)) { - lock_state |= MAX96722_LOCK_STATE_LINK_A; + if ((lock_state & MAXIM_GMSL_LOCK_LINK_A) == 0) + if (max96722_get_link_lock_state(max96722, MAXIM_GMSL_LOCK_LINK_A)) { + lock_state |= MAXIM_GMSL_LOCK_LINK_A; dev_info(dev, "LinkA locked time: %d ms\n", time_ms); } - if ((lock_state & MAX96722_LOCK_STATE_LINK_B) == 0) - if (max96722_get_link_lock_state(max96722, MAX96722_LOCK_STATE_LINK_B)) { - lock_state |= MAX96722_LOCK_STATE_LINK_B; + if ((lock_state & MAXIM_GMSL_LOCK_LINK_B) == 0) + if (max96722_get_link_lock_state(max96722, MAXIM_GMSL_LOCK_LINK_B)) { + lock_state |= MAXIM_GMSL_LOCK_LINK_B; dev_info(dev, "LinkB locked time: %d ms\n", time_ms); } - if ((lock_state & MAX96722_LOCK_STATE_LINK_C) == 0) - if (max96722_get_link_lock_state(max96722, MAX96722_LOCK_STATE_LINK_C)) { - lock_state |= MAX96722_LOCK_STATE_LINK_C; + if ((lock_state & MAXIM_GMSL_LOCK_LINK_C) == 0) + if (max96722_get_link_lock_state(max96722, MAXIM_GMSL_LOCK_LINK_C)) { + lock_state |= MAXIM_GMSL_LOCK_LINK_C; dev_info(dev, "LinkC locked time: %d ms\n", time_ms); } - if ((lock_state & MAX96722_LOCK_STATE_LINK_D) == 0) - if (max96722_get_link_lock_state(max96722, MAX96722_LOCK_STATE_LINK_D)) { - lock_state |= MAX96722_LOCK_STATE_LINK_D; + if ((lock_state & MAXIM_GMSL_LOCK_LINK_D) == 0) + if (max96722_get_link_lock_state(max96722, MAXIM_GMSL_LOCK_LINK_D)) { + lock_state |= MAXIM_GMSL_LOCK_LINK_D; dev_info(dev, "LinkD locked time: %d ms\n", time_ms); } @@ -790,7 +793,7 @@ static irqreturn_t max96722_hot_plug_detect_irq_handler(int irq, void *dev_id) struct device *dev = &max96722->client->dev; u8 lock_state = 0, link_mask = 0; - link_mask = max96722->link_mask & MAX96722_LOCK_STATE_MASK; + link_mask = max96722->link_mask & MAXIM_GMSL_LOCK_MASK; if (max96722->streaming) { lock_state = max96722_get_link_lock_state(max96722, link_mask); if (lock_state == link_mask) { @@ -803,21 +806,21 @@ static irqreturn_t max96722_hot_plug_detect_irq_handler(int irq, void *dev_id) return IRQ_HANDLED; } -static int __maybe_unused max96722_dphy_dpll_predef_set(struct i2c_client *client, - u32 link_freq_mhz) +static int max96722_dphy_dpll_predef_set(struct max96722 *max96722, u32 link_freq_mhz) { + struct device *dev = &max96722->client->dev; int ret = 0; u8 dpll_val = 0, dpll_lock = 0; u8 mipi_tx_phy_enable = 0; - ret = max96722_read_reg(client, MAX96722_I2C_ADDR, - 0x08A2, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, &mipi_tx_phy_enable); + ret = max96722_read_reg(max96722, I2C_DEV_DES, + 0x08A2, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &mipi_tx_phy_enable); if (ret) return ret; mipi_tx_phy_enable = (mipi_tx_phy_enable & 0xF0) >> 4; - dev_info(&client->dev, "DPLL predef set: mipi_tx_phy_enable = 0x%02x, link_freq_mhz = %d\n", + dev_info(dev, "DPLL predef set: mipi_tx_phy_enable = 0x%02x, link_freq_mhz = %d\n", mipi_tx_phy_enable, link_freq_mhz); // dphy max data rate is 2500MHz @@ -831,116 +834,117 @@ static int __maybe_unused max96722_dphy_dpll_predef_set(struct i2c_client *clien // MIPI PHY0 if (mipi_tx_phy_enable & BIT(0)) { // Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x1C00, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, - 0xf4); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x1C00, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xf4); // Set data rate and enable software override - ret |= max96722_update_reg_bits(client, MAX96722_I2C_ADDR, - 0x0415, MAX96722_REG_LENGTH_16BIT, 0x3F, dpll_val); + ret |= max96722_update_reg_bits(max96722, I2C_DEV_DES, + 0x0415, DEV_REG_LENGTH_16BITS, 0x3F, dpll_val); // Release reset to DPLL (config_soft_rst_n = 1) - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x1C00, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0xf5); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x1C00, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xf5); } // MIPI PHY1 if (mipi_tx_phy_enable & BIT(1)) { // Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x1D00, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0xf4); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x1D00, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xf4); // Set data rate and enable software override - ret |= max96722_update_reg_bits(client, MAX96722_I2C_ADDR, - 0x0418, MAX96722_REG_LENGTH_16BIT, 0x3F, dpll_val); + ret |= max96722_update_reg_bits(max96722, I2C_DEV_DES, + 0x0418, DEV_REG_LENGTH_16BITS, 0x3F, dpll_val); // Release reset to DPLL (config_soft_rst_n = 1) - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x1D00, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0xf5); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x1D00, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xf5); } // MIPI PHY2 if (mipi_tx_phy_enable & BIT(2)) { // Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x1E00, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0xf4); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x1E00, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xf4); // Set data rate and enable software override - ret |= max96722_update_reg_bits(client, MAX96722_I2C_ADDR, - 0x041B, MAX96722_REG_LENGTH_16BIT, 0x3F, dpll_val); + ret |= max96722_update_reg_bits(max96722, I2C_DEV_DES, + 0x041B, DEV_REG_LENGTH_16BITS, 0x3F, dpll_val); // Release reset to DPLL (config_soft_rst_n = 1) - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x1E00, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0xf5); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x1E00, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xf5); } // MIPI PHY3 if (mipi_tx_phy_enable & BIT(3)) { // Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x1F00, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0xf4); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x1F00, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xf4); // Set data rate and enable software override - ret |= max96722_update_reg_bits(client, MAX96722_I2C_ADDR, - 0x041E, MAX96722_REG_LENGTH_16BIT, 0x3F, dpll_val); + ret |= max96722_update_reg_bits(max96722, I2C_DEV_DES, + 0x041E, DEV_REG_LENGTH_16BITS, 0x3F, dpll_val); // Release reset to DPLL (config_soft_rst_n = 1) - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x1F00, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0xf5); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x1F00, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xf5); } if (ret) { - dev_err(&client->dev, "DPLL predef set error!\n"); + dev_err(dev, "DPLL predef set error!\n"); return ret; } ret = read_poll_timeout(max96722_read_reg, ret, !(ret < 0) && (dpll_lock & 0xF0), 1000, 10000, false, - client, MAX96722_I2C_ADDR, - 0x0400, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, &dpll_lock); + max96722, I2C_DEV_DES, + 0x0400, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, &dpll_lock); if (ret < 0) { - dev_err(&client->dev, "DPLL is not locked, dpll_lock = 0x%02x\n", dpll_lock); + dev_err(dev, "DPLL is not locked, dpll_lock = 0x%02x\n", dpll_lock); return ret; } else { - dev_err(&client->dev, "DPLL is locked, dpll_lock = 0x%02x\n", dpll_lock); + dev_err(dev, "DPLL is locked, dpll_lock = 0x%02x\n", dpll_lock); return 0; } } -static int max96722_auto_init_deskew(struct i2c_client *client, u32 deskew_mask) +static int max96722_auto_init_deskew(struct max96722 *max96722, u32 deskew_mask) { + struct device *dev = &max96722->client->dev; int ret = 0; - dev_info(&client->dev, "Auto initial deskew: deskew_mask = 0x%02x\n", deskew_mask); + dev_info(dev, "Auto initial deskew: deskew_mask = 0x%02x\n", deskew_mask); // D-PHY Deskew Initial Calibration Control if (deskew_mask & BIT(0)) // MIPI PHY0 - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x0903, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0x80); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x0903, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x80); if (deskew_mask & BIT(1)) // MIPI PHY1 - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x0943, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0x80); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x0943, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x80); if (deskew_mask & BIT(2)) // MIPI PHY2 - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x0983, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0x80); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x0983, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x80); if (deskew_mask & BIT(3)) // MIPI PHY3 - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x09C3, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0x80); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x09C3, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x80); return ret; } -static int max96722_frame_sync_period(struct i2c_client *client, u32 period) +static int max96722_frame_sync_period(struct max96722 *max96722, u32 period) { + struct device *dev = &max96722->client->dev; u32 pclk, fsync_peroid; u8 fsync_peroid_h, fsync_peroid_m, fsync_peroid_l; int ret = 0; @@ -948,23 +952,23 @@ static int max96722_frame_sync_period(struct i2c_client *client, u32 period) if (period == 0) return 0; - dev_info(&client->dev, "Frame sync period = %d\n", period); + dev_info(dev, "Frame sync period = %d\n", period); -#if 1 // TODO: Sensor +#if 1 // TODO: Sensor slave mode // sendor slave mode enable #endif // Master link Video 0 for frame sync generation - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x04A2, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0x00); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x04A2, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x00); // Disable Vsync-Fsync overlap window - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x04AA, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0x00); - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x04AB, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0x00); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x04AA, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x00); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x04AB, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x00); // Set FSYNC period to 25M/30 clock cycles. PCLK = 25MHz. Sync freq = 30Hz pclk = 25 * 1000 * 1000; @@ -972,74 +976,70 @@ static int max96722_frame_sync_period(struct i2c_client *client, u32 period) fsync_peroid_l = (fsync_peroid >> 0) & 0xFF; fsync_peroid_m = (fsync_peroid >> 8) & 0xFF; fsync_peroid_h = (fsync_peroid >> 16) & 0xFF; - dev_info(&client->dev, "Frame sync period: H = 0x%02x, M = 0x%02x, L = 0x%02x\n", + dev_info(dev, "Frame sync period: H = 0x%02x, M = 0x%02x, L = 0x%02x\n", fsync_peroid_h, fsync_peroid_m, fsync_peroid_l); // FSYNC_PERIOD_H - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x04A7, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, fsync_peroid_h); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x04A7, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, fsync_peroid_h); // FSYNC_PERIOD_M - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x04A6, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, fsync_peroid_m); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x04A6, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, fsync_peroid_m); // FSYNC_PERIOD_L - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x04A5, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, fsync_peroid_l); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x04A5, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, fsync_peroid_l); // FSYNC is GMSL2 type, use osc for fsync, include all links/pipes in fsync gen - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x04AF, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0xcf); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x04AF, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0xcf); -#if 1 // TODO: FSYNC GPIO +#if 1 // TODO: Desrializer MFP // FSYNC_TX_ID: set 4 to match MFP4 on serializer side - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x04B1, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0x20); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x04B1, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x20); #endif -#if 1 // TODO: Serializer +#if 1 // TODO: Serializer MFP // Enable GPIO_RX_EN on serializer MFP4 - ret |= max96722_write_reg(client, 0x40, - 0x02CA, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0x84); + ret |= max96722_write_reg(max96722, I2C_DEV_SER, + 0x02CA, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x84); #endif // MFP2, VS not gen internally, GPIO not used to gen fsync, manual mode - ret |= max96722_write_reg(client, MAX96722_I2C_ADDR, - 0x04A0, MAX96722_REG_LENGTH_16BIT, - MAX96722_REG_VALUE_08BIT, 0x04); + ret |= max96722_write_reg(max96722, I2C_DEV_DES, + 0x04A0, DEV_REG_LENGTH_16BITS, + DEV_REG_VALUE_08BITS, 0x04); return ret; } -static int max96722_mipi_enable(struct i2c_client *client, bool enable) +static int max96722_mipi_enable(struct max96722 *max96722, bool enable) { int ret = 0; if (enable) { -#if MAX96722_FORCE_ALL_CLOCK_EN +#if MAXIM_FORCE_ALL_CLOCK_EN // Force all MIPI clocks running - ret |= max96722_update_reg_bits(client, - MAX96722_I2C_ADDR, - 0x08A0, MAX96722_REG_LENGTH_16BIT, BIT(7), BIT(7)); + ret |= max96722_update_reg_bits(max96722, I2C_DEV_DES, + 0x08A0, DEV_REG_LENGTH_16BITS, BIT(7), BIT(7)); #endif // CSI output enabled - ret |= max96722_update_reg_bits(client, - MAX96722_I2C_ADDR, - 0x040B, MAX96722_REG_LENGTH_16BIT, BIT(1), BIT(1)); + ret |= max96722_update_reg_bits(max96722, I2C_DEV_DES, + 0x040B, DEV_REG_LENGTH_16BITS, BIT(1), BIT(1)); } else { -#if MAX96722_FORCE_ALL_CLOCK_EN +#if MAXIM_FORCE_ALL_CLOCK_EN // Normal mode - ret |= max96722_update_reg_bits(client, - MAX96722_I2C_ADDR, - 0x08A0, MAX96722_REG_LENGTH_16BIT, BIT(7), 0x00); + ret |= max96722_update_reg_bits(max96722, I2C_DEV_DES, + 0x08A0, DEV_REG_LENGTH_16BITS, BIT(7), 0x00); #endif // CSI output disabled - ret |= max96722_update_reg_bits(client, - MAX96722_I2C_ADDR, - 0x040B, MAX96722_REG_LENGTH_16BIT, BIT(1), 0x00); + ret |= max96722_update_reg_bits(max96722, I2C_DEV_DES, + 0x040B, DEV_REG_LENGTH_16BITS, BIT(1), 0x00); } return ret; @@ -1244,9 +1244,9 @@ static long max96722_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) stream = *((u32 *)arg); if (stream) - ret = max96722_mipi_enable(max96722->client, true); + ret = max96722_mipi_enable(max96722, true); else - ret = max96722_mipi_enable(max96722->client, false); + ret = max96722_mipi_enable(max96722, false); break; case RKMODULE_GET_VICAP_RST_INFO: max96722_get_vicap_rst_inf( @@ -1423,26 +1423,26 @@ static int __max96722_start_stream(struct max96722 *max96722) if (max96722->hot_plug_irq > 0) enable_irq(max96722->hot_plug_irq); - ret = max96722_write_array(max96722->client, + ret = max96722_write_array(max96722, max96722->cur_mode->reg_list); if (ret) return ret; link_freq_idx = max96722->cur_mode->link_freq_idx; link_freq_mhz = (u32)div_s64(link_freq_items[link_freq_idx], 1000000L); - ret = max96722_dphy_dpll_predef_set(max96722->client, link_freq_mhz); + ret = max96722_dphy_dpll_predef_set(max96722, link_freq_mhz); if (ret) return ret; if (max96722->auto_init_deskew_mask != 0) { - ret = max96722_auto_init_deskew(max96722->client, + ret = max96722_auto_init_deskew(max96722, max96722->auto_init_deskew_mask); if (ret) return ret; } if (max96722->frame_sync_period != 0) { - ret = max96722_frame_sync_period(max96722->client, + ret = max96722_frame_sync_period(max96722, max96722->frame_sync_period); if (ret) return ret; @@ -1455,7 +1455,7 @@ static int __max96722_start_stream(struct max96722 *max96722) if (ret) return ret; - return max96722_mipi_enable(max96722->client, true); + return max96722_mipi_enable(max96722, true); } @@ -1464,7 +1464,7 @@ static int __max96722_stop_stream(struct max96722 *max96722) if (max96722->hot_plug_irq > 0) disable_irq(max96722->hot_plug_irq); - return max96722_mipi_enable(max96722->client, false); + return max96722_mipi_enable(max96722, false); } static int max96722_s_stream(struct v4l2_subdev *sd, int on) @@ -1837,8 +1837,19 @@ static int max96722_parse_dt(struct max96722 *max96722) struct device *dev = &max96722->client->dev; struct device_node *node = dev->of_node; u8 mipi_data_lanes = max96722->bus_cfg.bus.mipi_csi2.num_data_lanes; + u32 value = 0; int ret = 0; + /* serializer i2c address */ + ret = of_property_read_u32(node, "ser-i2c-addr", &value); + if (ret) { + max96722->i2c_addr[I2C_DEV_SER] = SER_I2C_ADDR; + } else { + dev_info(dev, "ser-i2c-addr property: %d\n", value); + max96722->i2c_addr[I2C_DEV_SER] = value; + } + dev_info(dev, "serializer i2c address: 0x%02x\n", max96722->i2c_addr[I2C_DEV_SER]); + /* max96722 link mask: * bit[3:0] = link enable mask: 0 = disable, 1 = enable: * bit0 - LinkA, bit1 - LinkB, bit2 - LinkC, bit3 - LinkD @@ -1853,7 +1864,7 @@ static int max96722_parse_dt(struct max96722 *max96722) else max96722->link_mask = 0x33; /* Link A/B: GMSL2 and enable */ } else { - dev_info(dev, "link-mask property: 0x%x\n", max96722->link_mask); + dev_info(dev, "link-mask property: 0x%08x\n", max96722->link_mask); } dev_info(dev, "serdes link mask: 0x%02x\n", max96722->link_mask); @@ -1915,6 +1926,11 @@ static int max96722_probe(struct i2c_client *client, max96722->client = client; i2c_set_clientdata(client, max96722); + /* i2c default address init */ + max96722->i2c_addr[I2C_DEV_DES] = client->addr; + max96722->i2c_addr[I2C_DEV_SER] = SER_I2C_ADDR; + max96722->i2c_addr[I2C_DEV_CAM] = CAM_I2C_ADDR; + endpoint = of_graph_get_next_endpoint(dev->of_node, NULL); if (!endpoint) { dev_err(dev, "Failed to get endpoint\n"); @@ -1992,7 +2008,7 @@ static int max96722_probe(struct i2c_client *client, if (ret) goto err_free_handler; - ret = max96722_check_link_lock_state(max96722); + ret = max96722_check_local_chipid(max96722); if (ret) goto err_power_off; diff --git a/drivers/media/i2c/sc031gs.c b/drivers/media/i2c/sc031gs.c index bfee857f7bee..7c82cf69a9f3 100644 --- a/drivers/media/i2c/sc031gs.c +++ b/drivers/media/i2c/sc031gs.c @@ -1040,8 +1040,7 @@ static int sc031gs_set_ctrl(struct v4l2_ctrl *ctrl) ctrl->val + sc031gs->cur_mode->height); if (!ret) sc031gs->cur_vts = ctrl->val + sc031gs->cur_mode->height; - if (sc031gs->cur_vts != sc031gs->cur_mode->vts_def) - sc031gs_modify_fps_info(sc031gs); + sc031gs_modify_fps_info(sc031gs); break; case V4L2_CID_TEST_PATTERN: ret = sc031gs_enable_test_pattern(sc031gs, ctrl->val); diff --git a/drivers/media/i2c/sc035gs.c b/drivers/media/i2c/sc035gs.c index 376308201648..eb0877e0d791 100644 --- a/drivers/media/i2c/sc035gs.c +++ b/drivers/media/i2c/sc035gs.c @@ -1021,8 +1021,7 @@ static int sc035gs_set_ctrl(struct v4l2_ctrl *ctrl) ctrl->val + sc035gs->cur_mode->height); if (!ret) sc035gs->cur_vts = ctrl->val + sc035gs->cur_mode->height; - if (sc035gs->cur_vts != sc035gs->cur_mode->vts_def) - sc035gs_modify_fps_info(sc035gs); + sc035gs_modify_fps_info(sc035gs); break; case V4L2_CID_TEST_PATTERN: ret = sc035gs_enable_test_pattern(sc035gs, ctrl->val); diff --git a/drivers/media/i2c/sc132gs.c b/drivers/media/i2c/sc132gs.c index 3fa0e33af5c3..1309df925a7c 100644 --- a/drivers/media/i2c/sc132gs.c +++ b/drivers/media/i2c/sc132gs.c @@ -1136,8 +1136,7 @@ static int sc132gs_set_ctrl(struct v4l2_ctrl *ctrl) ctrl->val + sc132gs->cur_mode->height); if (!ret) sc132gs->cur_vts = ctrl->val + sc132gs->cur_mode->height; - if (sc132gs->cur_vts != sc132gs->cur_mode->vts_def) - sc132gs_modify_fps_info(sc132gs); + sc132gs_modify_fps_info(sc132gs); break; break; case V4L2_CID_TEST_PATTERN: diff --git a/drivers/media/i2c/sc200ai.c b/drivers/media/i2c/sc200ai.c index 140ebbff3a37..8452f27def63 100644 --- a/drivers/media/i2c/sc200ai.c +++ b/drivers/media/i2c/sc200ai.c @@ -1733,8 +1733,7 @@ static int sc200ai_set_ctrl(struct v4l2_ctrl *ctrl) & 0xff); if (!ret) sc200ai->cur_vts = ctrl->val + sc200ai->cur_mode->height; - if (sc200ai->cur_vts != sc200ai->cur_mode->vts_def) - sc200ai_modify_fps_info(sc200ai); + sc200ai_modify_fps_info(sc200ai); break; case V4L2_CID_TEST_PATTERN: ret = sc200ai_enable_test_pattern(sc200ai, ctrl->val); diff --git a/drivers/media/i2c/sc210iot.c b/drivers/media/i2c/sc210iot.c index 14e149105bdd..314981e15426 100644 --- a/drivers/media/i2c/sc210iot.c +++ b/drivers/media/i2c/sc210iot.c @@ -408,8 +408,7 @@ static int sc210iot_set_ctrl(struct v4l2_ctrl *ctrl) (ctrl->val + sc210iot->cur_mode->height) & 0xff); if (!ret) sc210iot->cur_vts = ctrl->val + sc210iot->cur_mode->height; - if (sc210iot->cur_vts != sc210iot->cur_mode->vts_def) - sc210iot_modify_fps_info(sc210iot); + sc210iot_modify_fps_info(sc210iot); break; case V4L2_CID_HFLIP: regmap_update_bits(sc210iot->regmap, SC210IOT_REG_MIRROR_FLIP, diff --git a/drivers/media/i2c/sc2232.c b/drivers/media/i2c/sc2232.c index d6b8df0e5fc1..e8a3e80ddca6 100644 --- a/drivers/media/i2c/sc2232.c +++ b/drivers/media/i2c/sc2232.c @@ -1205,8 +1205,7 @@ static int sc2232_set_ctrl(struct v4l2_ctrl *ctrl) ctrl->val + sc2232->cur_mode->height); if (!ret) sc2232->cur_vts = ctrl->val + sc2232->cur_mode->height; - if (sc2232->cur_vts != sc2232->cur_mode->vts_def) - sc2232_modify_fps_info(sc2232); + sc2232_modify_fps_info(sc2232); dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val); break; diff --git a/drivers/media/i2c/sc2239.c b/drivers/media/i2c/sc2239.c index 6e08a185f1a6..210bdfd4cde5 100644 --- a/drivers/media/i2c/sc2239.c +++ b/drivers/media/i2c/sc2239.c @@ -970,8 +970,7 @@ static int sc2239_set_ctrl(struct v4l2_ctrl *ctrl) ctrl->val + sc2239->cur_mode->height); if (!ret) sc2239->cur_vts = ctrl->val + sc2239->cur_mode->height; - if (sc2239->cur_vts != sc2239->cur_mode->vts_def) - sc2239_modify_fps_info(sc2239); + sc2239_modify_fps_info(sc2239); break; case V4L2_CID_TEST_PATTERN: ret = sc2239_enable_test_pattern(sc2239, ctrl->val); diff --git a/drivers/media/i2c/sc223a.c b/drivers/media/i2c/sc223a.c index 07031b942338..e578ac9f551d 100644 --- a/drivers/media/i2c/sc223a.c +++ b/drivers/media/i2c/sc223a.c @@ -1243,8 +1243,7 @@ static int sc223a_set_ctrl(struct v4l2_ctrl *ctrl) (ctrl->val + sc223a->cur_mode->height) & 0xff); sc223a->cur_vts = ctrl->val + sc223a->cur_mode->height; - if (sc223a->cur_vts != sc223a->cur_mode->vts_def) - sc223a_modify_fps_info(sc223a); + sc223a_modify_fps_info(sc223a); break; case V4L2_CID_TEST_PATTERN: ret = sc223a_enable_test_pattern(sc223a, ctrl->val); diff --git a/drivers/media/i2c/sc230ai.c b/drivers/media/i2c/sc230ai.c index 9bbdb859fea3..4cf8e3d84249 100644 --- a/drivers/media/i2c/sc230ai.c +++ b/drivers/media/i2c/sc230ai.c @@ -1458,8 +1458,7 @@ static int sc230ai_set_ctrl(struct v4l2_ctrl *ctrl) (ctrl->val + sc230ai->cur_mode->height) & 0xff); sc230ai->cur_vts = ctrl->val + sc230ai->cur_mode->height; - if (sc230ai->cur_vts != sc230ai->cur_mode->vts_def) - sc230ai_modify_fps_info(sc230ai); + sc230ai_modify_fps_info(sc230ai); break; case V4L2_CID_TEST_PATTERN: ret = sc230ai_enable_test_pattern(sc230ai, ctrl->val); diff --git a/drivers/media/i2c/sc2310.c b/drivers/media/i2c/sc2310.c index 865354ddd781..ab74a1bde67c 100644 --- a/drivers/media/i2c/sc2310.c +++ b/drivers/media/i2c/sc2310.c @@ -1639,8 +1639,7 @@ static int sc2310_set_ctrl(struct v4l2_ctrl *ctrl) ctrl->val + sc2310->cur_mode->height); if (!ret) sc2310->cur_vts = ctrl->val + sc2310->cur_mode->height; - if (sc2310->cur_vts != sc2310->cur_mode->vts_def) - sc2310_modify_fps_info(sc2310); + sc2310_modify_fps_info(sc2310); dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val); break; diff --git a/drivers/media/i2c/sc301iot.c b/drivers/media/i2c/sc301iot.c index 3dc04a050a71..2826aa394865 100644 --- a/drivers/media/i2c/sc301iot.c +++ b/drivers/media/i2c/sc301iot.c @@ -1941,8 +1941,7 @@ static int SC301IOT_set_ctrl(struct v4l2_ctrl *ctrl) & 0xff); if (!ret) SC301IOT->cur_vts = ctrl->val + SC301IOT->cur_mode->height; - if (SC301IOT->cur_vts != SC301IOT->cur_mode->vts_def) - SC301IOT_modify_fps_info(SC301IOT); + SC301IOT_modify_fps_info(SC301IOT); break; case V4L2_CID_TEST_PATTERN: ret = SC301IOT_enable_test_pattern(SC301IOT, ctrl->val); diff --git a/drivers/media/i2c/sc3336.c b/drivers/media/i2c/sc3336.c index 5b2428a1ddb5..5d29ae76f8c3 100644 --- a/drivers/media/i2c/sc3336.c +++ b/drivers/media/i2c/sc3336.c @@ -1371,8 +1371,7 @@ static int sc3336_set_ctrl(struct v4l2_ctrl *ctrl) (ctrl->val + sc3336->cur_mode->height) & 0xff); sc3336->cur_vts = ctrl->val + sc3336->cur_mode->height; - if (sc3336->cur_vts != sc3336->cur_mode->vts_def) - sc3336_modify_fps_info(sc3336); + sc3336_modify_fps_info(sc3336); break; case V4L2_CID_TEST_PATTERN: ret = sc3336_enable_test_pattern(sc3336, ctrl->val); diff --git a/drivers/media/i2c/sc3338.c b/drivers/media/i2c/sc3338.c index 70412caa3450..4f5a02f21c01 100644 --- a/drivers/media/i2c/sc3338.c +++ b/drivers/media/i2c/sc3338.c @@ -1190,8 +1190,7 @@ static int sc3338_set_ctrl(struct v4l2_ctrl *ctrl) (ctrl->val + sc3338->cur_mode->height) & 0xff); sc3338->cur_vts = ctrl->val + sc3338->cur_mode->height; - if (sc3338->cur_vts != sc3338->cur_mode->vts_def) - sc3338_modify_fps_info(sc3338); + sc3338_modify_fps_info(sc3338); break; case V4L2_CID_TEST_PATTERN: ret = sc3338_enable_test_pattern(sc3338, ctrl->val); diff --git a/drivers/media/i2c/sc401ai.c b/drivers/media/i2c/sc401ai.c index 5b8ea3a7e49c..ba4a36c1bb4a 100644 --- a/drivers/media/i2c/sc401ai.c +++ b/drivers/media/i2c/sc401ai.c @@ -1320,8 +1320,7 @@ static int sc401ai_set_ctrl(struct v4l2_ctrl *ctrl) & 0xff); if (!ret) sc401ai->cur_vts = ctrl->val + sc401ai->cur_mode->height; - if (sc401ai->cur_vts != sc401ai->cur_mode->vts_def) - sc401ai_modify_fps_info(sc401ai); + sc401ai_modify_fps_info(sc401ai); break; case V4L2_CID_TEST_PATTERN: ret = sc401ai_enable_test_pattern(sc401ai, ctrl->val); diff --git a/drivers/media/i2c/sc4210.c b/drivers/media/i2c/sc4210.c index 5f79a078deb1..c171fa22c4b3 100644 --- a/drivers/media/i2c/sc4210.c +++ b/drivers/media/i2c/sc4210.c @@ -2398,8 +2398,7 @@ static int sc4210_set_ctrl(struct v4l2_ctrl *ctrl) SC4210_REG_VALUE_08BIT, vts & 0xff); sc4210->cur_vts = ctrl->val + sc4210->cur_mode->height; - if (sc4210->cur_vts != sc4210->cur_mode->vts_def) - sc4210_modify_fps_info(sc4210); + sc4210_modify_fps_info(sc4210); dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val); break; case V4L2_CID_HFLIP: diff --git a/drivers/media/i2c/sc4238.c b/drivers/media/i2c/sc4238.c index 05ee4e2945be..4f1fabf801f4 100644 --- a/drivers/media/i2c/sc4238.c +++ b/drivers/media/i2c/sc4238.c @@ -2470,8 +2470,7 @@ static int sc4238_set_ctrl(struct v4l2_ctrl *ctrl) ctrl->val + sc4238->cur_mode->height); if (ret == 0) sc4238->cur_vts = ctrl->val + sc4238->cur_mode->height; - if (sc4238->cur_vts != sc4238->cur_mode->vts_def) - sc4238_modify_fps_info(sc4238); + sc4238_modify_fps_info(sc4238); dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val); break; diff --git a/drivers/media/i2c/sc430cs.c b/drivers/media/i2c/sc430cs.c index 76a820127ff6..447df377e14f 100644 --- a/drivers/media/i2c/sc430cs.c +++ b/drivers/media/i2c/sc430cs.c @@ -1191,8 +1191,7 @@ static int sc430cs_set_ctrl(struct v4l2_ctrl *ctrl) & 0xff); if (!ret) sc430cs->cur_vts = ctrl->val + sc430cs->cur_mode->height; - if (sc430cs->cur_vts != sc430cs->cur_mode->vts_def) - sc430cs_modify_fps_info(sc430cs); + sc430cs_modify_fps_info(sc430cs); break; case V4L2_CID_TEST_PATTERN: ret = sc430cs_enable_test_pattern(sc430cs, ctrl->val); diff --git a/drivers/media/i2c/sc4336.c b/drivers/media/i2c/sc4336.c index 5065b4d3a4f5..970ba507fbab 100644 --- a/drivers/media/i2c/sc4336.c +++ b/drivers/media/i2c/sc4336.c @@ -1188,8 +1188,7 @@ static int sc4336_set_ctrl(struct v4l2_ctrl *ctrl) (ctrl->val + sc4336->cur_mode->height) & 0xff); sc4336->cur_vts = ctrl->val + sc4336->cur_mode->height; - if (sc4336->cur_vts != sc4336->cur_mode->vts_def) - sc4336_modify_fps_info(sc4336); + sc4336_modify_fps_info(sc4336); break; case V4L2_CID_TEST_PATTERN: ret = sc4336_enable_test_pattern(sc4336, ctrl->val); diff --git a/drivers/media/i2c/sc500ai.c b/drivers/media/i2c/sc500ai.c index 2d06d9cd1230..19c65c1052b5 100644 --- a/drivers/media/i2c/sc500ai.c +++ b/drivers/media/i2c/sc500ai.c @@ -1478,8 +1478,7 @@ static int sc500ai_set_ctrl(struct v4l2_ctrl *ctrl) vts & 0xff); if (!ret) sc500ai->cur_vts = vts; - if (sc500ai->cur_vts != sc500ai->cur_mode->vts_def) - sc500ai_modify_fps_info(sc500ai); + sc500ai_modify_fps_info(sc500ai); break; case V4L2_CID_HFLIP: ret = sc500ai_read_reg(sc500ai->client, SC500AI_FLIP_MIRROR_REG, diff --git a/drivers/media/i2c/sc501ai.c b/drivers/media/i2c/sc501ai.c index 0123e224ea13..2652b8576b14 100644 --- a/drivers/media/i2c/sc501ai.c +++ b/drivers/media/i2c/sc501ai.c @@ -1041,8 +1041,7 @@ static int sc501ai_set_ctrl(struct v4l2_ctrl *ctrl) SC501AI_REG_VALUE_08BIT, vts & 0xff); sc501ai->cur_vts = vts; - if (sc501ai->cur_vts != sc501ai->cur_mode->vts_def) - sc501ai_modify_fps_info(sc501ai); + sc501ai_modify_fps_info(sc501ai); break; case V4L2_CID_HFLIP: ret = sc501ai_read_reg(sc501ai->client, SC501AI_FLIP_MIRROR_REG, diff --git a/drivers/media/i2c/sc530ai.c b/drivers/media/i2c/sc530ai.c index c1956a4c543c..58877541bf23 100644 --- a/drivers/media/i2c/sc530ai.c +++ b/drivers/media/i2c/sc530ai.c @@ -1706,8 +1706,7 @@ static int sc530ai_set_ctrl(struct v4l2_ctrl *ctrl) vts & 0xff); if (!ret) sc530ai->cur_vts = vts; - if (sc530ai->cur_vts != sc530ai->cur_mode->vts_def) - sc530ai_modify_fps_info(sc530ai); + sc530ai_modify_fps_info(sc530ai); dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val); break; case V4L2_CID_HFLIP: diff --git a/drivers/media/i2c/sc850sl.c b/drivers/media/i2c/sc850sl.c index 307d9c67c4f4..f7b38ea10b30 100644 --- a/drivers/media/i2c/sc850sl.c +++ b/drivers/media/i2c/sc850sl.c @@ -1399,8 +1399,7 @@ static int sc850sl_set_ctrl(struct v4l2_ctrl *ctrl) ctrl->val + sc850sl->cur_mode->height); if (!ret) sc850sl->cur_vts = ctrl->val + sc850sl->cur_mode->height; - if (sc850sl->cur_vts != sc850sl->cur_mode->vts_def) - sc850sl_modify_fps_info(sc850sl); + sc850sl_modify_fps_info(sc850sl); dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val); break; diff --git a/drivers/media/platform/rockchip/isp/capture_v30.c b/drivers/media/platform/rockchip/isp/capture_v30.c index 2393e0ca1eb8..c757051d2ba9 100644 --- a/drivers/media/platform/rockchip/isp/capture_v30.c +++ b/drivers/media/platform/rockchip/isp/capture_v30.c @@ -789,21 +789,22 @@ static void update_mi(struct rkisp_stream *stream) if (dev->hw_dev->is_unite) { u32 mult = stream->id != RKISP_STREAM_FBC ? 1 : (stream->out_isp_fmt.write_format ? 32 : 24); + u32 div = stream->out_isp_fmt.fourcc == V4L2_PIX_FMT_UYVY ? 1 : 2; reg = stream->config->mi.y_base_ad_init; val = stream->next_buf->buff_addr[RKISP_PLANE_Y]; - val += ((stream->out_fmt.width / 2) & ~0xf); + val += ((stream->out_fmt.width / div) & ~0xf); rkisp_next_write(dev, reg, val, false); reg = stream->config->mi.cb_base_ad_init; val = stream->next_buf->buff_addr[RKISP_PLANE_CB]; - val += ((stream->out_fmt.width / 2) & ~0xf) * mult; + val += ((stream->out_fmt.width / div) & ~0xf) * mult; rkisp_next_write(dev, reg, val, false); if (stream->id != RKISP_STREAM_FBC && stream->id != RKISP_STREAM_BP) { reg = stream->config->mi.cr_base_ad_init; val = stream->next_buf->buff_addr[RKISP_PLANE_CR]; - val += ((stream->out_fmt.width / 2) & ~0xf); + val += ((stream->out_fmt.width / div) & ~0xf); rkisp_next_write(dev, reg, val, false); } } diff --git a/drivers/media/platform/rockchip/isp/dev.c b/drivers/media/platform/rockchip/isp/dev.c index a2aa4db92989..265ca011b22d 100644 --- a/drivers/media/platform/rockchip/isp/dev.c +++ b/drivers/media/platform/rockchip/isp/dev.c @@ -976,6 +976,8 @@ static int __maybe_unused rkisp_runtime_resume(struct device *dev) rkisp_update_sensor_info(isp_dev) >= 0) _set_pipeline_default_fmt(isp_dev, false); + if (isp_dev->hw_dev->is_assigned_clk) + rkisp_clk_dbg = true; isp_dev->cap_dev.wait_line = rkisp_wait_line; isp_dev->cap_dev.wrap_line = rkisp_wrap_line; isp_dev->is_rdbk_auto = rkisp_rdbk_auto; diff --git a/drivers/media/platform/rockchip/isp/hw.c b/drivers/media/platform/rockchip/isp/hw.c index b2982c09a9ac..3e5cf57b1a4e 100644 --- a/drivers/media/platform/rockchip/isp/hw.c +++ b/drivers/media/platform/rockchip/isp/hw.c @@ -740,10 +740,12 @@ static int enable_sys_clk(struct rkisp_hw_dev *dev) } } - rate = dev->clk_rate_tbl[0].clk_rate * 1000000UL; - rkisp_set_clk_rate(dev->clks[0], rate); - if (dev->is_unite) - rkisp_set_clk_rate(dev->clks[5], rate); + if (!dev->is_assigned_clk) { + rate = dev->clk_rate_tbl[0].clk_rate * 1000000UL; + rkisp_set_clk_rate(dev->clks[0], rate); + if (dev->is_unite) + rkisp_set_clk_rate(dev->clks[5], rate); + } rkisp_soft_reset(dev, false); isp_config_clk(dev, true); return 0; @@ -802,6 +804,7 @@ static int rkisp_hw_probe(struct platform_device *pdev) struct resource *res; int i, ret; bool is_mem_reserved = true; + u32 clk_rate = 0; match = of_match_node(rkisp_hw_of_match, node); if (IS_ERR(match)) @@ -895,6 +898,11 @@ static int rkisp_hw_probe(struct platform_device *pdev) hw_dev->clk_rate_tbl = match_data->clk_rate_tbl; hw_dev->num_clk_rate_tbl = match_data->num_clk_rate_tbl; + hw_dev->is_assigned_clk = false; + ret = of_property_read_u32(node, "assigned-clock-rates", &clk_rate); + if (!ret && clk_rate) + hw_dev->is_assigned_clk = true; + hw_dev->reset = devm_reset_control_array_get(dev, false, false); if (IS_ERR(hw_dev->reset)) { dev_dbg(dev, "failed to get reset\n"); diff --git a/drivers/media/platform/rockchip/isp/hw.h b/drivers/media/platform/rockchip/isp/hw.h index 04dedc22921c..ce57aef2fbc6 100644 --- a/drivers/media/platform/rockchip/isp/hw.h +++ b/drivers/media/platform/rockchip/isp/hw.h @@ -104,6 +104,7 @@ struct rkisp_hw_dev { bool is_runing; bool is_frm_buf; bool is_dvfs; + bool is_assigned_clk; }; int rkisp_register_irq(struct rkisp_hw_dev *dev); diff --git a/drivers/media/platform/rockchip/isp/rkisp.c b/drivers/media/platform/rockchip/isp/rkisp.c index 7a3893c8eff3..eaa99e7b4d04 100644 --- a/drivers/media/platform/rockchip/isp/rkisp.c +++ b/drivers/media/platform/rockchip/isp/rkisp.c @@ -732,6 +732,7 @@ run_next: is_upd = true; } else if (is_try) { rkisp_multi_overflow_hdl(dev, true); + rkisp_update_regs(dev, ISP_LDCH_BASE, ISP_LDCH_BASE); is_upd = true; } } @@ -2164,7 +2165,6 @@ static int rkisp_isp_start(struct rkisp_device *dev) dev->isp_err_cnt = 0; dev->isp_isr_cnt = 0; - dev->isp_state = ISP_START | ISP_FRAME_END; dev->irq_ends_mask |= ISP_FRAME_END; dev->irq_ends = 0; @@ -2873,6 +2873,7 @@ static int rkisp_isp_sd_s_stream(struct v4l2_subdev *sd, int on) rkisp_config_cif(isp_dev); rkisp_isp_start(isp_dev); rkisp_global_update_mi(isp_dev); + isp_dev->isp_state = ISP_START | ISP_FRAME_END; rkisp_rdbk_trigger_event(isp_dev, T_CMD_QUEUE, NULL); return 0; } diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c index f40fb9a62545..98672bdac09f 100644 --- a/drivers/mmc/host/dw_mmc-rockchip.c +++ b/drivers/mmc/host/dw_mmc-rockchip.c @@ -168,7 +168,7 @@ static int dw_mci_v2_execute_tuning(struct dw_mci_slot *slot, u32 opcode) * It's impossible all 4 fixed phase won't be able to work. */ for (i = 0; i < ARRAY_SIZE(degrees); i++) { - degree = degrees[i] + priv->last_degree; + degree = degrees[i] + priv->last_degree + 90; degree = degree % 360; clk_set_phase(priv->sample_clk, degree); if (!mmc_send_tuning(mmc, opcode, NULL)) @@ -181,7 +181,7 @@ static int dw_mci_v2_execute_tuning(struct dw_mci_slot *slot, u32 opcode) } done: - dev_info(host->dev, "Successfully tuned phase to %d\n", degrees[i]); + dev_info(host->dev, "Successfully tuned phase to %d\n", degree); priv->last_degree = degree; return 0; } diff --git a/drivers/mtd/nand/spi/dosilicon.c b/drivers/mtd/nand/spi/dosilicon.c index d6e38ae71f08..d1385c1ad818 100644 --- a/drivers/mtd/nand/spi/dosilicon.c +++ b/drivers/mtd/nand/spi/dosilicon.c @@ -9,7 +9,7 @@ #define SPINAND_MFR_DOSILICON 0xE5 -#define DOSICON_STATUS_ECC_MASK GENMASK(7, 4) +#define DOSICON_STATUS_ECC_MASK GENMASK(6, 4) #define DOSICON_STATUS_ECC_NO_BITFLIPS (0 << 4) #define DOSICON_STATUS_ECC_1TO3_BITFLIPS (1 << 4) #define DOSICON_STATUS_ECC_4TO6_BITFLIPS (3 << 4) diff --git a/drivers/mtd/nand/spi/jsc.c b/drivers/mtd/nand/spi/jsc.c index 93fed1c40675..9c421c89c17c 100644 --- a/drivers/mtd/nand/spi/jsc.c +++ b/drivers/mtd/nand/spi/jsc.c @@ -70,12 +70,13 @@ static const struct mtd_ooblayout_ops js28u1gqscahg_ooblayout = { static int js28u1gqscahg_ecc_get_status(struct spinand_device *spinand, u8 status) { - u8 eccsr = (status & GENMASK(6, 4)) >> 2; + struct nand_device *nand = spinand_to_nand(spinand); + u8 eccsr = (status & GENMASK(6, 4)) >> 4; - if (eccsr <= 7) + if (eccsr < 4) return eccsr; - else if (eccsr == 12) - return 8; + else if (eccsr == 4) + return nanddev_get_ecc_requirements(nand)->strength; else return -EBADMSG; } diff --git a/drivers/mtd/nand/spi/unim.c b/drivers/mtd/nand/spi/unim.c index 659921e2a095..ee78420123eb 100644 --- a/drivers/mtd/nand/spi/unim.c +++ b/drivers/mtd/nand/spi/unim.c @@ -69,12 +69,13 @@ static const struct mtd_ooblayout_ops tx25g01_ooblayout = { static int tx25g01_ecc_get_status(struct spinand_device *spinand, u8 status) { - u8 eccsr = (status & GENMASK(6, 4)) >> 2; + struct nand_device *nand = spinand_to_nand(spinand); + u8 eccsr = (status & GENMASK(6, 4)) >> 4; - if (eccsr <= 7) + if (eccsr < 4) return eccsr; - else if (eccsr == 12) - return 8; + else if (eccsr == 4) + return nanddev_get_ecc_requirements(nand)->strength; else return -EBADMSG; } diff --git a/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c index 6b9976bcd110..31e84f74f2c7 100644 --- a/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c @@ -1203,7 +1203,7 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) rockchip_pcie_devmode_update(rockchip, RKEP_MODE_KERNEL, RKEP_SMODE_LNKRDY); rockchip->hot_rst_wq = create_singlethread_workqueue("rkep_hot_rst_wq"); - if (rockchip->hot_rst_wq) { + if (!rockchip->hot_rst_wq) { dev_err(dev, "failed to create hot_rst workqueue\n"); ret = -ENOMEM; goto deinit_phy; diff --git a/drivers/rknpu/include/rknpu_drv.h b/drivers/rknpu/include/rknpu_drv.h index d13a990d23b2..9ec5444f8a6d 100644 --- a/drivers/rknpu/include/rknpu_drv.h +++ b/drivers/rknpu/include/rknpu_drv.h @@ -30,10 +30,10 @@ #define DRIVER_NAME "rknpu" #define DRIVER_DESC "RKNPU driver" -#define DRIVER_DATE "20230625" +#define DRIVER_DATE "20230629" #define DRIVER_MAJOR 0 -#define DRIVER_MINOR 8 -#define DRIVER_PATCHLEVEL 9 +#define DRIVER_MINOR 9 +#define DRIVER_PATCHLEVEL 0 #define LOG_TAG "RKNPU" diff --git a/drivers/rknpu/include/rknpu_ioctl.h b/drivers/rknpu/include/rknpu_ioctl.h index 6294ac59274d..3b0b857108ce 100644 --- a/drivers/rknpu/include/rknpu_ioctl.h +++ b/drivers/rknpu/include/rknpu_ioctl.h @@ -73,8 +73,8 @@ enum e_rknpu_mem_type { RKNPU_MEM_ZEROING = 1 << 5, /* allocate secure buffer */ RKNPU_MEM_SECURE = 1 << 6, - /* allocate from non-dma32 zone */ - RKNPU_MEM_NON_DMA32 = 1 << 7, + /* allocate from dma32 zone */ + RKNPU_MEM_DMA32 = 1 << 7, /* request SRAM */ RKNPU_MEM_TRY_ALLOC_SRAM = 1 << 8, /* request NBUF */ @@ -82,7 +82,7 @@ enum e_rknpu_mem_type { RKNPU_MEM_MASK = RKNPU_MEM_NON_CONTIGUOUS | RKNPU_MEM_CACHEABLE | RKNPU_MEM_WRITE_COMBINE | RKNPU_MEM_KERNEL_MAPPING | RKNPU_MEM_IOMMU | RKNPU_MEM_ZEROING | - RKNPU_MEM_SECURE | RKNPU_MEM_NON_DMA32 | + RKNPU_MEM_SECURE | RKNPU_MEM_DMA32 | RKNPU_MEM_TRY_ALLOC_SRAM | RKNPU_MEM_TRY_ALLOC_NBUF }; diff --git a/drivers/rknpu/rknpu_drv.c b/drivers/rknpu/rknpu_drv.c index 584bdc8dbec8..ad0e22eabaa8 100644 --- a/drivers/rknpu/rknpu_drv.c +++ b/drivers/rknpu/rknpu_drv.c @@ -224,7 +224,6 @@ int rknpu_power_get(struct rknpu_device *rknpu_dev) { int ret = 0; - cancel_delayed_work(&rknpu_dev->power_off_work); mutex_lock(&rknpu_dev->power_lock); if (atomic_inc_return(&rknpu_dev->power_refcount) == 1) ret = rknpu_power_on(rknpu_dev); @@ -247,6 +246,9 @@ int rknpu_power_put(struct rknpu_device *rknpu_dev) static int rknpu_power_put_delay(struct rknpu_device *rknpu_dev) { + if (rknpu_dev->power_put_delay == 0) + return rknpu_power_put(rknpu_dev); + mutex_lock(&rknpu_dev->power_lock); if (atomic_read(&rknpu_dev->power_refcount) == 1) queue_delayed_work( @@ -255,6 +257,7 @@ static int rknpu_power_put_delay(struct rknpu_device *rknpu_dev) else atomic_dec_if_positive(&rknpu_dev->power_refcount); mutex_unlock(&rknpu_dev->power_lock); + return 0; } diff --git a/drivers/rknpu/rknpu_gem.c b/drivers/rknpu/rknpu_gem.c index 3bb84372c5c2..6c08734e0fbc 100644 --- a/drivers/rknpu/rknpu_gem.c +++ b/drivers/rknpu/rknpu_gem.c @@ -67,6 +67,7 @@ static int rknpu_gem_get_pages(struct rknpu_gem_object *rknpu_obj) rknpu_obj->size); goto free_sgt; } + iommu_flush_iotlb_all(iommu_get_domain_for_dev(drm->dev)); if (rknpu_obj->flags & RKNPU_MEM_KERNEL_MAPPING) { rknpu_obj->cookie = vmap(rknpu_obj->pages, rknpu_obj->num_pages, @@ -181,7 +182,9 @@ static int rknpu_gem_alloc_buf(struct rknpu_gem_object *rknpu_obj) if (rknpu_obj->flags & RKNPU_MEM_ZEROING) gfp_mask |= __GFP_ZERO; - if (!(rknpu_obj->flags & RKNPU_MEM_NON_DMA32)) { + if (!rknpu_dev->iommu_en || + rknpu_dev->config->dma_mask <= DMA_BIT_MASK(32) || + (rknpu_obj->flags & RKNPU_MEM_DMA32)) { gfp_mask &= ~__GFP_HIGHMEM; gfp_mask |= __GFP_DMA32; } @@ -360,6 +363,7 @@ static const struct drm_gem_object_funcs rknpu_gem_object_funcs = { static struct rknpu_gem_object *rknpu_gem_init(struct drm_device *drm, unsigned long size) { + struct rknpu_device *rknpu_dev = drm->dev_private; struct rknpu_gem_object *rknpu_obj = NULL; struct drm_gem_object *obj = NULL; gfp_t gfp_mask; @@ -388,7 +392,9 @@ static struct rknpu_gem_object *rknpu_gem_init(struct drm_device *drm, if (rknpu_obj->flags & RKNPU_MEM_ZEROING) gfp_mask |= __GFP_ZERO; - if (!(rknpu_obj->flags & RKNPU_MEM_NON_DMA32)) { + if (!rknpu_dev->iommu_en || + rknpu_dev->config->dma_mask <= DMA_BIT_MASK(32) || + (rknpu_obj->flags & RKNPU_MEM_DMA32)) { gfp_mask &= ~__GFP_HIGHMEM; gfp_mask |= __GFP_DMA32; } diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 425da3d35f18..56577f7df205 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -1198,6 +1198,12 @@ config SPI_SLAVE_SYSTEM_CONTROL SPI slave handler to allow remote control of system reboot, power off, halt, and suspend. +config SPI_SLAVE_ROCKCHIP_OBJ + tristate "Rockchip SPI slave inter transmission protocol demo" + help + SPI slave with a rockchip protocol specification for SPI slave + transmission, work with the corresponding master driver spidev_rkmst. + endif # SPI_SLAVE config SPI_DYNAMIC diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 4b34e855c841..f16ebb35dce9 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -149,3 +149,5 @@ obj-$(CONFIG_SPI_AMD) += spi-amd.o # SPI slave protocol handlers obj-$(CONFIG_SPI_SLAVE_TIME) += spi-slave-time.o obj-$(CONFIG_SPI_SLAVE_SYSTEM_CONTROL) += spi-slave-system-control.o +obj-$(CONFIG_SPI_SLAVE_ROCKCHIP_OBJ) += spidev-rkslv.o +obj-$(CONFIG_SPI_SLAVE_ROCKCHIP_OBJ) += spidev-rkmst.o diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 87603baaa553..297682079647 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -221,6 +221,7 @@ struct rockchip_spi { bool slave_aborted; bool cs_inactive; /* spi slave tansmition stop when cs inactive */ bool cs_high_supported; /* native CS supports active-high polarity */ + struct gpio_desc *ready; /* spi slave transmission ready */ struct spi_transfer *xfer; /* Store xfer temporarily */ phys_addr_t base_addr_phy; @@ -859,9 +860,18 @@ static int rockchip_spi_transfer_one( ret = rockchip_spi_prepare_irq(rs, ctlr, xfer); } + if (rs->ready) { + gpiod_set_value(rs->ready, 0); + udelay(1); + gpiod_set_value(rs->ready, 1); + } + if (ret > 0) ret = rockchip_spi_transfer_wait(ctlr, xfer); + if (rs->ready) + gpiod_set_value(rs->ready, 0); + return ret; } @@ -1178,6 +1188,8 @@ static int rockchip_spi_probe(struct platform_device *pdev) rs->cs_inactive = false; break; } + if (device_property_read_bool(&pdev->dev, "rockchip,cs-inactive-disable")) + rs->cs_inactive = false; pinctrl = devm_pinctrl_get(&pdev->dev); if (!IS_ERR(pinctrl)) { @@ -1188,6 +1200,13 @@ static int rockchip_spi_probe(struct platform_device *pdev) } } + rs->ready = devm_gpiod_get_optional(&pdev->dev, "ready", GPIOD_OUT_HIGH); + if (IS_ERR(rs->ready)) { + ret = dev_err_probe(&pdev->dev, PTR_ERR(rs->ready), + "invalid ready-gpios property in node\n"); + goto err_free_dma_rx; + } + ret = devm_spi_register_controller(&pdev->dev, ctlr); if (ret < 0) { dev_err(&pdev->dev, "Failed to register controller\n"); @@ -1210,7 +1229,8 @@ static int rockchip_spi_probe(struct platform_device *pdev) dev_info(&pdev->dev, "register misc device %s\n", misc_name); } - dev_info(rs->dev, "probed, poll=%d, rsd=%d\n", rs->poll, rs->rsd); + dev_info(rs->dev, "probed, poll=%d, rsd=%d, cs-inactive=%d, ready=%d\n", + rs->poll, rs->rsd, rs->cs_inactive, rs->ready ? 1 : 0); return 0; diff --git a/drivers/spi/spidev-rkmst.c b/drivers/spi/spidev-rkmst.c new file mode 100644 index 000000000000..a969adf5ec91 --- /dev/null +++ b/drivers/spi/spidev-rkmst.c @@ -0,0 +1,636 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define SPI_OBJ_MAX_XFER_SIZE 0x1040 +#define SPI_OBJ_APP_RAM_SIZE 0x10000 + +#define SPI_OBJ_CTRL_MSG_SIZE 0x8 +#define SPI_OBJ_CTRL_CMD_INIT 0x99 +#define SPI_OBJ_CTRL_CMD_READ 0x3A +#define SPI_OBJ_CTRL_CMD_WRITE 0x4B +#define SPI_OBJ_CTRL_CMD_DUPLEX 0x5C + +#define SPI_OBJ_DEFAULT_TIMEOUT_US 100000 + +struct spi_obj_ctrl { + u16 cmd; + u16 addr; + u32 data; +}; + +struct spidev_rkmst_data { + struct device *dev; + struct spi_device *spi; + char *ctrlbuf; + char *rxbuf; + char *txbuf; + struct gpio_desc *ready; + int ready_irqnum; + bool ready_status; + bool verbose; + struct miscdevice misc_dev; +}; + +static u32 bit_per_word = 8; + +static inline void spidev_mst_slave_ready_status(struct spidev_rkmst_data *spidev, bool status) +{ + spidev->ready_status = status; +} + +static irqreturn_t spidev_mst_slave_ready_interrupt(int irq, void *arg) +{ + struct spidev_rkmst_data *spidev = (struct spidev_rkmst_data *)arg; + + spidev_mst_slave_ready_status(spidev, true); + + return IRQ_HANDLED; +} + +static bool spidev_mst_check_slave_ready(struct spidev_rkmst_data *spidev) +{ + return spidev->ready_status; +} + +static int spidev_mst_wait_for_slave_ready(struct spidev_rkmst_data *spidev, + u32 timeout_us) +{ + bool ready; + int ret; + + ret = read_poll_timeout(spidev_mst_check_slave_ready, ready, + ready, 100, timeout_us + 100, false, spidev); + if (ret) { + dev_err(&spidev->spi->dev, "timeout and reset slave\n"); + + return -ETIMEDOUT; + } + + return true; +} + +static int spidev_mst_write(struct spidev_rkmst_data *spidev, const void *txbuf, size_t n) +{ + struct spi_device *spi = spidev->spi; + struct spi_transfer t = { + .tx_buf = txbuf, + .len = n, + .bits_per_word = bit_per_word, + }; + struct spi_message m; + int ret; + + spi_message_init(&m); + spi_message_add_tail(&t, &m); + + ret = spidev_mst_wait_for_slave_ready(spidev, SPI_OBJ_DEFAULT_TIMEOUT_US); + if (ret < 0) + return ret; + + spidev_mst_slave_ready_status(spidev, false); + ret = spi_sync(spi, &m); + + return ret; +} + +static int spidev_mst_write_bypass(struct spidev_rkmst_data *spidev, const void *txbuf, size_t n) +{ + struct spi_device *spi = spidev->spi; + struct spi_transfer t = { + .tx_buf = txbuf, + .len = n, + .bits_per_word = bit_per_word, + }; + struct spi_message m; + int ret; + + spi_message_init(&m); + spi_message_add_tail(&t, &m); + + ret = spi_sync(spi, &m); + + return ret; +} + +static int spidev_mst_read(struct spidev_rkmst_data *spidev, void *rxbuf, size_t n) +{ + struct spi_device *spi = spidev->spi; + struct spi_transfer t = { + .rx_buf = rxbuf, + .len = n, + .bits_per_word = bit_per_word, + }; + struct spi_message m; + int ret; + + spi_message_init(&m); + spi_message_add_tail(&t, &m); + + ret = spidev_mst_wait_for_slave_ready(spidev, SPI_OBJ_MAX_XFER_SIZE); + if (ret < 0) + return ret; + + spidev_mst_slave_ready_status(spidev, false); + ret = spi_sync(spi, &m); + + return ret; +} + +static int spidev_slv_write_and_read(struct spidev_rkmst_data *spidev, + const void *tx_buf, void *rx_buf, + size_t len) +{ + struct spi_device *spi = spidev->spi; + struct spi_transfer t = { + .tx_buf = tx_buf, + .rx_buf = rx_buf, + .len = len, + }; + struct spi_message m; + int ret; + + spi_message_init(&m); + spi_message_add_tail(&t, &m); + + ret = spidev_mst_wait_for_slave_ready(spidev, SPI_OBJ_MAX_XFER_SIZE); + if (ret < 0) + return ret; + + spidev_mst_slave_ready_status(spidev, false); + ret = spi_sync(spi, &m); + + return ret; +} + +static void spidev_rkmst_reset_slave(struct spidev_rkmst_data *spidev) +{ + struct spi_obj_ctrl *ctrl = (struct spi_obj_ctrl *)spidev->ctrlbuf; + + ctrl->cmd = SPI_OBJ_CTRL_CMD_INIT; + + spidev_mst_write_bypass(spidev, ctrl, SPI_OBJ_MAX_XFER_SIZE); + msleep(100); + spidev_mst_write_bypass(spidev, ctrl, SPI_OBJ_MAX_XFER_SIZE); +} + + +static int spidev_rkmst_ctrl(struct spidev_rkmst_data *spidev, u32 cmd, u16 addr, u32 data) +{ + struct spi_obj_ctrl *ctrl = (struct spi_obj_ctrl *)spidev->ctrlbuf; + struct spi_device *spi = spidev->spi; + int ret; + + if (spidev->verbose) + dev_err(&spi->dev, "ctrl cmd=%x addr=0x%x data=0x%x\n", cmd, addr, data); + + /* ctrl_xfer */ + ctrl->cmd = cmd; + ctrl->addr = addr; + ctrl->data = data; + ret = spidev_mst_write(spidev, ctrl, SPI_OBJ_CTRL_MSG_SIZE); + if (ret) { + dev_err(&spi->dev, "ctrl cmd=%x addr=0x%x data=0x%x, ret=%d\n", cmd, addr, data, ret); + return -EIO; + } + + return 0; +} + +static int spidev_rkmst_xfer(struct spidev_rkmst_data *spidev, void *tx, + void *rx, u16 addr, u32 len) +{ + struct spi_device *spi = spidev->spi; + int ret; + u32 cmd; + + if (tx && rx) + cmd = SPI_OBJ_CTRL_CMD_DUPLEX; + else if (rx) + cmd = SPI_OBJ_CTRL_CMD_READ; + else if (tx) + cmd = SPI_OBJ_CTRL_CMD_WRITE; + else + return -EINVAL; + + /* ctrl_xfer */ + ret = spidev_rkmst_ctrl(spidev, cmd, addr, len); + if (ret) { + spidev_rkmst_reset_slave(spidev); + return -EIO; + } + + if (spidev->verbose) + dev_err(&spi->dev, "xfer len=0x%x\n", len); + /* data_xfer */ + switch (cmd) { + case SPI_OBJ_CTRL_CMD_READ: + ret = spidev_mst_read(spidev, rx, len); + if (ret) + goto err_out; + break; + case SPI_OBJ_CTRL_CMD_WRITE: + ret = spidev_mst_write(spidev, tx, len); + if (ret) + goto err_out; + break; + case SPI_OBJ_CTRL_CMD_DUPLEX: + ret = spidev_slv_write_and_read(spidev, tx, rx, len); + if (ret) + goto err_out; + break; + default: + dev_err(&spi->dev, "%s unknown\n", __func__); + } + + return 0; +err_out: + dev_err(&spi->dev, "xfer cmd=%x addr=0x%x len=0x%x, ret=%d\n", + cmd, addr, len, ret); + + return ret; +} + +static ssize_t spidev_rkmst_misc_write(struct file *filp, const char __user *buf, + size_t n, loff_t *offset) +{ + struct spidev_rkmst_data *spidev; + struct spi_device *spi; + int argc = 0, i; + char tmp[64]; + char *argv[16]; + char *cmd, *data; + + if (n >= 64) + return -EINVAL; + + spidev = filp->private_data; + + if (!spidev) + return -ESHUTDOWN; + + spi = spidev->spi; + memset(tmp, 0, sizeof(tmp)); + if (copy_from_user(tmp, buf, n)) + return -EFAULT; + cmd = tmp; + data = tmp; + + while (data < (tmp + n)) { + data = strstr(data, " "); + if (!data) + break; + *data = 0; + argv[argc] = ++data; + argc++; + if (argc >= 16) + break; + } + + tmp[n - 1] = 0; + + if (!strcmp(cmd, "verbose")) { + int val; + + if (argc < 1) + return -EINVAL; + + if (kstrtoint(argv[0], 0, &val)) + return -EINVAL; + + if (val == 1) + spidev->verbose = true; + else + spidev->verbose = false; + } else if (!strcmp(cmd, "init")) { + spidev_rkmst_ctrl(spidev, SPI_OBJ_CTRL_CMD_INIT, 0x55AA, 0x1234567); + } else if (!strcmp(cmd, "read")) { + int addr, len; + + if (argc < 2) + return -EINVAL; + + if (kstrtoint(argv[0], 0, &addr)) + return -EINVAL; + if (kstrtoint(argv[1], 0, &len)) + return -EINVAL; + + if (!len) { + dev_err(&spi->dev, "param invalid,%s %s\n", argv[0], argv[1]); + return -EINVAL; + } + + if (addr + len > SPI_OBJ_APP_RAM_SIZE) { + dev_err(&spi->dev, "rxbuf print out of size\n"); + return -EINVAL; + } + + spidev_rkmst_xfer(spidev, NULL, spidev->rxbuf, addr, len); + + print_hex_dump(KERN_ERR, "m-r: ", + DUMP_PREFIX_OFFSET, + 16, + 1, + spidev->rxbuf, + len, + 1); + } else if (!strcmp(cmd, "write")) { + int addr, len; + + if (argc < 2) + return -EINVAL; + + if (kstrtoint(argv[0], 0, &addr)) + return -EINVAL; + if (kstrtoint(argv[1], 0, &len)) + return -EINVAL; + + if (!len) { + dev_err(&spi->dev, "param invalid,%s %s\n", argv[0], argv[1]); + return -EINVAL; + } + + if (addr + len > SPI_OBJ_APP_RAM_SIZE) { + dev_err(&spi->dev, "rxbuf print out of size\n"); + return -EINVAL; + } + + for (i = 0; i < len; i++) + spidev->txbuf[i] = i & 0xFF; + ((u32 *)spidev->txbuf)[0] = addr; + + spidev_rkmst_xfer(spidev, spidev->txbuf, NULL, addr, len); + } else if (!strcmp(cmd, "duplex")) { + int addr, len; + + if (argc < 2) + return -EINVAL; + + if (kstrtoint(argv[0], 0, &addr)) + return -EINVAL; + if (kstrtoint(argv[1], 0, &len)) + return -EINVAL; + + if (!len) { + dev_err(&spi->dev, "param invalid,%s %s\n", argv[0], argv[1]); + return -EINVAL; + } + + if (addr + len > SPI_OBJ_APP_RAM_SIZE) { + dev_err(&spi->dev, "rxbuf print out of size\n"); + return -EINVAL; + } + + for (i = 0; i < len; i++) + spidev->txbuf[i] = i & 0xFF; + ((u32 *)spidev->txbuf)[0] = addr; + + spidev_rkmst_xfer(spidev, spidev->txbuf, spidev->rxbuf, addr, len); + + print_hex_dump(KERN_ERR, "m-d: ", + DUMP_PREFIX_OFFSET, + 16, + 1, + spidev->rxbuf, + len, + 1); + } else if (!strcmp(cmd, "autotest")) { + int addr = 0, len, loops, i; + unsigned long long bytes = 0; + unsigned long us = 0; + ktime_t start_time; + ktime_t end_time; + ktime_t cost_time; + char *tempbuf; + + if (argc < 2) + return -EINVAL; + + if (kstrtoint(argv[0], 0, &len)) + return -EINVAL; + + if (kstrtoint(argv[1], 0, &loops)) + return -EINVAL; + + if (!len) { + dev_err(&spi->dev, "param invalid,%s %s\n", argv[0], argv[1]); + return -EINVAL; + } + + if (len > SPI_OBJ_APP_RAM_SIZE) { + dev_err(&spi->dev, "rxbuf print out of size\n"); + return -EINVAL; + } + + tempbuf = kzalloc(len, GFP_KERNEL); + if (!tempbuf) + return -ENOMEM; + + prandom_bytes(tempbuf, len); + spidev_rkmst_xfer(spidev, tempbuf, NULL, addr, len); + start_time = ktime_get(); + for (i = 0; i < loops; i++) { + prandom_bytes(spidev->txbuf, len); + spidev_rkmst_xfer(spidev, spidev->txbuf, spidev->rxbuf, addr, len); + if (memcmp(spidev->rxbuf, tempbuf, len)) { + dev_err(&spi->dev, "dulplex autotest failed, loops=%d\n", i); + print_hex_dump(KERN_ERR, "m-d-t: ", + DUMP_PREFIX_OFFSET, + 16, + 1, + spidev->txbuf, + len, + 1); + print_hex_dump(KERN_ERR, "m-d-r: ", + DUMP_PREFIX_OFFSET, + 16, + 1, + spidev->rxbuf, + len, + 1); + print_hex_dump(KERN_ERR, "m-d-c: ", + DUMP_PREFIX_OFFSET, + 16, + 1, + tempbuf, + len, + 1); + break; + } + memcpy(tempbuf, spidev->txbuf, len); + } + end_time = ktime_get(); + cost_time = ktime_sub(end_time, start_time); + us = ktime_to_us(cost_time); + + bytes = (u64)len * (u64)loops * 1000; + do_div(bytes, us); + if (i >= loops) + dev_err(&spi->dev, "dulplex test pass, cost=%ldus, speed=%lldKB/S, %ldus/loops\n", + us, bytes, us / loops); + + start_time = ktime_get(); + for (i = 0; i < loops; i++) { + prandom_bytes(spidev->txbuf, len); + spidev_rkmst_xfer(spidev, spidev->txbuf, NULL, addr, len); + spidev_rkmst_xfer(spidev, NULL, spidev->rxbuf, addr, len); + if (memcmp(spidev->rxbuf, spidev->txbuf, len)) { + dev_err(&spi->dev, "read/write autotest failed, loops=%d\n", i); + print_hex_dump(KERN_ERR, "m-d-t: ", + DUMP_PREFIX_OFFSET, + 16, + 1, + spidev->txbuf, + len, + 1); + print_hex_dump(KERN_ERR, "m-d-r: ", + DUMP_PREFIX_OFFSET, + 16, + 1, + spidev->rxbuf, + len, + 1); + break; + } + } + end_time = ktime_get(); + cost_time = ktime_sub(end_time, start_time); + us = ktime_to_us(cost_time); + + bytes = (u64)len * (u64)loops * 2 * 1000; /* multi 2 for both write and read */ + do_div(bytes, us); + if (i >= loops) + dev_err(&spi->dev, "read/write test pass, cost=%ldus, speed=%lldKB/S, %ldus/loops\n", + us, bytes, us / loops); + kfree(tempbuf); + } else { + dev_err(&spi->dev, "unknown command\n"); + } + + return n; +} + +static int spidev_rkmst_misc_open(struct inode *inode, struct file *filp) +{ + struct miscdevice *miscdev = filp->private_data; + struct spidev_rkmst_data *spidev; + + spidev = container_of(miscdev, struct spidev_rkmst_data, misc_dev); + filp->private_data = spidev; + + return 0; +} + +static const struct file_operations spidev_rkmst_misc_fops = { + .write = spidev_rkmst_misc_write, + .open = spidev_rkmst_misc_open, +}; + +static int spidev_rkmst_probe(struct spi_device *spi) +{ + struct spidev_rkmst_data *spidev = NULL; + int ret; + + if (!spi) + return -ENOMEM; + + spidev = devm_kzalloc(&spi->dev, sizeof(struct spidev_rkmst_data), GFP_KERNEL); + if (!spidev) + return -ENOMEM; + + spidev->ctrlbuf = devm_kzalloc(&spi->dev, SPI_OBJ_MAX_XFER_SIZE, GFP_KERNEL); + if (!spidev->ctrlbuf) + return -ENOMEM; + + spidev->rxbuf = devm_kzalloc(&spi->dev, SPI_OBJ_APP_RAM_SIZE, GFP_KERNEL | GFP_DMA); + if (!spidev->rxbuf) + return -ENOMEM; + + spidev->txbuf = devm_kzalloc(&spi->dev, SPI_OBJ_MAX_XFER_SIZE, GFP_KERNEL); + if (!spidev->txbuf) + return -ENOMEM; + + spidev->spi = spi; + spidev->dev = &spi->dev; + + spidev_mst_slave_ready_status(spidev, false); + spidev->ready = devm_gpiod_get_optional(&spi->dev, "ready", GPIOD_IN); + if (IS_ERR(spidev->ready)) + return dev_err_probe(&spi->dev, PTR_ERR(spidev->ready), + "invalid ready-gpios property in node\n"); + + spidev->ready_irqnum = gpiod_to_irq(spidev->ready); + ret = devm_request_irq(&spi->dev, spidev->ready_irqnum, spidev_mst_slave_ready_interrupt, + IRQF_TRIGGER_FALLING, "spidev-mst-ready-in", spidev); + if (ret < 0) { + dev_err(&spi->dev, "request ready irq failed\n"); + return ret; + } + dev_set_drvdata(&spi->dev, spidev); + + dev_err(&spi->dev, "mode=%d, max_speed_hz=%d\n", spi->mode, spi->max_speed_hz); + + spidev->misc_dev.minor = MISC_DYNAMIC_MINOR; + spidev->misc_dev.name = "spidev_rkmst_misc"; + spidev->misc_dev.fops = &spidev_rkmst_misc_fops; + spidev->misc_dev.parent = &spi->dev; + ret = misc_register(&spidev->misc_dev); + if (ret) { + dev_err(&spi->dev, "fail to register misc device\n"); + return ret; + } + + spidev_rkmst_reset_slave(spidev); + + return 0; +} + +static int spidev_rkmst_remove(struct spi_device *spi) +{ + struct spidev_rkmst_data *spidev = dev_get_drvdata(&spi->dev); + + misc_deregister(&spidev->misc_dev); + + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id spidev_rkmst_dt_match[] = { + { .compatible = "rockchip,spi-obj-master", }, + {}, +}; +MODULE_DEVICE_TABLE(of, spidev_rkmst_dt_match); + +#endif /* CONFIG_OF */ + +static struct spi_driver spidev_rkmst_driver = { + .driver = { + .name = "spidev_rkmst", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(spidev_rkmst_dt_match), + }, + .probe = spidev_rkmst_probe, + .remove = spidev_rkmst_remove, +}; +module_spi_driver(spidev_rkmst_driver); + +MODULE_AUTHOR("Jon Lin "); +MODULE_DESCRIPTION("ROCKCHIP SPI Object Master Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("spi:spidev_rkmst"); diff --git a/drivers/spi/spidev-rkslv.c b/drivers/spi/spidev-rkslv.c new file mode 100644 index 000000000000..0ff4415ff7e3 --- /dev/null +++ b/drivers/spi/spidev-rkslv.c @@ -0,0 +1,382 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SPI_OBJ_MAX_XFER_SIZE 0x1040 +#define SPI_OBJ_APP_RAM_SIZE 0x10000 + +#define SPI_OBJ_CTRL_MSG_SIZE 0x8 +#define SPI_OBJ_CTRL_CMD_INIT 0x99 +#define SPI_OBJ_CTRL_CMD_READ 0x3A +#define SPI_OBJ_CTRL_CMD_WRITE 0x4B +#define SPI_OBJ_CTRL_CMD_DUPLEX 0x5C + +struct spi_obj_ctrl { + u16 cmd; + u16 addr; + u32 data; +}; + +struct spidev_rkslv_data { + struct device *dev; + struct spi_device *spi; + char *ctrlbuf; + char *appmem; + char *tempbuf; + bool verbose; + struct task_struct *tsk; + bool tsk_run; + struct miscdevice misc_dev; +}; + +static u32 bit_per_word = 8; + +static int spidev_slv_write(struct spidev_rkslv_data *spidev, const void *txbuf, size_t n) +{ + int ret = -1; + struct spi_device *spi = spidev->spi; + struct spi_transfer t = { + .tx_buf = txbuf, + .len = n, + .bits_per_word = bit_per_word, + }; + struct spi_message m; + + spi_message_init(&m); + spi_message_add_tail(&t, &m); + ret = spi_sync(spi, &m); + + return ret; +} + +static int spidev_slv_read(struct spidev_rkslv_data *spidev, void *rxbuf, size_t n) +{ + int ret = -1; + struct spi_device *spi = spidev->spi; + struct spi_transfer t = { + .rx_buf = rxbuf, + .len = n, + .bits_per_word = bit_per_word, + }; + struct spi_message m; + + spi_message_init(&m); + spi_message_add_tail(&t, &m); + ret = spi_sync(spi, &m); + + return ret; +} + +static int spidev_slv_write_and_read(struct spidev_rkslv_data *spidev, const void *tx_buf, + void *rx_buf, size_t len) +{ + struct spi_device *spi = spidev->spi; + struct spi_transfer t = { + .tx_buf = tx_buf, + .rx_buf = rx_buf, + .len = len, + }; + struct spi_message m; + + spi_message_init(&m); + spi_message_add_tail(&t, &m); + return spi_sync(spi, &m); +} + +static ssize_t spidev_rkslv_misc_write(struct file *filp, const char __user *buf, + size_t n, loff_t *offset) +{ + struct spidev_rkslv_data *spidev; + struct spi_device *spi; + int argc = 0; + char tmp[64]; + char *argv[16]; + char *cmd, *data; + + if (n >= 64) + return -EINVAL; + + spidev = filp->private_data; + + if (!spidev) + return -ESHUTDOWN; + + spi = spidev->spi; + memset(tmp, 0, sizeof(tmp)); + if (copy_from_user(tmp, buf, n)) + return -EFAULT; + cmd = tmp; + data = tmp; + + while (data < (tmp + n)) { + data = strstr(data, " "); + if (!data) + break; + *data = 0; + argv[argc] = ++data; + argc++; + if (argc >= 16) + break; + } + + tmp[n - 1] = 0; + + if (!strcmp(cmd, "verbose")) { + int val; + + if (argc < 1) + return -EINVAL; + + if (kstrtoint(argv[0], 0, &val)) + return -EINVAL; + + if (val == 1) + spidev->verbose = true; + else + spidev->verbose = false; + } else if (!strcmp(cmd, "appmem")) { + int addr, len; + + if (argc < 2) + return -EINVAL; + + if (kstrtoint(argv[0], 0, &addr)) + return -EINVAL; + if (kstrtoint(argv[1], 0, &len)) + return -EINVAL; + + if (!len) { + dev_err(&spi->dev, "param invalid,%s %s\n", argv[0], argv[1]); + return -EINVAL; + } + + if (addr + len > SPI_OBJ_APP_RAM_SIZE) { + dev_err(&spi->dev, "appmem print out of size\n"); + return -EINVAL; + } + + print_hex_dump(KERN_ERR, "APPMEM: ", + DUMP_PREFIX_OFFSET, + 16, + 1, + spidev->appmem + addr, + len, + 1); + } else { + dev_err(&spi->dev, "unknown command\n"); + } + + return n; +} + +static int spidev_rkslv_misc_open(struct inode *inode, struct file *filp) +{ + struct miscdevice *miscdev = filp->private_data; + struct spidev_rkslv_data *spidev; + + spidev = container_of(miscdev, struct spidev_rkslv_data, misc_dev); + filp->private_data = spidev; + + return 0; +} + +static const struct file_operations spidev_rkslv_misc_fops = { + .write = spidev_rkslv_misc_write, + .open = spidev_rkslv_misc_open, +}; + +static int spidev_rkslv_xfer(struct spidev_rkslv_data *spidev) +{ + char *ctrlbuf = spidev->ctrlbuf, *appmem = spidev->appmem, *tempbuf = spidev->tempbuf; + struct spi_obj_ctrl *ctrl; + struct spi_device *spi = spidev->spi; + u32 len; + int ret; + + memset(spidev->ctrlbuf, 0, SPI_OBJ_CTRL_MSG_SIZE); + ret = spidev_slv_read(spidev, spidev->ctrlbuf, SPI_OBJ_CTRL_MSG_SIZE); + if (ret) { + dev_err(&spi->dev, "%s ctrl\n", __func__); + return -EIO; + } + + ctrl = (struct spi_obj_ctrl *)ctrlbuf; + if (spidev->verbose) + dev_err(&spi->dev, "ctrl cmd=%x addr=0x%x data=0x%x\n", + ctrl->cmd, ctrl->addr, ctrl->data); + + switch (ctrl->cmd) { + case SPI_OBJ_CTRL_CMD_INIT: + return 0; + case SPI_OBJ_CTRL_CMD_READ: + len = ctrl->data; + ret = spidev_slv_write(spidev, appmem + ctrl->addr, len); + if (ret) { + dev_err(&spi->dev, "%s cmd=%x addr=0x%x data=0x%x\n", + __func__, ctrl->cmd, ctrl->addr, ctrl->data); + return -EIO; + } + break; + case SPI_OBJ_CTRL_CMD_WRITE: + len = ctrl->data; + ret = spidev_slv_read(spidev, appmem + ctrl->addr, len); + if (ret) { + dev_err(&spi->dev, "%s cmd=%x addr=0x%x data=0x%x\n", + __func__, ctrl->cmd, ctrl->addr, ctrl->data); + return -EIO; + } + if (spidev->verbose) { + print_hex_dump(KERN_ERR, "s-r: ", + DUMP_PREFIX_OFFSET, + 16, + 1, + appmem + ctrl->addr, + len, + 1); + } + break; + case SPI_OBJ_CTRL_CMD_DUPLEX: + len = ctrl->data; + ret = spidev_slv_write_and_read(spidev, appmem + ctrl->addr, tempbuf, len); + if (ret) { + dev_err(&spi->dev, "%s cmd=%x addr=0x%x data=0x%x\n", + __func__, ctrl->cmd, ctrl->addr, ctrl->data); + return -EIO; + } + if (spidev->verbose) { + print_hex_dump(KERN_ERR, "s-d-t: ", + DUMP_PREFIX_OFFSET, + 16, + 1, + appmem + ctrl->addr, + len, + 1); + print_hex_dump(KERN_ERR, "s-d-r: ", + DUMP_PREFIX_OFFSET, + 16, + 1, + tempbuf, + len, + 1); + } + memcpy(appmem + ctrl->addr, tempbuf, len); + break; + default: + if (spidev->verbose) + dev_err(&spi->dev, "%s unknown\n", __func__); + return 0; + } + + if (spidev->verbose) + dev_err(&spi->dev, "xfer len=0x%x\n", ctrl->data); + + return 0; +} + +static int spidev_rkslv_ctrl_receiver_thread(void *p) +{ + struct spidev_rkslv_data *spidev = (struct spidev_rkslv_data *)p; + + while (spidev->tsk_run) + spidev_rkslv_xfer(spidev); + + return 0; +} + +static int spidev_rkslv_probe(struct spi_device *spi) +{ + struct spidev_rkslv_data *spidev = NULL; + int ret; + + if (!spi) + return -ENOMEM; + + spidev = devm_kzalloc(&spi->dev, sizeof(struct spidev_rkslv_data), GFP_KERNEL); + if (!spidev) + return -ENOMEM; + + spidev->ctrlbuf = devm_kzalloc(&spi->dev, SPI_OBJ_MAX_XFER_SIZE, GFP_KERNEL); + if (!spidev->ctrlbuf) + return -ENOMEM; + + spidev->appmem = devm_kzalloc(&spi->dev, SPI_OBJ_APP_RAM_SIZE, GFP_KERNEL | GFP_DMA); + if (!spidev->appmem) + return -ENOMEM; + + spidev->tempbuf = devm_kzalloc(&spi->dev, SPI_OBJ_MAX_XFER_SIZE, GFP_KERNEL); + if (!spidev->tempbuf) + return -ENOMEM; + + spidev->spi = spi; + spidev->dev = &spi->dev; + dev_set_drvdata(&spi->dev, spidev); + + dev_err(&spi->dev, "mode=%d, max_speed_hz=%d\n", spi->mode, spi->max_speed_hz); + + spidev->misc_dev.minor = MISC_DYNAMIC_MINOR; + spidev->misc_dev.name = "spidev_rkslv_misc"; + spidev->misc_dev.fops = &spidev_rkslv_misc_fops; + spidev->misc_dev.parent = &spi->dev; + ret = misc_register(&spidev->misc_dev); + if (ret) { + dev_err(&spi->dev, "fail to register misc device\n"); + return ret; + } + + spidev->tsk_run = true; + spidev->tsk = kthread_run(spidev_rkslv_ctrl_receiver_thread, spidev, "spidev-rkslv"); + if (IS_ERR(spidev->tsk)) { + dev_err(&spi->dev, "start spidev-rkslv thread failed\n"); + return PTR_ERR(spidev->tsk); + } + + return 0; +} + +static int spidev_rkslv_remove(struct spi_device *spi) +{ + struct spidev_rkslv_data *spidev = dev_get_drvdata(&spi->dev); + + spidev->tsk_run = false; + spi_slave_abort(spi); + kthread_stop(spidev->tsk); + misc_deregister(&spidev->misc_dev); + + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id spidev_rkslv_dt_match[] = { + { .compatible = "rockchip,spi-obj-slave", }, + {}, +}; +MODULE_DEVICE_TABLE(of, spidev_rkslv_dt_match); + +#endif /* CONFIG_OF */ + +static struct spi_driver spidev_rkmst_driver = { + .driver = { + .name = "spidev_rkslv", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(spidev_rkslv_dt_match), + }, + .probe = spidev_rkslv_probe, + .remove = spidev_rkslv_remove, +}; +module_spi_driver(spidev_rkmst_driver); + +MODULE_AUTHOR("Jon Lin "); +MODULE_DESCRIPTION("ROCKCHIP SPI Object Slave Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("spi:spidev_rkslv"); diff --git a/drivers/video/rockchip/mpp/mpp_vepu2.c b/drivers/video/rockchip/mpp/mpp_vepu2.c index 522cebcafe01..395a5b69333f 100644 --- a/drivers/video/rockchip/mpp/mpp_vepu2.c +++ b/drivers/video/rockchip/mpp/mpp_vepu2.c @@ -314,43 +314,40 @@ fail: static void *vepu_prepare(struct mpp_dev *mpp, struct mpp_task *mpp_task) { - struct mpp_taskqueue *queue = mpp->queue; struct vepu_dev *enc = to_vepu_dev(mpp); struct vepu_ccu *ccu = enc->ccu; unsigned long core_idle; unsigned long flags; - u32 core_id_max; s32 core_id; u32 i; spin_lock_irqsave(&ccu->lock, flags); - core_idle = queue->core_idle; - core_id_max = queue->core_id_max; + core_idle = ccu->core_idle; - for (i = 0; i <= core_id_max; i++) { - struct mpp_dev *mpp = queue->cores[i]; + for (i = 0; i < ccu->core_num; i++) { + struct mpp_dev *mpp = ccu->cores[i]; if (mpp && mpp->disable) - clear_bit(i, &core_idle); + clear_bit(mpp->core_id, &core_idle); } - core_id = find_first_bit(&ccu->core_idle, ccu->core_num); - core_id = array_index_nospec(core_id, MPP_MAX_CORE_NUM); - if (core_id >= core_id_max + 1 || !queue->cores[core_id]) { + core_id = find_first_bit(&core_idle, ccu->core_num); + if (core_id >= ARRAY_SIZE(ccu->cores)) { mpp_task = NULL; mpp_dbg_core("core %d all busy %lx\n", core_id, ccu->core_idle); - } else { - unsigned long core_idle = ccu->core_idle; - - clear_bit(core_id, &ccu->core_idle); - mpp_task->mpp = ccu->cores[core_id]; - mpp_task->core_id = core_id; - - mpp_dbg_core("core cnt %d core %d set idle %lx -> %lx\n", - ccu->core_num, core_id, core_idle, ccu->core_idle); + goto done; } + core_id = array_index_nospec(core_id, MPP_MAX_CORE_NUM); + clear_bit(core_id, &ccu->core_idle); + mpp_task->mpp = ccu->cores[core_id]; + mpp_task->core_id = core_id; + + mpp_dbg_core("core cnt %d core %d set idle %lx -> %lx\n", + ccu->core_num, core_id, core_idle, ccu->core_idle); + +done: spin_unlock_irqrestore(&ccu->lock, flags); return mpp_task; diff --git a/drivers/video/rockchip/rga3/include/rga.h b/drivers/video/rockchip/rga3/include/rga.h index f6be6eafb718..21aa72d373e7 100644 --- a/drivers/video/rockchip/rga3/include/rga.h +++ b/drivers/video/rockchip/rga3/include/rga.h @@ -203,6 +203,55 @@ enum rga_surf_format { RGA_FORMAT_UNKNOWN = 0x100, }; +enum rga_alpha_mode { + RGA_ALPHA_STRAIGHT = 0, + RGA_ALPHA_INVERSE = 1, +}; + +enum rga_global_blend_mode { + RGA_ALPHA_GLOBAL = 0, + RGA_ALPHA_PER_PIXEL = 1, + RGA_ALPHA_PER_PIXEL_GLOBAL = 2, +}; + +enum rga_alpha_cal_mode { + RGA_ALPHA_SATURATION = 0, + RGA_ALPHA_NO_SATURATION = 1, +}; + +enum rga_factor_mode { + RGA_ALPHA_ZERO = 0, + RGA_ALPHA_ONE = 1, + /* + * When used as a factor for the SRC channel, it indicates + * the use of the DST channel's alpha value, and vice versa. + */ + RGA_ALPHA_OPPOSITE = 2, + RGA_ALPHA_OPPOSITE_INVERSE = 3, + RGA_ALPHA_OWN = 4, +}; + +enum rga_color_mode { + RGA_ALPHA_PRE_MULTIPLIED = 0, + RGA_ALPHA_NO_PRE_MULTIPLIED = 1, +}; + +enum rga_alpha_blend_mode { + RGA_ALPHA_NONE = 0, + RGA_ALPHA_BLEND_SRC, + RGA_ALPHA_BLEND_DST, + RGA_ALPHA_BLEND_SRC_OVER, + RGA_ALPHA_BLEND_DST_OVER, + RGA_ALPHA_BLEND_SRC_IN, + RGA_ALPHA_BLEND_DST_IN, + RGA_ALPHA_BLEND_SRC_OUT, + RGA_ALPHA_BLEND_DST_OUT, + RGA_ALPHA_BLEND_SRC_ATOP, + RGA_ALPHA_BLEND_DST_ATOP, + RGA_ALPHA_BLEND_XOR, + RGA_ALPHA_BLEND_CLEAR, +}; + #define RGA_SCHED_PRIORITY_DEFAULT 0 #define RGA_SCHED_PRIORITY_MAX 6 @@ -628,6 +677,19 @@ struct rga_req { uint8_t reservr[59]; }; +struct rga_alpha_config { + bool enable; + bool fg_pre_multiplied; + bool bg_pre_multiplied; + bool fg_pixel_alpha_en; + bool bg_pixel_alpha_en; + bool fg_global_alpha_en; + bool bg_global_alpha_en; + uint16_t fg_global_alpha_value; + uint16_t bg_global_alpha_value; + enum rga_alpha_blend_mode mode; +}; + struct rga2_req { /* (enum) process mode sel */ u8 render_mode; @@ -672,29 +734,7 @@ struct rga2_req { /* ([7] = 1 gradient fill mode sel) */ u16 alpha_rop_flag; - /* [0] SrcAlphaMode0 */ - /* [2:1] SrcGlobalAlphaMode0 */ - /* [3] SrcAlphaSelectMode0 */ - /* [6:4] SrcFactorMode0 */ - /* [7] SrcColorMode */ - - /* [8] DstAlphaMode0 */ - /* [10:9] DstGlobalAlphaMode0 */ - /* [11] DstAlphaSelectMode0 */ - /* [14:12] DstFactorMode0 */ - /* [15] DstColorMode0 */ - u16 alpha_mode_0; - - /* [0] SrcAlphaMode1 */ - /* [2:1] SrcGlobalAlphaMode1 */ - /* [3] SrcAlphaSelectMode1 */ - /* [6:4] SrcFactorMode1 */ - - /* [8] DstAlphaMode1 */ - /* [10:9] DstGlobalAlphaMode1 */ - /* [11] DstAlphaSelectMode1 */ - /* [14:12] DstFactorMode1 */ - u16 alpha_mode_1; + struct rga_alpha_config alpha_config; /* 0 1 2 3 */ u8 scale_bicu_mode; @@ -782,8 +822,10 @@ struct rga3_req { u16 alpha_rop_flag; - u16 alpha_mode_0; - u16 alpha_mode_1; + struct rga_alpha_config alpha_config; + + /* for abb mode presever alpha. */ + bool abb_alpha_pass; u8 scale_bicu_mode; diff --git a/drivers/video/rockchip/rga3/include/rga2_reg_info.h b/drivers/video/rockchip/rga3/include/rga2_reg_info.h index 6a5601b114cd..add2f41bda78 100644 --- a/drivers/video/rockchip/rga3/include/rga2_reg_info.h +++ b/drivers/video/rockchip/rga3/include/rga2_reg_info.h @@ -434,6 +434,43 @@ #define RGA2_VSP_BICUBIC_LIMIT 1996 +union rga2_color_ctrl { + uint32_t value; + struct { + uint32_t dst_color_mode:1; + uint32_t src_color_mode:1; + + uint32_t dst_factor_mode:3; + uint32_t src_factor_mode:3; + + uint32_t dst_alpha_cal_mode:1; + uint32_t src_alpha_cal_mode:1; + + uint32_t dst_blend_mode:2; + uint32_t src_blend_mode:2; + + uint32_t dst_alpha_mode:1; + uint32_t src_alpha_mode:1; + } bits; +}; + +union rga2_alpha_ctrl { + uint32_t value; + struct { + uint32_t dst_factor_mode:3; + uint32_t src_factor_mode:3; + + uint32_t dst_alpha_cal_mode:1; + uint32_t src_alpha_cal_mode:1; + + uint32_t dst_blend_mode:2; + uint32_t src_blend_mode:2; + + uint32_t dst_alpha_mode:1; + uint32_t src_alpha_mode:1; + } bits; +}; + extern const struct rga_backend_ops rga2_ops; #endif diff --git a/drivers/video/rockchip/rga3/include/rga3_reg_info.h b/drivers/video/rockchip/rga3/include/rga3_reg_info.h index 88d05a5beccb..4db80cfb09ee 100644 --- a/drivers/video/rockchip/rga3/include/rga3_reg_info.h +++ b/drivers/video/rockchip/rga3/include/rga3_reg_info.h @@ -489,6 +489,32 @@ #define RGA3_ROT_BIT_X_MIRROR BIT(1) #define RGA3_ROT_BIT_Y_MIRROR BIT(2) +union rga3_color_ctrl { + uint32_t value; + struct { + uint32_t color_mode:1; + uint32_t alpha_mode:1; + uint32_t blend_mode:2; + uint32_t alpha_cal_mode:1; + uint32_t factor_mode:3; + + uint32_t reserved:8; + + uint32_t global_alpha:8; + } bits; +}; + +union rga3_alpha_ctrl { + uint32_t value; + struct { + uint32_t reserved:1; + uint32_t alpha_mode:1; + uint32_t blend_mode:2; + uint32_t alpha_cal_mode:1; + uint32_t factor_mode:3; + } bits; +}; + extern const struct rga_backend_ops rga3_ops; #endif diff --git a/drivers/video/rockchip/rga3/include/rga_common.h b/drivers/video/rockchip/rga3/include/rga_common.h index 0b2ad9ec95db..67aad7b48202 100644 --- a/drivers/video/rockchip/rga3/include/rga_common.h +++ b/drivers/video/rockchip/rga3/include/rga_common.h @@ -34,9 +34,7 @@ int rga_get_pixel_stride_from_format(uint32_t format); const char *rga_get_format_name(uint32_t format); const char *rga_get_render_mode_str(uint8_t mode); const char *rga_get_rotate_mode_str(uint8_t mode); -const char *rga_get_blend_mode_str(uint16_t alpha_rop_flag, - uint16_t alpha_mode_0, - uint16_t alpha_mode_1); +const char *rga_get_blend_mode_str(enum rga_alpha_blend_mode mode); const char *rga_get_memory_type_str(uint8_t type); const char *rga_get_mmu_type_str(enum rga_mmu mmu_type); diff --git a/drivers/video/rockchip/rga3/rga2_reg_info.c b/drivers/video/rockchip/rga3/rga2_reg_info.c index a624778bf6c3..c987919cfff3 100644 --- a/drivers/video/rockchip/rga3/rga2_reg_info.c +++ b/drivers/video/rockchip/rga3/rga2_reg_info.c @@ -1277,104 +1277,253 @@ static void RGA2_set_reg_alpha_info(u8 *base, struct rga2_req *msg) u32 *bRGA_ALPHA_CTRL0; u32 *bRGA_ALPHA_CTRL1; u32 *bRGA_FADING_CTRL; - u32 reg0 = 0; - u32 reg1 = 0; + u32 reg = 0; + union rga2_color_ctrl color_ctrl; + union rga2_alpha_ctrl alpha_ctrl; + struct rga_alpha_config *config; bRGA_ALPHA_CTRL0 = (u32 *) (base + RGA2_ALPHA_CTRL0_OFFSET); bRGA_ALPHA_CTRL1 = (u32 *) (base + RGA2_ALPHA_CTRL1_OFFSET); bRGA_FADING_CTRL = (u32 *) (base + RGA2_FADING_CTRL_OFFSET); - reg0 = - ((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0)) | + color_ctrl.value = 0; + alpha_ctrl.value = 0; + config = &msg->alpha_config; + + color_ctrl.bits.src_color_mode = + config->fg_pre_multiplied ? RGA_ALPHA_PRE_MULTIPLIED : RGA_ALPHA_NO_PRE_MULTIPLIED; + color_ctrl.bits.dst_color_mode = + config->bg_pre_multiplied ? RGA_ALPHA_PRE_MULTIPLIED : RGA_ALPHA_NO_PRE_MULTIPLIED; + + if (config->fg_pixel_alpha_en) + color_ctrl.bits.src_blend_mode = + config->fg_global_alpha_en ? RGA_ALPHA_PER_PIXEL_GLOBAL : + RGA_ALPHA_PER_PIXEL; + else + color_ctrl.bits.src_blend_mode = RGA_ALPHA_GLOBAL; + + if (config->bg_pixel_alpha_en) + color_ctrl.bits.dst_blend_mode = + config->bg_global_alpha_en ? RGA_ALPHA_PER_PIXEL_GLOBAL : + RGA_ALPHA_PER_PIXEL; + else + color_ctrl.bits.dst_blend_mode = RGA_ALPHA_GLOBAL; + + /* + * Since the hardware uses 256 as 1, the original alpha value needs to + * be + (alpha >> 7). + */ + color_ctrl.bits.src_alpha_cal_mode = RGA_ALPHA_SATURATION; + color_ctrl.bits.dst_alpha_cal_mode = RGA_ALPHA_SATURATION; + + /* porter duff alpha enable */ + switch (config->mode) { + case RGA_ALPHA_BLEND_SRC: + /* + * SRC mode: + * Sf = 1, Df = 0； + * [Rc,Ra] = [Sc,Sa]； + */ + color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.src_factor_mode = RGA_ALPHA_ONE; + + color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ZERO; + + break; + + case RGA_ALPHA_BLEND_DST: + /* + * SRC mode: + * Sf = 0, Df = 1； + * [Rc,Ra] = [Dc,Da]； + */ + color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.src_factor_mode = RGA_ALPHA_ZERO; + + color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ONE; + + break; + + case RGA_ALPHA_BLEND_SRC_OVER: + /* + * SRC-OVER mode: + * Sf = 1, Df = (1 - Sa) + * [Rc,Ra] = [ Sc + (1 - Sa) * Dc, Sa + (1 - Sa) * Da ] + */ + color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.src_factor_mode = RGA_ALPHA_ONE; + + color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE; + + break; + + case RGA_ALPHA_BLEND_DST_OVER: + /* + * DST-OVER mode: + * Sf = (1 - Da) , Df = 1 + * [Rc,Ra] = [ Sc * (1 - Da) + Dc, Sa * (1 - Da) + Da ] + */ + color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE; + + color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ONE; + + break; + + case RGA_ALPHA_BLEND_SRC_IN: + /* + * SRC-IN mode: + * Sf = Da , Df = 0 + * [Rc,Ra] = [ Sc * Da, Sa * Da ] + */ + color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE; + + color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ZERO; + + break; + + case RGA_ALPHA_BLEND_DST_IN: + /* + * DST-IN mode: + * Sf = 0 , Df = Sa + * [Rc,Ra] = [ Dc * Sa, Da * Sa ] + */ + color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.src_factor_mode = RGA_ALPHA_ZERO; + + color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE; + + break; + + case RGA_ALPHA_BLEND_SRC_OUT: + /* + * SRC-OUT mode: + * Sf = (1 - Da) , Df = 0 + * [Rc,Ra] = [ Sc * (1 - Da), Sa * (1 - Da) ] + */ + color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE; + + color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ZERO; + + break; + + case RGA_ALPHA_BLEND_DST_OUT: + /* + * DST-OUT mode: + * Sf = 0 , Df = (1 - Sa) + * [Rc,Ra] = [ Dc * (1 - Sa), Da * (1 - Sa) ] + */ + color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.src_factor_mode = RGA_ALPHA_ZERO; + + color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE; + + break; + + case RGA_ALPHA_BLEND_SRC_ATOP: + /* + * SRC-ATOP mode: + * Sf = Da , Df = (1 - Sa) + * [Rc,Ra] = [ Sc * Da + Dc * (1 - Sa), Sa * Da + Da * (1 - Sa) ] + */ + color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE; + + color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE; + + break; + + case RGA_ALPHA_BLEND_DST_ATOP: + /* + * DST-ATOP mode: + * Sf = (1 - Da) , Df = Sa + * [Rc,Ra] = [ Sc * (1 - Da) + Dc * Sa, Sa * (1 - Da) + Da * Sa ] + */ + color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE; + + color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE; + + break; + + case RGA_ALPHA_BLEND_XOR: + /* + * DST-XOR mode: + * Sf = (1 - Da) , Df = (1 - Sa) + * [Rc,Ra] = [ Sc * (1 - Da) + Dc * (1 - Sa), Sa * (1 - Da) + Da * (1 - Sa) ] + */ + color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE; + + color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE; + + break; + + case RGA_ALPHA_BLEND_CLEAR: + /* + * DST-CLEAR mode: + * Sf = 0 , Df = 0 + * [Rc,Ra] = [ 0, 0 ] + */ + color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.src_factor_mode = RGA_ALPHA_ZERO; + + color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT; + color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ZERO; + + break; + + default: + break; + } + + alpha_ctrl.bits.src_blend_mode = color_ctrl.bits.src_blend_mode; + alpha_ctrl.bits.dst_blend_mode = color_ctrl.bits.dst_blend_mode; + + alpha_ctrl.bits.src_alpha_cal_mode = color_ctrl.bits.src_alpha_cal_mode; + alpha_ctrl.bits.dst_alpha_cal_mode = color_ctrl.bits.dst_alpha_cal_mode; + + alpha_ctrl.bits.src_alpha_mode = color_ctrl.bits.src_alpha_mode; + alpha_ctrl.bits.src_factor_mode = color_ctrl.bits.src_factor_mode; + + alpha_ctrl.bits.dst_alpha_mode = color_ctrl.bits.dst_alpha_mode; + alpha_ctrl.bits.dst_factor_mode = color_ctrl.bits.dst_factor_mode; + + reg = + ((reg & (~m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0)) | (s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0(msg->alpha_rop_flag))); - reg0 = - ((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL)) | + reg = + ((reg & (~m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL)) | (s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL (msg->alpha_rop_flag >> 1))); - reg0 = - ((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_ROP_MODE)) | + reg = + ((reg & (~m_RGA2_ALPHA_CTRL0_SW_ROP_MODE)) | (s_RGA2_ALPHA_CTRL0_SW_ROP_MODE(msg->rop_mode))); - reg0 = - ((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA)) | + reg = + ((reg & (~m_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA)) | (s_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA - (msg->src_a_global_val))); - reg0 = - ((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA)) | + ((uint8_t)config->fg_global_alpha_value))); + reg = + ((reg & (~m_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA)) | (s_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA - (msg->dst_a_global_val))); + ((uint8_t)config->bg_global_alpha_value))); - reg1 = - ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0)) | - (s_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0 - (msg->alpha_mode_0 >> 15))); - reg1 = - ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0)) | - (s_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0 - (msg->alpha_mode_0 >> 7))); - reg1 = - ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0)) | - (s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0 - (msg->alpha_mode_0 >> 12))); - reg1 = - ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0)) | - (s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0 - (msg->alpha_mode_0 >> 4))); - reg1 = - ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0)) | - (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0 - (msg->alpha_mode_0 >> 11))); - reg1 = - ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0)) | - (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0 - (msg->alpha_mode_0 >> 3))); - reg1 = - ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0)) | - (s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0 - (msg->alpha_mode_0 >> 9))); - reg1 = - ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0)) | - (s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0 - (msg->alpha_mode_0 >> 1))); - reg1 = - ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0)) | - (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0 - (msg->alpha_mode_0 >> 8))); - reg1 = - ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0)) | - (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0 - (msg->alpha_mode_0 >> 0))); + *bRGA_ALPHA_CTRL0 = reg; + *bRGA_ALPHA_CTRL1 = color_ctrl.value | (alpha_ctrl.value << 16); - reg1 = - ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1)) | - (s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1 - (msg->alpha_mode_1 >> 12))); - reg1 = - ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1)) | - (s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1 - (msg->alpha_mode_1 >> 4))); - reg1 = - ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1)) | - (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1 - (msg->alpha_mode_1 >> 11))); - reg1 = - ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1)) | - (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1 - (msg->alpha_mode_1 >> 3))); - reg1 = - ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1)) | - (s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1(msg->alpha_mode_1 >> 9))); - reg1 = - ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1)) | - (s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1(msg->alpha_mode_1 >> 1))); - reg1 = - ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1)) | - (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1(msg->alpha_mode_1 >> 8))); - reg1 = - ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1)) | - (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1(msg->alpha_mode_1 >> 0))); - - *bRGA_ALPHA_CTRL0 = reg0; - *bRGA_ALPHA_CTRL1 = reg1; if ((msg->alpha_rop_flag >> 2) & 1) { *bRGA_FADING_CTRL = (1 << 24) | (msg->fading_b_value << 16) | @@ -1776,8 +1925,6 @@ static int rga2_gen_reg_info(u8 *base, struct rga2_req *msg) static void rga_cmd_to_rga2_cmd(struct rga_scheduler_t *scheduler, struct rga_req *req_rga, struct rga2_req *req) { - u16 alpha_mode_0, alpha_mode_1; - if (req_rga->render_mode == 6) req->render_mode = UPDATE_PALETTE_TABLE_MODE; else if (req_rga->render_mode == 7) @@ -1918,110 +2065,92 @@ static void rga_cmd_to_rga2_cmd(struct rga_scheduler_t *scheduler, if (((req_rga->alpha_rop_flag) & 1)) { if ((req_rga->alpha_rop_flag >> 3) & 1) { + req->alpha_config.enable = true; + + if ((req_rga->alpha_rop_flag >> 9) & 1) { + req->alpha_config.fg_pre_multiplied = false; + req->alpha_config.bg_pre_multiplied = false; + } else if (req->osd_info.enable) { + req->alpha_config.fg_pre_multiplied = true; + /* set dst(osd_block) real color mode */ + req->alpha_config.bg_pre_multiplied = false; + } else { + req->alpha_config.fg_pre_multiplied = true; + req->alpha_config.bg_pre_multiplied = true; + } + + req->alpha_config.fg_pixel_alpha_en = rga_is_alpha_format(req->src.format); + if (req->bitblt_mode) + req->alpha_config.bg_pixel_alpha_en = + rga_is_alpha_format(req->src1.format); + else + req->alpha_config.bg_pixel_alpha_en = + rga_is_alpha_format(req->dst.format); + + req->alpha_config.fg_global_alpha_en = false; + req->alpha_config.bg_global_alpha_en = false; + + req->alpha_config.fg_global_alpha_value = req_rga->alpha_global_value; + req->alpha_config.bg_global_alpha_value = req_rga->alpha_global_value; + /* porter duff alpha enable */ switch (req_rga->PD_mode) { /* dst = 0 */ case 0: break; - /* dst = src */ case 1: - req->alpha_mode_0 = 0x0212; - req->alpha_mode_1 = 0x0212; + req->alpha_config.mode = RGA_ALPHA_BLEND_SRC; break; - /* dst = dst */ case 2: - req->alpha_mode_0 = 0x1202; - req->alpha_mode_1 = 0x1202; + req->alpha_config.mode = RGA_ALPHA_BLEND_DST; break; - /* dst = (256*sc + (256 - sa)*dc) >> 8 */ case 3: if ((req_rga->alpha_rop_mode & 3) == 0) { /* both use globalAlpha. */ - alpha_mode_0 = 0x3010; - alpha_mode_1 = 0x3010; + req->alpha_config.fg_global_alpha_en = true; + req->alpha_config.bg_global_alpha_en = true; } else if ((req_rga->alpha_rop_mode & 3) == 1) { /* Do not use globalAlpha. */ - alpha_mode_0 = 0x3212; - alpha_mode_1 = 0x3212; - } else if ((req_rga->alpha_rop_mode & 3) == 2) { - /* - * dst use globalAlpha, - * and dst has pixelAlpha. - */ - alpha_mode_0 = 0x3014; - alpha_mode_1 = 0x3014; + req->alpha_config.fg_global_alpha_en = false; + req->alpha_config.bg_global_alpha_en = false; } else { - /* - * dst use globalAlpha, and - * dst does not have pixelAlpha. - */ - alpha_mode_0 = 0x3012; - alpha_mode_1 = 0x3012; + /* dst use globalAlpha */ + req->alpha_config.fg_global_alpha_en = false; + req->alpha_config.bg_global_alpha_en = true; } - req->alpha_mode_0 = alpha_mode_0; - req->alpha_mode_1 = alpha_mode_1; + + req->alpha_config.mode = RGA_ALPHA_BLEND_SRC_OVER; break; - /* dst = (sc*(256-da) + 256*dc) >> 8 */ case 4: - /* Do not use globalAlpha. */ - req->alpha_mode_0 = 0x1232; - req->alpha_mode_1 = 0x1232; + req->alpha_config.mode = RGA_ALPHA_BLEND_DST_OVER; break; - /* dst = (da*sc) >> 8 */ case 5: + req->alpha_config.mode = RGA_ALPHA_BLEND_SRC_IN; break; - /* dst = (sa*dc) >> 8 */ case 6: + req->alpha_config.mode = RGA_ALPHA_BLEND_DST_IN; break; - /* dst = ((256-da)*sc) >> 8 */ case 7: + req->alpha_config.mode = RGA_ALPHA_BLEND_SRC_OUT; break; - /* dst = ((256-sa)*dc) >> 8 */ case 8: + req->alpha_config.mode = RGA_ALPHA_BLEND_DST_OUT; break; - /* dst = (da*sc + (256-sa)*dc) >> 8 */ case 9: - req->alpha_mode_0 = 0x3040; - req->alpha_mode_1 = 0x3040; + req->alpha_config.mode = RGA_ALPHA_BLEND_SRC_ATOP; break; - /* dst = ((256-da)*sc + (sa*dc)) >> 8 */ case 10: + req->alpha_config.mode = RGA_ALPHA_BLEND_DST_ATOP; break; - /* dst = ((256-da)*sc + (256-sa)*dc) >> 8 */ case 11: + req->alpha_config.mode = RGA_ALPHA_BLEND_XOR; break; case 12: - req->alpha_mode_0 = 0x0010; - req->alpha_mode_1 = 0x0820; + req->alpha_config.mode = RGA_ALPHA_BLEND_CLEAR; break; default: break; } - - if (req->osd_info.enable) { - /* set dst(osd_block) real color mode */ - if (req->alpha_mode_0 & (0x01 << 9)) - req->alpha_mode_0 |= (1 << 15); - } - - /* Real color mode */ - if ((req_rga->alpha_rop_flag >> 9) & 1) { - if (req->alpha_mode_0 & (0x01 << 1)) - req->alpha_mode_0 |= (1 << 7); - if (req->alpha_mode_0 & (0x01 << 9)) - req->alpha_mode_0 |= (1 << 15); - } - } else { - if ((req_rga->alpha_rop_mode & 3) == 0) { - req->alpha_mode_0 = 0x3040; - req->alpha_mode_1 = 0x3040; - } else if ((req_rga->alpha_rop_mode & 3) == 1) { - req->alpha_mode_0 = 0x3042; - req->alpha_mode_1 = 0x3242; - } else if ((req_rga->alpha_rop_mode & 3) == 2) { - req->alpha_mode_0 = 0x3044; - req->alpha_mode_1 = 0x3044; - } } } @@ -2094,9 +2223,9 @@ static void rga2_soft_reset(struct rga_scheduler_t *scheduler) } if (i == RGA_RESET_TIMEOUT) - pr_err("RAG2 soft reset timeout.\n"); + pr_err("RAG2 core[%d] soft reset timeout.\n", scheduler->core); else - pr_info("RGA2 soft reset complete.\n"); + pr_info("RGA2 core[%d] soft reset complete.\n", scheduler->core); } @@ -2216,11 +2345,14 @@ static void print_debug_info(struct rga2_req *req) pr_info("mmu: src=%.2x src1=%.2x dst=%.2x els=%.2x\n", req->mmu_info.src0_mmu_flag, req->mmu_info.src1_mmu_flag, req->mmu_info.dst_mmu_flag, req->mmu_info.els_mmu_flag); - pr_info("alpha: flag %x mode0=%x mode1=%x\n", req->alpha_rop_flag, - req->alpha_mode_0, req->alpha_mode_1); - pr_info("blend mode is %s\n", - rga_get_blend_mode_str(req->alpha_rop_flag, req->alpha_mode_0, - req->alpha_mode_1)); + pr_info("alpha: flag %x mode=%s\n", + req->alpha_rop_flag, rga_get_blend_mode_str(req->alpha_config.mode)); + pr_info("alpha: pre_multi=[%d,%d] pixl=[%d,%d] glb=[%d,%d]\n", + req->alpha_config.fg_pre_multiplied, req->alpha_config.bg_pre_multiplied, + req->alpha_config.fg_pixel_alpha_en, req->alpha_config.bg_pixel_alpha_en, + req->alpha_config.fg_global_alpha_en, req->alpha_config.bg_global_alpha_en); + pr_info("alpha: fg_global_alpha=%x bg_global_alpha=%x\n", + req->alpha_config.fg_global_alpha_value, req->alpha_config.bg_global_alpha_value); pr_info("yuv2rgb mode is %x\n", req->yuv2rgb_mode); } diff --git a/drivers/video/rockchip/rga3/rga3_reg_info.c b/drivers/video/rockchip/rga3/rga3_reg_info.c index d462f98850b2..b1d0f6b9ff69 100644 --- a/drivers/video/rockchip/rga3/rga3_reg_info.c +++ b/drivers/video/rockchip/rga3/rga3_reg_info.c @@ -1028,6 +1028,9 @@ static void RGA3_set_reg_overlap_info(u8 *base, struct rga3_req *msg) u32 *bRGA3_OVLP_OFF; u32 reg; + union rga3_color_ctrl top_color_ctrl, bottom_color_ctrl; + union rga3_alpha_ctrl top_alpha_ctrl, bottom_alpha_ctrl; + struct rga_alpha_config *config; bRGA_OVERLAP_TOP_CTRL = (u32 *) (base + RGA3_OVLP_TOP_CTRL_OFFSET); bRGA_OVERLAP_BOT_CTRL = (u32 *) (base + RGA3_OVLP_BOT_CTRL_OFFSET); @@ -1039,98 +1042,249 @@ static void RGA3_set_reg_overlap_info(u8 *base, struct rga3_req *msg) /* Alpha blend */ /*bot -> win0(dst), top -> win1(src). */ - reg = 0; - reg = - ((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_COLOR_M0)) | - (s_RGA3_OVLP_TOP_CTRL_SW_TOP_COLOR_M0 - (msg->alpha_mode_0 >> 7))); - reg = - ((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_M0)) | - (s_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_M0 - (msg->alpha_mode_0 >> 0))); - reg = - ((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_BLEND_M0)) | - (s_RGA3_OVLP_TOP_CTRL_SW_TOP_BLEND_M0 - (msg->alpha_mode_0 >> 1))); - reg = - ((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_CAL_M0)) | - (s_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_CAL_M0 - (msg->alpha_mode_0 >> 3))); - reg = - ((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_FACTOR_M0)) | - (s_RGA3_OVLP_TOP_CTRL_SW_TOP_FACTOR_M0 - (msg->alpha_mode_0 >> 4))); - reg = - ((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_GLOBAL_ALPHA)) | - (s_RGA3_OVLP_TOP_CTRL_SW_TOP_GLOBAL_ALPHA - (msg->win1_a_global_val))); - *bRGA_OVERLAP_TOP_CTRL = reg; + top_color_ctrl.value = 0; + bottom_color_ctrl.value = 0; + top_alpha_ctrl.value = 0; + bottom_alpha_ctrl.value = 0; + config = &msg->alpha_config; - reg = 0; - reg = - ((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_COLOR_M0)) | - (s_RGA3_OVLP_BOT_CTRL_SW_BOT_COLOR_M0 - (msg->alpha_mode_0 >> 15))); - reg = - ((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_M0)) | - (s_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_M0 - (msg->alpha_mode_0 >> 8))); - reg = - ((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_BLEND_M0)) | - (s_RGA3_OVLP_BOT_CTRL_SW_BOT_BLEND_M0 - (msg->alpha_mode_0 >> 9))); - reg = - ((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_CAL_M0)) | - (s_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_CAL_M0 - (msg->alpha_mode_0 >> 11))); - reg = - ((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_FACTOR_M0)) | - (s_RGA3_OVLP_BOT_CTRL_SW_BOT_FACTOR_M0 - (msg->alpha_mode_0 >> 12))); - reg = - ((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_GLOBAL_ALPHA)) | - (s_RGA3_OVLP_BOT_CTRL_SW_BOT_GLOBAL_ALPHA - (msg->win0_a_global_val))); - *bRGA_OVERLAP_BOT_CTRL = reg; + if (config->fg_pixel_alpha_en) + top_color_ctrl.bits.blend_mode = + config->fg_global_alpha_en ? RGA_ALPHA_PER_PIXEL_GLOBAL : + RGA_ALPHA_PER_PIXEL; + else + top_color_ctrl.bits.blend_mode = RGA_ALPHA_GLOBAL; - reg = 0; - reg = - ((reg & (~m_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_M1)) | - (s_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_M1 - (msg->alpha_mode_1 >> 0))); - reg = - ((reg & (~m_RGA3_OVLP_TOP_ALPHA_SW_TOP_BLEND_M1)) | - (s_RGA3_OVLP_TOP_ALPHA_SW_TOP_BLEND_M1 - (msg->alpha_mode_1 >> 1))); - reg = - ((reg & (~m_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_CAL_M1)) | - (s_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_CAL_M1 - (msg->alpha_mode_1 >> 3))); - reg = - ((reg & (~m_RGA3_OVLP_TOP_ALPHA_SW_TOP_FACTOR_M1)) | - (s_RGA3_OVLP_TOP_ALPHA_SW_TOP_FACTOR_M1 - (msg->alpha_mode_1 >> 4))); - *bRGA_OVERLAP_TOP_ALPHA = reg; + if (config->bg_pixel_alpha_en) + bottom_color_ctrl.bits.blend_mode = + config->bg_global_alpha_en ? RGA_ALPHA_PER_PIXEL_GLOBAL : + RGA_ALPHA_PER_PIXEL; + else + bottom_color_ctrl.bits.blend_mode = RGA_ALPHA_GLOBAL; - reg = 0; - reg = - ((reg & (~m_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_M1)) | - (s_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_M1 - (msg->alpha_mode_1 >> 8))); - reg = - ((reg & (~m_RGA3_OVLP_BOT_ALPHA_SW_BOT_BLEND_M1)) | - (s_RGA3_OVLP_BOT_ALPHA_SW_BOT_BLEND_M1 - (msg->alpha_mode_1 >> 9))); - reg = - ((reg & (~m_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_CAL_M1)) | - (s_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_CAL_M1 - (msg->alpha_mode_1 >> 11))); - reg = - ((reg & (~m_RGA3_OVLP_BOT_ALPHA_SW_BOT_FACTOR_M1)) | - (s_RGA3_OVLP_BOT_ALPHA_SW_BOT_FACTOR_M1 - (msg->alpha_mode_1 >> 12))); + /* + * Since the hardware uses 256 as 1, the original alpha value needs to + * be + (alpha >> 7). + */ + top_color_ctrl.bits.alpha_cal_mode = RGA_ALPHA_SATURATION; + bottom_color_ctrl.bits.alpha_cal_mode = RGA_ALPHA_SATURATION; - *bRGA_OVERLAP_BOT_ALPHA = reg; + top_color_ctrl.bits.global_alpha = config->fg_global_alpha_value; + bottom_color_ctrl.bits.global_alpha = config->fg_global_alpha_value; + + /* porter duff alpha enable */ + switch (config->mode) { + case RGA_ALPHA_BLEND_SRC: + /* + * SRC mode: + * Sf = 1, Df = 0； + * [Rc,Ra] = [Sc,Sa]； + */ + top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + top_color_ctrl.bits.factor_mode = RGA_ALPHA_ONE; + + bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO; + + break; + + case RGA_ALPHA_BLEND_DST: + /* + * SRC mode: + * Sf = 0, Df = 1； + * [Rc,Ra] = [Dc,Da]； + */ + top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + top_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO; + + bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ONE; + + break; + + case RGA_ALPHA_BLEND_SRC_OVER: + /* + * SRC-OVER mode: + * Sf = 1, Df = (1 - Sa) + * [Rc,Ra] = [ Sc + (1 - Sa) * Dc, Sa + (1 - Sa) * Da ] + */ + top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + top_color_ctrl.bits.factor_mode = RGA_ALPHA_ONE; + + bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE; + + break; + + case RGA_ALPHA_BLEND_DST_OVER: + /* + * DST-OVER mode: + * Sf = (1 - Da) , Df = 1 + * [Rc,Ra] = [ Sc * (1 - Da) + Dc, Sa * (1 - Da) + Da ] + */ + top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE; + + bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ONE; + + break; + + case RGA_ALPHA_BLEND_SRC_IN: + /* + * SRC-IN mode: + * Sf = Da , Df = 0 + * [Rc,Ra] = [ Sc * Da, Sa * Da ] + */ + top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE; + + bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO; + + break; + + case RGA_ALPHA_BLEND_DST_IN: + /* + * DST-IN mode: + * Sf = 0 , Df = Sa + * [Rc,Ra] = [ Dc * Sa, Da * Sa ] + */ + top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + top_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO; + + bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE; + + break; + + case RGA_ALPHA_BLEND_SRC_OUT: + /* + * SRC-OUT mode: + * Sf = (1 - Da) , Df = 0 + * [Rc,Ra] = [ Sc * (1 - Da), Sa * (1 - Da) ] + */ + top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE; + + bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO; + + break; + + case RGA_ALPHA_BLEND_DST_OUT: + /* + * DST-OUT mode: + * Sf = 0 , Df = (1 - Sa) + * [Rc,Ra] = [ Dc * (1 - Sa), Da * (1 - Sa) ] + */ + top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + top_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO; + + bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE; + + break; + + case RGA_ALPHA_BLEND_SRC_ATOP: + /* + * SRC-ATOP mode: + * Sf = Da , Df = (1 - Sa) + * [Rc,Ra] = [ Sc * Da + Dc * (1 - Sa), Sa * Da + Da * (1 - Sa) ] + */ + top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE; + + bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE; + + break; + + case RGA_ALPHA_BLEND_DST_ATOP: + /* + * DST-ATOP mode: + * Sf = (1 - Da) , Df = Sa + * [Rc,Ra] = [ Sc * (1 - Da) + Dc * Sa, Sa * (1 - Da) + Da * Sa ] + */ + top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE; + + bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE; + + break; + + case RGA_ALPHA_BLEND_XOR: + /* + * DST-XOR mode: + * Sf = (1 - Da) , Df = (1 - Sa) + * [Rc,Ra] = [ Sc * (1 - Da) + Dc * (1 - Sa), Sa * (1 - Da) + Da * (1 - Sa) ] + */ + top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE; + + bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE; + + break; + + case RGA_ALPHA_BLEND_CLEAR: + /* + * DST-CLEAR mode: + * Sf = 0 , Df = 0 + * [Rc,Ra] = [ 0, 0 ] + */ + top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + top_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO; + + bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT; + bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO; + + break; + + default: + break; + } + + if (!config->enable && msg->abb_alpha_pass) { + /* + * enabled by default bot_blend_m1 && bot_alpha_cal_m1 for src channel(win0) + * In ABB mode, the number will be fetched according to 16*16, so it needs to + * be enabled top_blend_m1 && top_alpha_cal_m1 for dst channel(wr). + */ + top_color_ctrl.bits.color_mode = RGA_ALPHA_PRE_MULTIPLIED; + + top_alpha_ctrl.bits.blend_mode = RGA_ALPHA_PER_PIXEL; + top_alpha_ctrl.bits.alpha_cal_mode = RGA_ALPHA_NO_SATURATION; + + bottom_color_ctrl.bits.color_mode = RGA_ALPHA_PRE_MULTIPLIED; + + bottom_alpha_ctrl.bits.blend_mode = RGA_ALPHA_PER_PIXEL; + bottom_alpha_ctrl.bits.alpha_cal_mode = RGA_ALPHA_NO_SATURATION; + } else { + top_color_ctrl.bits.color_mode = + config->fg_pre_multiplied ? + RGA_ALPHA_PRE_MULTIPLIED : RGA_ALPHA_NO_PRE_MULTIPLIED; + + top_alpha_ctrl.bits.blend_mode = top_color_ctrl.bits.blend_mode; + top_alpha_ctrl.bits.alpha_cal_mode = top_color_ctrl.bits.alpha_cal_mode; + top_alpha_ctrl.bits.alpha_mode = top_color_ctrl.bits.alpha_mode; + top_alpha_ctrl.bits.factor_mode = top_color_ctrl.bits.factor_mode; + + bottom_color_ctrl.bits.color_mode = + config->bg_pre_multiplied ? + RGA_ALPHA_PRE_MULTIPLIED : RGA_ALPHA_NO_PRE_MULTIPLIED; + + bottom_alpha_ctrl.bits.blend_mode = bottom_color_ctrl.bits.blend_mode; + bottom_alpha_ctrl.bits.alpha_cal_mode = bottom_color_ctrl.bits.alpha_cal_mode; + bottom_alpha_ctrl.bits.alpha_mode = bottom_color_ctrl.bits.alpha_mode; + bottom_alpha_ctrl.bits.factor_mode = bottom_color_ctrl.bits.factor_mode; + } + + *bRGA_OVERLAP_TOP_CTRL = top_color_ctrl.value; + *bRGA_OVERLAP_BOT_CTRL = bottom_color_ctrl.value; + *bRGA_OVERLAP_TOP_ALPHA = top_alpha_ctrl.value; + *bRGA_OVERLAP_BOT_ALPHA = bottom_alpha_ctrl.value; /* set RGA_OVERLAP_CTRL */ reg = 0; @@ -1166,9 +1320,8 @@ static void RGA3_set_reg_overlap_info(u8 *base, struct rga3_req *msg) * warning: if m1 & m0 need config split，need to redesign * this judge, which consider RGBA8888 format */ - if (msg->alpha_mode_1 > 0 && msg->alpha_mode_0 > 0) - reg = ((reg & (~m_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN)) | - (s_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN(1))); + reg = ((reg & (~m_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN)) | + (s_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN(config->enable))); *bRGA_OVERLAP_CTRL = reg; @@ -1261,7 +1414,6 @@ static void set_wr_info(struct rga_req *req_rga, struct rga3_req *req) /* TODO: common part */ static void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req) { - u16 alpha_mode_0, alpha_mode_1; struct rga_img_info_t tmp; req->render_mode = BITBLT_MODE; @@ -1324,8 +1476,8 @@ static void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req) if (!(req_rga->alpha_rop_flag & 1)) { if (!rga_is_alpha_format(req_rga->src.format) && rga_is_alpha_format(req_rga->dst.format)) { - req->win0_a_global_val = 0xff; - req->win1_a_global_val = 0xff; + req->alpha_config.fg_global_alpha_value = 0xff; + req->alpha_config.bg_global_alpha_value = 0xff; } } @@ -1345,7 +1497,7 @@ static void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req) * be enabled top_blend_m1 && top_alpha_cal_m1 for dst channel(wr). */ if (rga_is_alpha_format(req_rga->src.format)) - req->alpha_mode_1 = 0x0a0a; + req->abb_alpha_pass = true; set_win_info(&req->win0, &req_rga->src); @@ -1375,7 +1527,7 @@ static void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req) * be enabled bot_blend_m1 && bot_alpha_cal_m1 for src1/dst channel(win0). */ if (rga_is_alpha_format(req_rga->src.format)) - req->alpha_mode_1 = 0x0a0a; + req->abb_alpha_pass = true; if (req_rga->pat.yrgb_addr != 0) { if (req_rga->src.yrgb_addr == req_rga->dst.yrgb_addr) { @@ -1478,103 +1630,83 @@ static void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req) /* Alpha blend mode */ if (((req_rga->alpha_rop_flag) & 1)) { if ((req_rga->alpha_rop_flag >> 3) & 1) { + req->alpha_config.enable = true; + + if ((req_rga->alpha_rop_flag >> 9) & 1) { + req->alpha_config.fg_pre_multiplied = false; + req->alpha_config.bg_pre_multiplied = false; + } else { + req->alpha_config.fg_pre_multiplied = true; + req->alpha_config.bg_pre_multiplied = true; + } + + req->alpha_config.fg_pixel_alpha_en = rga_is_alpha_format(req->win1.format); + req->alpha_config.bg_pixel_alpha_en = rga_is_alpha_format(req->win0.format); + + req->alpha_config.fg_global_alpha_en = false; + req->alpha_config.bg_global_alpha_en = false; + + req->alpha_config.fg_global_alpha_value = req_rga->alpha_global_value; + req->alpha_config.bg_global_alpha_value = req_rga->alpha_global_value; + /* porter duff alpha enable */ switch (req_rga->PD_mode) { /* dst = 0 */ case 0: break; - /* dst = src */ case 1: - req->alpha_mode_0 = 0x0212; - req->alpha_mode_1 = 0x0212; + req->alpha_config.mode = RGA_ALPHA_BLEND_SRC; break; - /* dst = dst */ case 2: - req->alpha_mode_0 = 0x1202; - req->alpha_mode_1 = 0x1202; + req->alpha_config.mode = RGA_ALPHA_BLEND_DST; break; - /* dst = (256*sc + (256 - sa)*dc) >> 8 */ case 3: if ((req_rga->alpha_rop_mode & 3) == 0) { /* both use globalAlpha. */ - alpha_mode_0 = 0x3010; - alpha_mode_1 = 0x3010; + req->alpha_config.fg_global_alpha_en = true; + req->alpha_config.bg_global_alpha_en = true; } else if ((req_rga->alpha_rop_mode & 3) == 1) { /* Do not use globalAlpha. */ - alpha_mode_0 = 0x3212; - alpha_mode_1 = 0x3212; - } else if ((req_rga->alpha_rop_mode & 3) == 2) { - /* - * dst use globalAlpha, - * and dst has pixelAlpha. - */ - alpha_mode_0 = 0x3014; - alpha_mode_1 = 0x3014; + req->alpha_config.fg_global_alpha_en = false; + req->alpha_config.bg_global_alpha_en = false; } else { - /* - * dst use globalAlpha, - * and dst does not have pixelAlpha. - */ - alpha_mode_0 = 0x3012; - alpha_mode_1 = 0x3012; + /* dst use globalAlpha */ + req->alpha_config.fg_global_alpha_en = false; + req->alpha_config.bg_global_alpha_en = true; } - req->alpha_mode_0 = alpha_mode_0; - req->alpha_mode_1 = alpha_mode_1; + + req->alpha_config.mode = RGA_ALPHA_BLEND_SRC_OVER; break; - /* dst = (sc*(256-da) + 256*dc) >> 8 */ case 4: - /* Do not use globalAlpha. */ - req->alpha_mode_0 = 0x1232; - req->alpha_mode_1 = 0x1232; + req->alpha_config.mode = RGA_ALPHA_BLEND_DST_OVER; break; - /* dst = (da*sc) >> 8 */ case 5: + req->alpha_config.mode = RGA_ALPHA_BLEND_SRC_IN; break; - /* dst = (sa*dc) >> 8 */ case 6: + req->alpha_config.mode = RGA_ALPHA_BLEND_DST_IN; break; - /* dst = ((256-da)*sc) >> 8 */ case 7: + req->alpha_config.mode = RGA_ALPHA_BLEND_SRC_OUT; break; - /* dst = ((256-sa)*dc) >> 8 */ case 8: + req->alpha_config.mode = RGA_ALPHA_BLEND_DST_OUT; break; - /* dst = (da*sc + (256-sa)*dc) >> 8 */ case 9: - req->alpha_mode_0 = 0x3040; - req->alpha_mode_1 = 0x3040; + req->alpha_config.mode = RGA_ALPHA_BLEND_SRC_ATOP; break; - /* dst = ((256-da)*sc + (sa*dc)) >> 8 */ case 10: + req->alpha_config.mode = RGA_ALPHA_BLEND_DST_ATOP; break; - /* dst = ((256-da)*sc + (256-sa)*dc) >> 8 */ case 11: + req->alpha_config.mode = RGA_ALPHA_BLEND_XOR; break; case 12: - req->alpha_mode_0 = 0x0010; - req->alpha_mode_1 = 0x0820; + req->alpha_config.mode = RGA_ALPHA_BLEND_CLEAR; break; default: break; } - /* Real color mode */ - if ((req_rga->alpha_rop_flag >> 9) & 1) { - if (req->alpha_mode_0 & (0x01 << 1)) - req->alpha_mode_0 |= (1 << 7); - if (req->alpha_mode_0 & (0x01 << 9)) - req->alpha_mode_0 |= (1 << 15); - } - } else { - if ((req_rga->alpha_rop_mode & 3) == 0) { - req->alpha_mode_0 = 0x3040; - req->alpha_mode_1 = 0x3040; - } else if ((req_rga->alpha_rop_mode & 3) == 1) { - req->alpha_mode_0 = 0x3042; - req->alpha_mode_1 = 0x3242; - } else if ((req_rga->alpha_rop_mode & 3) == 2) { - req->alpha_mode_0 = 0x3044; - req->alpha_mode_1 = 0x3044; - } } } @@ -1651,10 +1783,11 @@ static void rga3_soft_reset(struct rga_scheduler_t *scheduler) } if (i == RGA_RESET_TIMEOUT) - pr_err("RGA3 soft reset timeout. SYS_CTRL[0x%x], RO_SRST[0x%x]\n", - rga_read(RGA3_SYS_CTRL, scheduler), rga_read(RGA3_RO_SRST, scheduler)); + pr_err("RGA3 core[%d] soft reset timeout. SYS_CTRL[0x%x], RO_SRST[0x%x]\n", + scheduler->core, rga_read(RGA3_SYS_CTRL, scheduler), + rga_read(RGA3_RO_SRST, scheduler)); else - pr_info("RGA3 soft reset complete.\n"); + pr_info("RGA3 core[%d] soft reset complete.\n", scheduler->core); } static int rga3_scale_check(const struct rga3_req *req) @@ -1821,11 +1954,14 @@ static void print_debug_info(struct rga3_req *req) pr_info("mmu: win0 = %.2x win1 = %.2x wr = %.2x\n", req->mmu_info.src0_mmu_flag, req->mmu_info.src1_mmu_flag, req->mmu_info.dst_mmu_flag); - pr_info("alpha: flag %x mode0=%x mode1=%x\n", req->alpha_rop_flag, - req->alpha_mode_0, req->alpha_mode_1); - pr_info("blend mode is %s\n", - rga_get_blend_mode_str(req->alpha_rop_flag, req->alpha_mode_0, - req->alpha_mode_1)); + pr_info("alpha: flag %x mode=%s\n", + req->alpha_rop_flag, rga_get_blend_mode_str(req->alpha_config.mode)); + pr_info("alpha: pre_multi=[%d,%d] pixl=[%d,%d] glb=[%d,%d]\n", + req->alpha_config.fg_pre_multiplied, req->alpha_config.bg_pre_multiplied, + req->alpha_config.fg_pixel_alpha_en, req->alpha_config.bg_pixel_alpha_en, + req->alpha_config.fg_global_alpha_en, req->alpha_config.bg_global_alpha_en); + pr_info("alpha: fg_global_alpha=%x bg_global_alpha=%x\n", + req->alpha_config.fg_global_alpha_value, req->alpha_config.bg_global_alpha_value); pr_info("yuv2rgb mode is %x\n", req->yuv2rgb_mode); } diff --git a/drivers/video/rockchip/rga3/rga_common.c b/drivers/video/rockchip/rga3/rga_common.c index dfe11032c95e..6f8b57921506 100644 --- a/drivers/video/rockchip/rga3/rga_common.c +++ b/drivers/video/rockchip/rga3/rga_common.c @@ -529,20 +529,49 @@ const char *rga_get_rotate_mode_str(uint8_t mode) } } -const char *rga_get_blend_mode_str(uint16_t alpha_rop_flag, - uint16_t alpha_mode_0, - uint16_t alpha_mode_1) +const char *rga_get_blend_mode_str(enum rga_alpha_blend_mode mode) { - if (alpha_rop_flag == 0) { + switch (mode) { + case RGA_ALPHA_NONE: return "no blend"; - } else if (alpha_rop_flag == 0x9) { - if (alpha_mode_0 == 0x381A && alpha_mode_1 == 0x381A) - return "105 src + (1-src.a)*dst"; - else if (alpha_mode_0 == 0x483A && alpha_mode_1 == 0x483A) - return "405 src.a * src + (1-src.a) * dst"; - else - return "check reg for more imformation"; - } else { + + case RGA_ALPHA_BLEND_SRC: + return "src"; + + case RGA_ALPHA_BLEND_DST: + return "dst"; + + case RGA_ALPHA_BLEND_SRC_OVER: + return "src-over"; + + case RGA_ALPHA_BLEND_DST_OVER: + return "dst-over"; + + case RGA_ALPHA_BLEND_SRC_IN: + return "src-in"; + + case RGA_ALPHA_BLEND_DST_IN: + return "dst-in"; + + case RGA_ALPHA_BLEND_SRC_OUT: + return "src-out"; + + case RGA_ALPHA_BLEND_DST_OUT: + return "dst-out"; + + case RGA_ALPHA_BLEND_SRC_ATOP: + return "src-atop"; + + case RGA_ALPHA_BLEND_DST_ATOP: + return "dst-atop"; + + case RGA_ALPHA_BLEND_XOR: + return "xor"; + + case RGA_ALPHA_BLEND_CLEAR: + return "clear"; + + default: return "check reg for more imformation"; } } diff --git a/drivers/video/rockchip/rga3/rga_job.c b/drivers/video/rockchip/rga3/rga_job.c index bbe6fa87e82f..37e29bb689f4 100644 --- a/drivers/video/rockchip/rga3/rga_job.c +++ b/drivers/video/rockchip/rga3/rga_job.c @@ -650,7 +650,8 @@ static int rga_request_scheduler_job_abort(struct rga_request *request) scheduler->ops->soft_reset(scheduler); } - pr_err("reset core[%d] by request abort", scheduler->core); + pr_err("reset core[%d] by request[%d] abort", + scheduler->core, request->id); running_abort_count++; } } @@ -757,12 +758,13 @@ static int rga_request_timeout_query_state(struct rga_request *request) } else if (!test_bit(RGA_JOB_STATE_DONE, &job->state) && test_bit(RGA_JOB_STATE_FINISH, &job->state)) { spin_unlock_irqrestore(&scheduler->irq_lock, flags); - pr_err("hardware has finished, but the software has timeout!\n"); + pr_err("request[%d] hardware has finished, but the software has timeout!\n", + request->id); return -EBUSY; } else if (!test_bit(RGA_JOB_STATE_DONE, &job->state) && !test_bit(RGA_JOB_STATE_FINISH, &job->state)) { spin_unlock_irqrestore(&scheduler->irq_lock, flags); - pr_err("hardware has timeout.\n"); + pr_err("request[%d] hardware has timeout.\n", request->id); return -EBUSY; } } @@ -835,7 +837,7 @@ static void rga_request_acquire_fence_signaled_cb(struct dma_fence *fence, struct rga_pending_request_manager *request_manager = rga_drvdata->pend_request_manager; if (rga_request_commit(request)) - pr_err("rga request commit failed!\n"); + pr_err("rga request[%d] commit failed!\n", request->id); mutex_lock(&request_manager->lock); rga_request_put(request); @@ -1099,7 +1101,7 @@ int rga_request_submit(struct rga_request *request) request_commit: ret = rga_request_commit(request); if (ret < 0) { - pr_err("rga request commit failed!\n"); + pr_err("rga request[%d] commit failed!\n", request->id); goto err_put_release_fence; } diff --git a/drivers/video/rockchip/vehicle/vehicle_ad_nvp6324.c b/drivers/video/rockchip/vehicle/vehicle_ad_nvp6324.c index 4c1b3da8176e..3f5115fd097c 100644 --- a/drivers/video/rockchip/vehicle/vehicle_ad_nvp6324.c +++ b/drivers/video/rockchip/vehicle/vehicle_ad_nvp6324.c @@ -96,6 +96,848 @@ struct rk_sensor_reg { #define SENSOR_ID(_msb, _lsb) ((_msb) << 8 | (_lsb)) +/* NTSC Preview resolution setting*/ +static struct rk_sensor_reg sensor_preview_data_ntsc_30hz[] = { + {0xff, 0x04}, + {0xa0, 0x24}, + {0xa1, 0x24}, + {0xa2, 0x24}, + {0xa3, 0x24}, + {0xa4, 0x24}, + {0xa5, 0x24}, + {0xa6, 0x24}, + {0xa7, 0x24}, + {0xa8, 0x24}, + {0xa9, 0x24}, + {0xaa, 0x24}, + {0xab, 0x24}, + {0xac, 0x24}, + {0xad, 0x24}, + {0xae, 0x24}, + {0xaf, 0x24}, + {0xb0, 0x24}, + {0xb1, 0x24}, + {0xb2, 0x24}, + {0xb3, 0x24}, + {0xb4, 0x24}, + {0xb5, 0x24}, + {0xb6, 0x24}, + {0xb7, 0x24}, + {0xb8, 0x24}, + {0xb9, 0x24}, + {0xba, 0x24}, + {0xbb, 0x24}, + {0xbc, 0x24}, + {0xbd, 0x24}, + {0xbe, 0x24}, + {0xbf, 0x24}, + {0xc0, 0x24}, + {0xc1, 0x24}, + {0xc2, 0x24}, + {0xc3, 0x24}, + {0xff, 0x21}, + {0x07, 0x80}, + {0x07, 0x00}, + {0xff, 0x0A}, + {0x77, 0x8F}, + {0xF7, 0x8F}, + {0xff, 0x0B}, + {0x77, 0x8F}, + {0xF7, 0x8F}, + + {0xFF, 0x21}, + {0x40, 0xAC}, + {0x41, 0x10}, + {0x42, 0x03}, + {0x43, 0x43}, + {0x11, 0x04}, + {0x10, 0x0A}, + {0x12, 0x06}, + {0x13, 0x09}, + {0x17, 0x01}, + {0x18, 0x0D}, + {0x15, 0x04}, + {0x14, 0x16}, + {0x16, 0x05}, + {0x19, 0x05}, + {0x1A, 0x0A}, + {0x1B, 0x08}, + {0x1C, 0x07}, + {0x44, 0x00}, + {0x49, 0xF3}, + {0x49, 0xF0}, + {0x44, 0x02}, + {0x08, 0x40}, //0x40:non-continue;0x48:continuous + {0x0F, 0x01}, + {0x38, 0x1E}, + {0x39, 0x1E}, + {0x3A, 0x1E}, + {0x3B, 0x1E}, + {0x07, 0x0f}, //0x07:2lane;0x0f:4lane + {0x2D, 0x01}, //0x00:2lane;0x01:4lane + {0x45, 0x02}, + {0xFF, 0x13}, + {0x30, 0x00}, + {0x31, 0x00}, + {0x32, 0x00}, + + {0xFF, 0x00}, + {0x00, 0x00}, + {0x01, 0x00}, + {0x02, 0x00}, + {0x03, 0x00}, + {0x04, 0x0e}, //sd_mode + {0x05, 0x0e}, + {0x06, 0x0e}, + {0x07, 0x0e}, + {0x08, 0x00}, //ahd_mode + {0x09, 0x00}, + {0x0a, 0x00}, + {0x0b, 0x00}, + {0x0c, 0x00}, + {0x0d, 0x00}, + {0x0e, 0x00}, + {0x0f, 0x00}, + {0x10, 0xa0}, //video_format + {0x11, 0xa0}, + {0x12, 0xa0}, + {0x13, 0xa0}, + {0x14, 0x00}, + {0x15, 0x00}, + {0x16, 0x00}, + {0x17, 0x00}, + {0x18, 0x13}, + {0x19, 0x13}, + {0x1a, 0x13}, + {0x1b, 0x13}, + {0x1c, 0x1a}, + {0x1d, 0x1a}, + {0x1e, 0x1a}, + {0x1f, 0x1a}, + {0x20, 0x00}, + {0x21, 0x00}, + {0x22, 0x00}, + {0x23, 0x00}, + {0x24, 0x90}, //contrast + {0x25, 0x90}, + {0x26, 0x90}, + {0x27, 0x90}, + {0x28, 0x90}, //black_level + {0x29, 0x90}, + {0x2a, 0x90}, + {0x2b, 0x90}, + {0x30, 0x00}, //y_peaking_mode + {0x31, 0x00}, + {0x32, 0x00}, + {0x33, 0x00}, + {0x34, 0x08}, //y_fir_mode + {0x35, 0x08}, + {0x36, 0x08}, + {0x37, 0x08}, + {0x40, 0x00}, + {0x41, 0x00}, + {0x42, 0x00}, + {0x43, 0x00}, + {0x44, 0x00}, + {0x45, 0x00}, + {0x46, 0x00}, + {0x47, 0x00}, + {0x48, 0x00}, + {0x49, 0x00}, + {0x4a, 0x00}, + {0x4b, 0x00}, + {0x4c, 0xfe}, + {0x4d, 0xfe}, + {0x4e, 0xfe}, + {0x4f, 0xfe}, + {0x50, 0xfb}, + {0x51, 0xfb}, + {0x52, 0xfb}, + {0x53, 0xfb}, + {0x58, 0x80}, + {0x59, 0x80}, + {0x5a, 0x80}, + {0x5b, 0x80}, + {0x5c, 0x82}, //pal_cm_off + {0x5d, 0x82}, + {0x5e, 0x82}, + {0x5f, 0x82}, + {0x60, 0x10}, + {0x61, 0x10}, + {0x62, 0x10}, + {0x63, 0x10}, + {0x64, 0x18}, //y_delay + {0x65, 0x18}, + {0x66, 0x18}, + {0x67, 0x18}, + {0x68, 0x70}, //h_delay_a //h_delay_lsb + {0x69, 0x70}, + {0x6a, 0x70}, + {0x6b, 0x70}, + {0x6c, 0x00}, + {0x6d, 0x00}, + {0x6e, 0x00}, + {0x6f, 0x00}, + {0x70, 0x9e}, //v_crop_start + {0x71, 0x9e}, + {0x72, 0x9e}, + {0x73, 0x9e}, + {0x78, 0xc0}, + {0x79, 0xc0}, + {0x7a, 0xc0}, + {0x7b, 0xc0}, + + {0xFF, 0x01}, + {0x7C, 0x00}, + {0x84, 0x04}, + {0x85, 0x04}, + {0x86, 0x04}, + {0x87, 0x04}, + {0x88, 0x01}, + {0x89, 0x01}, + {0x8a, 0x01}, + {0x8b, 0x01}, + {0x8c, 0x02}, + {0x8d, 0x02}, + {0x8e, 0x02}, + {0x8f, 0x02}, + {0xEC, 0x00}, + {0xED, 0x00}, + {0xEE, 0x00}, + {0xEF, 0x00}, + + {0xFF, 0x05}, + {0x00, 0xd0}, + {0x01, 0x2c}, + {0x05, 0x20}, //d_agc_option + {0x1d, 0x0c}, + {0x21, 0x20}, //sub contrast + {0x24, 0x2a}, + {0x25, 0xdc}, //fsc_lock_mode + {0x26, 0x40}, + {0x27, 0x57}, + {0x28, 0x80}, //s_point + {0x2b, 0xc0}, //saturation_b + {0x31, 0x82}, + {0x32, 0x10}, + {0x38, 0x00}, + {0x47, 0x04}, + {0x50, 0x84}, + {0x53, 0x04}, + {0x57, 0x00}, + {0x58, 0x77}, + {0x59, 0x00}, + {0x5C, 0x78}, + {0x5F, 0x00}, + {0x62, 0x20}, + {0x64, 0x01}, + {0x65, 0x00}, + {0x69, 0x00}, + {0x6E, 0x00}, //VBLK_EXT_EN + {0x6F, 0x00}, //VBLK_EXT_[7:0] + {0x90, 0x01}, //comb_mode + {0x92, 0x00}, + {0x94, 0x00}, + {0x95, 0x00}, + {0xa9, 0x00}, + {0xb5, 0x00}, + {0xb7, 0xfc}, + {0xb8, 0xb8}, + {0xb9, 0x72}, + {0xbb, 0x0f}, + {0xd1, 0x30}, //burst_dec_c + {0xd5, 0x80}, + + {0xFF, 0x09}, + {0x40, 0x00}, + {0x41, 0x00}, + {0x42, 0x00}, + {0x43, 0x00}, + {0x44, 0x00}, + {0x45, 0x00}, + {0x46, 0x00}, + {0x47, 0x00}, + {0x50, 0x30}, + {0x51, 0x6f}, + {0x52, 0x67}, + {0x53, 0x48}, + {0x54, 0x30}, + {0x55, 0x6f}, + {0x56, 0x67}, + {0x57, 0x48}, + {0x58, 0x30}, + {0x59, 0x6f}, + {0x5a, 0x67}, + {0x5b, 0x48}, + {0x5c, 0x30}, + {0x5d, 0x6f}, + {0x5e, 0x67}, + {0x5f, 0x48}, + {0x96, 0x10}, + {0x97, 0x10}, + {0x98, 0x00}, + {0x99, 0x00}, + {0x9a, 0x00}, + {0x9b, 0x00}, + {0x9c, 0x00}, + {0x9d, 0x00}, + {0x9e, 0x00}, + {0xb6, 0x10}, + {0xb7, 0x10}, + {0xb8, 0x00}, + {0xb9, 0x00}, + {0xba, 0x00}, + {0xbb, 0x00}, + {0xbc, 0x00}, + {0xbd, 0x00}, + {0xbe, 0x00}, + {0xd6, 0x10}, + {0xd7, 0x10}, + {0xd8, 0x00}, + {0xd9, 0x00}, + {0xda, 0x00}, + {0xdb, 0x00}, + {0xdc, 0x00}, + {0xdd, 0x00}, + {0xde, 0x00}, + {0xf6, 0x10}, + {0xf7, 0x10}, + {0xf8, 0x00}, + {0xf9, 0x00}, + {0xfa, 0x00}, + {0xfb, 0x00}, + {0xfc, 0x00}, + {0xfd, 0x00}, + {0xfe, 0x00}, + + {0xff, 0x0a}, + {0x3d, 0x00}, + {0x3c, 0x00}, + {0x30, 0xac}, + {0x31, 0x78}, + {0x32, 0x17}, + {0x33, 0xc1}, + {0x34, 0x40}, + {0x35, 0x00}, + {0x36, 0xc3}, + {0x37, 0x0a}, + {0x38, 0x00}, + {0x39, 0x02}, + {0x3a, 0x00}, + {0x3b, 0xb2}, + {0x25, 0x10}, + {0x27, 0x1e}, + {0xbd, 0x00}, + {0xbc, 0x00}, + {0xb0, 0xac}, + {0xb1, 0x78}, + {0xb2, 0x17}, + {0xb3, 0xc1}, + {0xb4, 0x40}, + {0xb5, 0x00}, + {0xb6, 0xc3}, + {0xb7, 0x0a}, + {0xb8, 0x00}, + {0xb9, 0x02}, + {0xba, 0x00}, + {0xbb, 0xb2}, + {0xa5, 0x10}, + {0xa7, 0x1e}, + + {0xff, 0x0b}, + {0x3d, 0x00}, + {0x3c, 0x00}, + {0x30, 0xac}, + {0x31, 0x78}, + {0x32, 0x17}, + {0x33, 0xc1}, + {0x34, 0x40}, + {0x35, 0x00}, + {0x36, 0xc3}, + {0x37, 0x0a}, + {0x38, 0x00}, + {0x39, 0x02}, + {0x3a, 0x00}, + {0x3b, 0xb2}, + {0x25, 0x10}, + {0x27, 0x1e}, + {0xbd, 0x00}, + {0xbc, 0x00}, + {0xb0, 0xac}, + {0xb1, 0x78}, + {0xb2, 0x17}, + {0xb3, 0xc1}, + {0xb4, 0x40}, + {0xb5, 0x00}, + {0xb6, 0xc3}, + {0xb7, 0x0a}, + {0xb8, 0x00}, + {0xb9, 0x02}, + {0xba, 0x00}, + {0xbb, 0xb2}, + {0xa5, 0x10}, + {0xa7, 0x1e}, + + {0xFF, 0x21}, + {0x3E, 0x00}, + {0x3F, 0x00}, + {0xFF, 0x20}, + {0x01, 0xaa}, //0x00:1/1;0x55:1/2;0xaa:1/4 + {0x00, 0x00}, + {0x40, 0x01}, + {0x0F, 0x00}, + {0x0D, 0x01}, //0x01:4lane;0x00:2lane + {0x40, 0x00}, + {0x00, 0xff}, //0xff:ch1/2/3/4 0x33:ch1/2 0x11:ch1 + + {0xFF, 0x01}, + {0xC8, 0x00}, + {0xC9, 0x00}, + {0xCA, 0x00}, + {0xCB, 0x00}, + + //pattern enabled + {0xFF, 0x00}, + {0x1C, 0x1A}, + {0x1D, 0x1A}, + {0x1E, 0x1A}, + {0x1F, 0x1A}, + + {0xFF, 0x05}, + {0x6A, 0x80}, + {0xFF, 0x06}, + {0x6A, 0x80}, + {0xFF, 0x07}, + {0x6A, 0x80}, + {0xFF, 0x08}, + {0x6A, 0x80}, + {0xFF, 0x21}, //add frame num + {0x3E, 0x11}, //1 : Fix to 1 for Odd Field, 2 for Even Field + {0x3F, 0x11}, //1 : Fix to 1 for Odd Field, 2 for Even Field + SensorEnd +}; + +/* Pal Preview resolution setting*/ +static struct rk_sensor_reg sensor_preview_data_pal_25hz[] = { + {0xff, 0x04}, + {0xa0, 0x24}, + {0xa1, 0x24}, + {0xa2, 0x24}, + {0xa3, 0x24}, + {0xa4, 0x24}, + {0xa5, 0x24}, + {0xa6, 0x24}, + {0xa7, 0x24}, + {0xa8, 0x24}, + {0xa9, 0x24}, + {0xaa, 0x24}, + {0xab, 0x24}, + {0xac, 0x24}, + {0xad, 0x24}, + {0xae, 0x24}, + {0xaf, 0x24}, + {0xb0, 0x24}, + {0xb1, 0x24}, + {0xb2, 0x24}, + {0xb3, 0x24}, + {0xb4, 0x24}, + {0xb5, 0x24}, + {0xb6, 0x24}, + {0xb7, 0x24}, + {0xb8, 0x24}, + {0xb9, 0x24}, + {0xba, 0x24}, + {0xbb, 0x24}, + {0xbc, 0x24}, + {0xbd, 0x24}, + {0xbe, 0x24}, + {0xbf, 0x24}, + {0xc0, 0x24}, + {0xc1, 0x24}, + {0xc2, 0x24}, + {0xc3, 0x24}, + {0xff, 0x21}, + {0x07, 0x80}, + {0x07, 0x00}, + {0xff, 0x0A}, + {0x77, 0x8F}, + {0xF7, 0x8F}, + {0xff, 0x0B}, + {0x77, 0x8F}, + {0xF7, 0x8F}, + + {0xFF, 0x21}, + {0x40, 0xAC}, + {0x41, 0x10}, + {0x42, 0x03}, + {0x43, 0x43}, + {0x11, 0x04}, + {0x10, 0x0A}, + {0x12, 0x06}, + {0x13, 0x09}, + {0x17, 0x01}, + {0x18, 0x0D}, + {0x15, 0x04}, + {0x14, 0x16}, + {0x16, 0x05}, + {0x19, 0x05}, + {0x1A, 0x0A}, + {0x1B, 0x08}, + {0x1C, 0x07}, + {0x44, 0x00}, + {0x49, 0xF3}, + {0x49, 0xF0}, + {0x44, 0x02}, + {0x08, 0x40}, //0x40:non-continue;0x48:continuous + {0x0F, 0x01}, + {0x38, 0x1E}, + {0x39, 0x1E}, + {0x3A, 0x1E}, + {0x3B, 0x1E}, + {0x07, 0x0f}, //0x07:2lane;0x0f:4lane + {0x2D, 0x01}, //0x00:2lane;0x01:4lane + {0x45, 0x02}, + {0xFF, 0x13}, + {0x30, 0x00}, + {0x31, 0x00}, + {0x32, 0x00}, + + {0xFF, 0x00}, + {0x00, 0x00}, + {0x01, 0x00}, + {0x02, 0x00}, + {0x03, 0x00}, + {0x04, 0x0f}, //sd_mode + {0x05, 0x0f}, + {0x06, 0x0f}, + {0x07, 0x0f}, + {0x08, 0x00}, //ahd_mode + {0x09, 0x00}, + {0x0a, 0x00}, + {0x0b, 0x00}, + {0x0c, 0x00}, + {0x0d, 0x00}, + {0x0e, 0x00}, + {0x0f, 0x00}, + {0x10, 0xdd}, //video_format + {0x11, 0xdd}, + {0x12, 0xdd}, + {0x13, 0xdd}, + {0x14, 0x00}, + {0x15, 0x00}, + {0x16, 0x00}, + {0x17, 0x00}, + {0x18, 0x13}, + {0x19, 0x13}, + {0x1a, 0x13}, + {0x1b, 0x13}, + {0x1c, 0x1a}, + {0x1d, 0x1a}, + {0x1e, 0x1a}, + {0x1f, 0x1a}, + {0x20, 0x00}, + {0x21, 0x00}, + {0x22, 0x00}, + {0x23, 0x00}, + {0x24, 0x90}, //contrast + {0x25, 0x90}, + {0x26, 0x90}, + {0x27, 0x90}, + {0x28, 0x90}, //black_level + {0x29, 0x90}, + {0x2a, 0x90}, + {0x2b, 0x90}, + {0x30, 0x00}, //y_peaking_mode + {0x31, 0x00}, + {0x32, 0x00}, + {0x33, 0x00}, + {0x34, 0x08}, //y_fir_mode + {0x35, 0x08}, + {0x36, 0x08}, + {0x37, 0x08}, + {0x40, 0x00}, + {0x41, 0x00}, + {0x42, 0x00}, + {0x43, 0x00}, + {0x44, 0x00}, + {0x45, 0x00}, + {0x46, 0x00}, + {0x47, 0x00}, + {0x48, 0x00}, + {0x49, 0x00}, + {0x4a, 0x00}, + {0x4b, 0x00}, + {0x4c, 0xfe}, + {0x4d, 0xfe}, + {0x4e, 0xfe}, + {0x4f, 0xfe}, + {0x50, 0xfb}, + {0x51, 0xfb}, + {0x52, 0xfb}, + {0x53, 0xfb}, + {0x58, 0x80}, + {0x59, 0x80}, + {0x5a, 0x80}, + {0x5b, 0x80}, + {0x5c, 0x82}, //pal_cm_off + {0x5d, 0x82}, + {0x5e, 0x82}, + {0x5f, 0x82}, + {0x60, 0x10}, + {0x61, 0x10}, + {0x62, 0x10}, + {0x63, 0x10}, + {0x64, 0x07}, //y_delay + {0x65, 0x07}, + {0x66, 0x07}, + {0x67, 0x07}, + {0x68, 0x68}, //h_delay_a //h_delay_lsb + {0x69, 0x68}, + {0x6a, 0x68}, + {0x6b, 0x68}, + {0x6c, 0x00}, + {0x6d, 0x00}, + {0x6e, 0x00}, + {0x6f, 0x00}, + {0x70, 0x3f}, //v_crop_start + {0x71, 0x3f}, + {0x72, 0x3f}, + {0x73, 0x3f}, + {0x78, 0x21}, + {0x79, 0x21}, + {0x7a, 0x21}, + {0x7b, 0x21}, + + {0xFF, 0x01}, + {0x7C, 0x00}, + {0x84, 0x04}, + {0x85, 0x04}, + {0x86, 0x04}, + {0x87, 0x04}, + {0x88, 0x01}, + {0x89, 0x01}, + {0x8a, 0x01}, + {0x8b, 0x01}, + {0x8c, 0x02}, + {0x8d, 0x02}, + {0x8e, 0x02}, + {0x8f, 0x02}, + {0xEC, 0x00}, + {0xED, 0x00}, + {0xEE, 0x00}, + {0xEF, 0x00}, + + {0xFF, 0x05}, + {0x00, 0xd0}, + {0x01, 0x2c}, + {0x05, 0x20}, //d_agc_option + {0x1d, 0x0c}, + {0x21, 0x20}, //sub contrast + {0x24, 0x2a}, + {0x25, 0xcc}, //fsc_lock_mode + {0x26, 0x40}, + {0x27, 0x57}, + {0x28, 0x80}, //s_point + {0x2b, 0xc0}, //saturation_b + {0x31, 0x02}, + {0x32, 0x10}, + {0x38, 0x00}, + {0x47, 0xEE}, + {0x50, 0xc6}, + {0x53, 0x04}, + {0x57, 0x00}, + {0x58, 0x77}, + {0x59, 0x00}, + {0x5C, 0x78}, + {0x5F, 0x00}, + {0x62, 0x20}, + {0x64, 0x01}, + {0x65, 0x00}, + {0x69, 0x00}, + {0x6E, 0x00}, //VBLK_EXT_EN + {0x6F, 0x00}, //VBLK_EXT_[7:0] + {0x90, 0x0d}, //comb_mode + {0x92, 0x00}, + {0x94, 0x00}, + {0x95, 0x00}, + {0xa9, 0x00}, + {0xb5, 0x00}, + {0xb7, 0xfc}, + {0xb8, 0xb8}, + {0xb9, 0x72}, + {0xbb, 0x0f}, + {0xd1, 0x30}, //burst_dec_c + {0xd5, 0x80}, + + {0xFF, 0x09}, + {0x40, 0x00}, + {0x41, 0x00}, + {0x42, 0x00}, + {0x43, 0x00}, + {0x44, 0x00}, + {0x45, 0x00}, + {0x46, 0x00}, + {0x47, 0x00}, + {0x50, 0x30}, + {0x51, 0x6f}, + {0x52, 0x67}, + {0x53, 0x48}, + {0x54, 0x30}, + {0x55, 0x6f}, + {0x56, 0x67}, + {0x57, 0x48}, + {0x58, 0x30}, + {0x59, 0x6f}, + {0x5a, 0x67}, + {0x5b, 0x48}, + {0x5c, 0x30}, + {0x5d, 0x6f}, + {0x5e, 0x67}, + {0x5f, 0x48}, + {0x96, 0x10}, + {0x97, 0x10}, + {0x98, 0x00}, + {0x99, 0x00}, + {0x9a, 0x00}, + {0x9b, 0x00}, + {0x9c, 0x00}, + {0x9d, 0x00}, + {0x9e, 0x00}, + {0xb6, 0x10}, + {0xb7, 0x10}, + {0xb8, 0x00}, + {0xb9, 0x00}, + {0xba, 0x00}, + {0xbb, 0x00}, + {0xbc, 0x00}, + {0xbd, 0x00}, + {0xbe, 0x00}, + {0xd6, 0x10}, + {0xd7, 0x10}, + {0xd8, 0x00}, + {0xd9, 0x00}, + {0xda, 0x00}, + {0xdb, 0x00}, + {0xdc, 0x00}, + {0xdd, 0x00}, + {0xde, 0x00}, + {0xf6, 0x10}, + {0xf7, 0x10}, + {0xf8, 0x00}, + {0xf9, 0x00}, + {0xfa, 0x00}, + {0xfb, 0x00}, + {0xfc, 0x00}, + {0xfd, 0x00}, + {0xfe, 0x00}, + + {0xff, 0x0a}, + {0x3d, 0x00}, + {0x3c, 0x00}, + {0x30, 0xac}, + {0x31, 0x78}, + {0x32, 0x17}, + {0x33, 0xc1}, + {0x34, 0x40}, + {0x35, 0x00}, + {0x36, 0xc3}, + {0x37, 0x0a}, + {0x38, 0x00}, + {0x39, 0x02}, + {0x3a, 0x00}, + {0x3b, 0xb2}, + {0x25, 0x10}, + {0x27, 0x1e}, + {0xbd, 0x00}, + {0xbc, 0x00}, + {0xb0, 0xac}, + {0xb1, 0x78}, + {0xb2, 0x17}, + {0xb3, 0xc1}, + {0xb4, 0x40}, + {0xb5, 0x00}, + {0xb6, 0xc3}, + {0xb7, 0x0a}, + {0xb8, 0x00}, + {0xb9, 0x02}, + {0xba, 0x00}, + {0xbb, 0xb2}, + {0xa5, 0x10}, + {0xa7, 0x1e}, + + {0xff, 0x0b}, + {0x3d, 0x00}, + {0x3c, 0x00}, + {0x30, 0xac}, + {0x31, 0x78}, + {0x32, 0x17}, + {0x33, 0xc1}, + {0x34, 0x40}, + {0x35, 0x00}, + {0x36, 0xc3}, + {0x37, 0x0a}, + {0x38, 0x00}, + {0x39, 0x02}, + {0x3a, 0x00}, + {0x3b, 0xb2}, + {0x25, 0x10}, + {0x27, 0x1e}, + {0xbd, 0x00}, + {0xbc, 0x00}, + {0xb0, 0xac}, + {0xb1, 0x78}, + {0xb2, 0x17}, + {0xb3, 0xc1}, + {0xb4, 0x40}, + {0xb5, 0x00}, + {0xb6, 0xc3}, + {0xb7, 0x0a}, + {0xb8, 0x00}, + {0xb9, 0x02}, + {0xba, 0x00}, + {0xbb, 0xb2}, + {0xa5, 0x10}, + {0xa7, 0x1e}, + + {0xFF, 0x21}, + {0x3E, 0x00}, + {0x3F, 0x00}, + {0xFF, 0x20}, + {0x01, 0xaa}, //0x00:1/1;0x55:1/2;0xaa:1/4 + {0x00, 0x00}, + {0x40, 0x01}, + {0x0F, 0x00}, + {0x0D, 0x01}, //0x01:4lane;0x00:2lane + {0x40, 0x00}, + {0x00, 0xff}, //0xff:ch1/2/3/4 0x33:ch1/2 0x11:ch1 + + {0xFF, 0x01}, + {0xC8, 0x00}, + {0xC9, 0x00}, + {0xCA, 0x00}, + {0xCB, 0x00}, + + //pattern enabled + {0xFF, 0x00}, + {0x1C, 0x1A}, + {0x1D, 0x1A}, + {0x1E, 0x1A}, + {0x1F, 0x1A}, + + {0xFF, 0x05}, + {0x6A, 0x80}, + {0xFF, 0x06}, + {0x6A, 0x80}, + {0xFF, 0x07}, + {0x6A, 0x80}, + {0xFF, 0x08}, + {0x6A, 0x80}, + {0xFF, 0x21}, //add frame num + {0x3E, 0x11}, //1 : Fix to 1 for Odd Field, 2 for Even Field + {0x3F, 0x11}, //1 : Fix to 1 for Odd Field, 2 for Even Field + SensorEnd +}; + /* 720p Preview resolution setting*/ static struct rk_sensor_reg sensor_preview_data_720p_25hz[] = { {0xff, 0x04}, @@ -923,6 +1765,34 @@ static void nvp6324_reinit_parameter(struct vehicle_ad_dev *ad, unsigned char cv int i = 0; switch (cvstd) { + case CVSTD_PAL: + ad->cfg.width = FORCE_PAL_WIDTH; + ad->cfg.height = FORCE_PAL_HEIGHT; + ad->cfg.start_x = 0; + ad->cfg.start_y = 0; + ad->cfg.input_format = CIF_INPUT_FORMAT_PAL; + ad->cfg.output_format = FORCE_CIF_OUTPUT_FORMAT; + ad->cfg.field_order = 1; + ad->cfg.yuv_order = 0;/*00 - UYVY*/ + ad->cfg.href = 0; + ad->cfg.vsync = 0; + ad->cfg.frame_rate = 25;//25 30 + ad->cfg.mipi_freq = JAGUAR1_LINK_FREQ_320M; + break; + case CVSTD_NTSC: + ad->cfg.width = FORCE_NTSC_WIDTH; + ad->cfg.height = FORCE_NTSC_HEIGHT; + ad->cfg.start_x = 0; + ad->cfg.start_y = 0; + ad->cfg.input_format = CIF_INPUT_FORMAT_NTSC; + ad->cfg.output_format = FORCE_CIF_OUTPUT_FORMAT; + ad->cfg.field_order = 1; + ad->cfg.yuv_order = 0;/*00 - UYVY*/ + ad->cfg.href = 0; + ad->cfg.vsync = 0; + ad->cfg.frame_rate = 30;//25 30 + ad->cfg.mipi_freq = JAGUAR1_LINK_FREQ_320M; + break; case CVSTD_720P25: ad->cfg.width = 1280; ad->cfg.height = 720; @@ -1009,6 +1879,14 @@ static void nvp6324_reg_init(struct vehicle_ad_dev *ad, unsigned char cvstd) int i; switch (cvstd) { + case CVSTD_NTSC: + VEHICLE_DG("%s, init CVSTD_NTSC mode", __func__); + sensor = sensor_preview_data_ntsc_30hz; + break; + case CVSTD_PAL: + VEHICLE_DG("%s, init CVSTD_PAL mode", __func__); + sensor = sensor_preview_data_pal_25hz; + break; case CVSTD_720P25: VEHICLE_DG("%s, init CVSTD_720P25 mode)", __func__); sensor = sensor_preview_data_720p_25hz; @@ -1167,10 +2045,10 @@ static int nvp6324_check_cvstd(struct vehicle_ad_dev *ad, bool activate_check) VEHICLE_DG("%s(%d): 1080P25", __func__, __LINE__); } else if (cvstd == 0x00) { cvstd_mode = CVSTD_NTSC; - VEHICLE_DG("%s(%d): 720H NTSC\n", __func__, __LINE__); + VEHICLE_DG("%s(%d): 960H NTSC\n", __func__, __LINE__); } else if (cvstd == 0x10) { cvstd_mode = CVSTD_PAL; - VEHICLE_DG("%s(%d): 720H PAL\n", __func__, __LINE__); + VEHICLE_DG("%s(%d): 960H PAL\n", __func__, __LINE__); } else if (cvstd == 0xff) { cvstd_mode = cvstd_old; VEHICLE_DG("%s(%d): no ahd plugin!\n", __func__, __LINE__); diff --git a/drivers/video/rockchip/vehicle/vehicle_cif.c b/drivers/video/rockchip/vehicle/vehicle_cif.c index 7d2e08e8e0f4..904cd206116b 100644 --- a/drivers/video/rockchip/vehicle/vehicle_cif.c +++ b/drivers/video/rockchip/vehicle/vehicle_cif.c @@ -2266,6 +2266,31 @@ static enum cif_reg_index get_reg_index_of_frm0_y_addr(int channel_id) return index; } +static enum cif_reg_index get_reg_index_of_frm_num(int channel_id) +{ + enum cif_reg_index index; + + switch (channel_id) { + case 0: + index = CIF_REG_MIPI_FRAME_NUM_VC0; + break; + case 1: + index = CIF_REG_MIPI_FRAME_NUM_VC1; + break; + case 2: + index = CIF_REG_MIPI_FRAME_NUM_VC2; + break; + case 3: + index = CIF_REG_MIPI_FRAME_NUM_VC3; + break; + default: + index = CIF_REG_MIPI_FRAME_NUM_VC0; + break; + } + + return index; +} + static enum cif_reg_index get_reg_index_of_frm1_y_addr(int channel_id) { enum cif_reg_index index; @@ -2758,14 +2783,14 @@ static int vehicle_cif_csi_channel_init(struct vehicle_cif *cif, VEHICLE_DG("%s, LINE=%d, channel->fmt_val = 0x%x", __func__, __LINE__, channel->fmt_val); if (cfg->input_format == CIF_INPUT_FORMAT_PAL || cfg->input_format == CIF_INPUT_FORMAT_NTSC) { - VEHICLE_DG("CVBS IN PAL or NTSC config."); + VEHICLE_INFO("CVBS IN PAL or NTSC config."); channel->virtual_width *= 2; cif->interlaced_enable = true; cif->interlaced_offset = channel->width; cif->interlaced_counts = 0; cif->interlaced_buffer = 0; channel->height /= 2; - VEHICLE_DG("do denterlaced.\n"); + VEHICLE_INFO("do denterlaced.\n"); } channel->data_type = get_data_type(cfg->mbus_code, @@ -3930,7 +3955,7 @@ static int vehicle_cif_next_buffer(struct vehicle_cif *cif, u32 frame_ready, int static unsigned long temp_y_addr, temp_uv_addr; int commit_buf = 0; struct vehicle_rkcif_dummy_buffer *dummy_buf = &cif->dummy_buf; - + u32 frm_num_reg, frame_id = 0; VEHICLE_DG("@%s, enter, mipi_id(%d)\n", __func__, mipi_id); if ((frame_ready > 1) || (cif->cif_cfg.buf_num < 2) || @@ -3946,6 +3971,10 @@ static int vehicle_cif_next_buffer(struct vehicle_cif *cif, u32 frame_ready, int frm0_addr_uv = get_reg_index_of_frm0_uv_addr(mipi_id); frm1_addr_y = get_reg_index_of_frm1_y_addr(mipi_id); frm1_addr_uv = get_reg_index_of_frm1_uv_addr(mipi_id); + frm_num_reg = get_reg_index_of_frm_num(mipi_id); + frame_id = rkcif_read_reg(cif, frm_num_reg); + VEHICLE_DG("@%s, frm_num_reg(0x%x), frame_id:0x%x\n", __func__, + frm_num_reg, frame_id); } else { frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(mipi_id); frm0_addr_uv = get_dvp_reg_index_of_frm0_uv_addr(mipi_id); @@ -3979,10 +4008,11 @@ static int vehicle_cif_next_buffer(struct vehicle_cif *cif, u32 frame_ready, int uv_addr = temp_uv_addr; commit_buf = 0; } else { - if ((cif->interlaced_counts % 2) == 0) { + if ((frame_id != 0 && (frame_id & 0xffff) % 2 == 0) || + (frame_id == 0 && (cif->interlaced_counts % 2 == 0))) { temp_y_addr = vehicle_flinger_request_cif_buffer(); if (temp_y_addr == 0) { - VEHICLE_INFO("%s,warnning request buffer failed\n", __func__); + VEHICLE_DGERR("%s,warnning request buffer failed\n", __func__); spin_unlock(&cif->vbq_lock); return -1; } @@ -3995,6 +4025,11 @@ static int vehicle_cif_next_buffer(struct vehicle_cif *cif, u32 frame_ready, int //uv_addr = temp_uv_addr; uv_addr = temp_uv_addr + cif->interlaced_offset; commit_buf = 0; //even & odd field add + if (temp_y_addr == 0) { + VEHICLE_DGERR("%s,warnning temp_y_addr is NULL!\n", __func__); + spin_unlock(&cif->vbq_lock); + return -1; + } } WARN_ON(y_addr == cif->interlaced_offset); WARN_ON(uv_addr == cif->interlaced_offset); diff --git a/drivers/video/rockchip/vehicle/vehicle_flinger.c b/drivers/video/rockchip/vehicle/vehicle_flinger.c index 5fd279559f0f..ef5c605c4c4d 100644 --- a/drivers/video/rockchip/vehicle/vehicle_flinger.c +++ b/drivers/video/rockchip/vehicle/vehicle_flinger.c @@ -46,7 +46,6 @@ static int vehicle_dump_cif; static int vehicle_dump_rga; static int vehicle_dump_vop; -static bool nv12_display = true; enum force_value { FORCE_WIDTH = 1920, @@ -662,7 +661,10 @@ static int rk_flinger_rga_scaler(struct flinger *flinger, rga_request.rotate_mode = 0; rga_request.sina = 0; rga_request.cosa = 0; - rga_request.yuv2rgb_mode = 0x1 << 0; // limit range + + rga_request.yuv2rgb_mode = 0x0 << 0; // yuvtoyuv config 0 + /* yuv to rgb color space transform if need */ + //rga_request.yuv2rgb_mode = 0x1 << 0; // limit range //rga_request.yuv2rgb_mode = 0x2 << 0; // full range rga_request.src.act_w = src_buffer->src.w; @@ -685,7 +687,7 @@ static int rk_flinger_rga_scaler(struct flinger *flinger, rga_request.dst.yrgb_addr = dst_buffer->fd; rga_request.dst.uv_addr = 0; rga_request.dst.v_addr = 0; - rga_request.dst.format = RGA_FORMAT_RGBX_8888; + rga_request.dst.format = RGA_FORMAT_YCrCb_420_SP; rga_request.scale_mode = 1; @@ -1294,20 +1296,12 @@ try_again: VEHICLE_DG("it is ypbpr signal\n"); iep_buffer = &(flg->target_buffer[NUM_TARGET_BUFFERS - 1]); iep_buffer->state = ACQUIRE; - //scaler by rga for rgbx8888/rgb888/rgb565 display - if (!nv12_display) { - rk_flinger_rga_render(flg, src_buffer, iep_buffer); - src_buffer->state = FREE; - rk_flinger_rga_scaler(flg, iep_buffer, dst_buffer); - iep_buffer->state = FREE; - rk_flinger_vop_show(flg, dst_buffer); - } else { - rk_flinger_rga_render(flg, src_buffer, dst_buffer); - src_buffer->state = FREE; - rk_flinger_vop_show(flg, dst_buffer); - // rk_flinger_vop_show(flg, src_buffer); - } - + //scaler by rga to force widthxheight display + rk_flinger_rga_render(flg, src_buffer, iep_buffer); + src_buffer->state = FREE; + rk_flinger_rga_scaler(flg, iep_buffer, dst_buffer); + iep_buffer->state = FREE; + rk_flinger_vop_show(flg, dst_buffer); for (i = 0; i < NUM_TARGET_BUFFERS; i++) { buffer = &(flinger->target_buffer[i]); if (buffer->state == DISPLAY) @@ -1475,9 +1469,8 @@ unsigned long vehicle_flinger_request_cif_buffer(void) int i; src_buffer = NULL; - found = last_src_index + 1; for (i = 1; i < NUM_SOURCE_BUFFERS; i++) { - found = (found + i) % NUM_SOURCE_BUFFERS; + found = (last_src_index + i) % NUM_SOURCE_BUFFERS; VEHICLE_DG("%s,flg->source_buffer[%d].state(%d)", __func__, found, flg->source_buffer[found].state); if (flg->source_buffer[found].state == FREE) { diff --git a/include/linux/rfkill-wlan.h b/include/linux/rfkill-wlan.h index 431e71a7a844..c1987c316794 100644 --- a/include/linux/rfkill-wlan.h +++ b/include/linux/rfkill-wlan.h @@ -46,7 +46,14 @@ struct rksdmmc_gpio_wifi_moudle { struct clk *ext_clk; }; +#if IS_REACHABLE(CONFIG_RFKILL_RK) int rfkill_get_wifi_power_state(int *power); +#else +static inline int rfkill_get_wifi_power_state(int *power) +{ + return -1; +} +#endif void *rockchip_mem_prealloc(int section, unsigned long size); int rfkill_set_wifi_bt_power(int on); int rockchip_wifi_power(int on); diff --git a/include/soc/rockchip/rockchip_dmc.h b/include/soc/rockchip/rockchip_dmc.h index 882aa268ac85..44a976bad019 100644 --- a/include/soc/rockchip/rockchip_dmc.h +++ b/include/soc/rockchip/rockchip_dmc.h @@ -51,6 +51,7 @@ struct dmcfreq_common_info { struct freq_map_table *vop_frame_bw_tbl; struct rl_map_table *vop_pn_rl_tbl; struct delayed_work msch_rl_work; + unsigned long vop_4k_rate; unsigned long vop_req_rate; unsigned int read_latency; unsigned int auto_freq_en; @@ -62,6 +63,7 @@ struct dmcfreq_vop_info { unsigned int line_bw_mbyte; unsigned int frame_bw_mbyte; unsigned int plane_num; + unsigned int plane_num_4k; }; #if IS_REACHABLE(CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ) diff --git a/include/soc/rockchip/rockchip_iommu.h b/include/soc/rockchip/rockchip_iommu.h index bb86f5a1c26b..b3086c0f0617 100644 --- a/include/soc/rockchip/rockchip_iommu.h +++ b/include/soc/rockchip/rockchip_iommu.h @@ -35,7 +35,7 @@ struct third_iommu_ops_wrap { int (*probe)(struct platform_device *pdev); }; -#if IS_ENABLED(CONFIG_ROCKCHIP_IOMMU) +#if IS_REACHABLE(CONFIG_ROCKCHIP_IOMMU) int rockchip_iommu_enable(struct device *dev); int rockchip_iommu_disable(struct device *dev); int rockchip_pagefault_done(struct device *master_dev); diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig index 389aabe45a8c..04db3e88223f 100644 --- a/sound/soc/rockchip/Kconfig +++ b/sound/soc/rockchip/Kconfig @@ -40,6 +40,13 @@ config SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES Say Y or M if you want to add support for TDM Multi Lanes based on I2S_TDM controller. +config SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES + bool "Rockchip TDM Multi Lanes" + depends on SND_SOC_ROCKCHIP_I2S_TDM + help + Say Y or M if you want to add support for TDM Multi Lanes + based on I2S_TDM controller. + config SND_SOC_ROCKCHIP_MULTI_DAIS tristate "Rockchip Multi-DAIS Device Driver" depends on HAVE_CLK && SND_SOC_ROCKCHIP diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c index c7f5c562cb7c..72e11d794577 100644 --- a/sound/soc/rockchip/rockchip_i2s.c +++ b/sound/soc/rockchip/rockchip_i2s.c @@ -409,6 +409,7 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream, val |= I2S_TXCR_VDW(24); break; case SNDRV_PCM_FORMAT_S32_LE: + case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE: val |= I2S_TXCR_VDW(32); break; default: @@ -837,7 +838,8 @@ static int rockchip_i2s_init_dai(struct rk_i2s_dev *i2s, struct resource *res, SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | - SNDRV_PCM_FMTBIT_S32_LE; + SNDRV_PCM_FMTBIT_S32_LE | + SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE; i2s->playback_dma_data.addr = res->start + I2S_TXDR; i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; @@ -858,7 +860,8 @@ static int rockchip_i2s_init_dai(struct rk_i2s_dev *i2s, struct resource *res, SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | - SNDRV_PCM_FMTBIT_S32_LE; + SNDRV_PCM_FMTBIT_S32_LE | + SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE; i2s->capture_dma_data.addr = res->start + I2S_RXDR; i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; diff --git a/sound/soc/rockchip/rockchip_pdm.c b/sound/soc/rockchip/rockchip_pdm.c index d2f903f767ed..e71b6adc74df 100644 --- a/sound/soc/rockchip/rockchip_pdm.c +++ b/sound/soc/rockchip/rockchip_pdm.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -48,6 +49,8 @@ struct rk_pdm_dev { struct regmap *regmap; struct snd_dmaengine_dai_dma_data capture_dma_data; struct reset_control *reset; + struct pinctrl *pinctrl; + struct pinctrl_state *clk_state; unsigned int start_delay_ms; unsigned int filter_delay_ms; enum rk_pdm_version version; @@ -724,6 +727,31 @@ static const struct snd_soc_component_driver rockchip_pdm_component = { .legacy_dai_naming = 1, }; +static int rockchip_pdm_pinctrl_select_clk_state(struct device *dev) +{ + struct rk_pdm_dev *pdm = dev_get_drvdata(dev); + + if (IS_ERR_OR_NULL(pdm->pinctrl) || !pdm->clk_state) + return 0; + + /* + * A necessary delay to make sure the correct + * frac div has been applied when resume from + * power down. + */ + udelay(10); + + /* + * Must disable the clk to avoid clk glitch + * when pinctrl switch from gpio to pdm clk. + */ + clk_disable_unprepare(pdm->clk); + pinctrl_select_state(pdm->pinctrl, pdm->clk_state); + clk_prepare_enable(pdm->clk); + + return 0; +} + static int rockchip_pdm_runtime_suspend(struct device *dev) { struct rk_pdm_dev *pdm = dev_get_drvdata(dev); @@ -732,6 +760,8 @@ static int rockchip_pdm_runtime_suspend(struct device *dev) clk_disable_unprepare(pdm->clk); clk_disable_unprepare(pdm->hclk); + pinctrl_pm_select_idle_state(dev); + return 0; } @@ -756,6 +786,8 @@ static int rockchip_pdm_runtime_resume(struct device *dev) rockchip_pdm_rxctrl(pdm, 0); + rockchip_pdm_pinctrl_select_clk_state(dev); + return 0; err_regmap: @@ -937,6 +969,15 @@ static int rockchip_pdm_probe(struct platform_device *pdev) pdm->dev = &pdev->dev; dev_set_drvdata(&pdev->dev, pdm); + pdm->pinctrl = devm_pinctrl_get(&pdev->dev); + if (!IS_ERR_OR_NULL(pdm->pinctrl)) { + pdm->clk_state = pinctrl_lookup_state(pdm->pinctrl, "clk"); + if (IS_ERR(pdm->clk_state)) { + pdm->clk_state = NULL; + dev_dbg(pdm->dev, "Have no clk pinctrl state\n"); + } + } + pdm->start_delay_ms = PDM_START_DELAY_MS_DEFAULT; pdm->filter_delay_ms = PDM_FILTER_DELAY_MS_MIN; @@ -997,6 +1038,8 @@ static int rockchip_pdm_probe(struct platform_device *pdev) goto err_suspend; } + clk_disable_unprepare(pdm->hclk); + return 0; err_suspend: @@ -1012,15 +1055,10 @@ err_pm_disable: static int rockchip_pdm_remove(struct platform_device *pdev) { - struct rk_pdm_dev *pdm = dev_get_drvdata(&pdev->dev); - pm_runtime_disable(&pdev->dev); if (!pm_runtime_status_suspended(&pdev->dev)) rockchip_pdm_runtime_suspend(&pdev->dev); - clk_disable_unprepare(pdm->clk); - clk_disable_unprepare(pdm->hclk); - return 0; }