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ASoC: rockchip: sai: Fix mclk rate check

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Should compare to mclk_req rate, and also increase delta
from 1 Hz to 5 Hz.

Fixes: bca24656b6 ("ASoC: rockchip: sai: Allow mclk shift around 1 Hz")

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I7906c21e670c1dd7f105c025e110af61cbd56299
This commit is contained in:
Sugar Zhang
2023-10-12 10:58:41 +08:00
committed by Tao Huang
parent adf9ddf934
commit 1831ca1cdc
1 changed files with 8 additions and 7 deletions
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15
sound/soc/rockchip/rockchip_sai.c
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@@ -23,7 +23,7 @@
#define DRV_NAME "rockchip-sai" #define DRV_NAME "rockchip-sai"
#define CLK_SHIFT_RATE_HZ_MAX 1 /* 1 Hz */ #define CLK_SHIFT_RATE_HZ_MAX 5
#define FW_RATIO_MAX 8 #define FW_RATIO_MAX 8
#define FW_RATIO_MIN 1 #define FW_RATIO_MIN 1
#define MAXBURST_PER_FIFO 8 #define MAXBURST_PER_FIFO 8
@@ -423,7 +423,7 @@ static int rockchip_sai_hw_params(struct snd_pcm_substream *substream,
{ {
struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
struct snd_dmaengine_dai_dma_data *dma_data; struct snd_dmaengine_dai_dma_data *dma_data;
unsigned int mclk_rate, bclk_rate, div_bclk; unsigned int mclk_rate, mclk_req_rate, bclk_rate, div_bclk;
unsigned int ch_per_lane, lanes, slot_width; unsigned int ch_per_lane, lanes, slot_width;
unsigned int val, fscr, reg; unsigned int val, fscr, reg;
@@ -498,15 +498,16 @@ static int rockchip_sai_hw_params(struct snd_pcm_substream *substream,
if (sai->is_clk_auto) if (sai->is_clk_auto)
clk_set_rate(sai->mclk, bclk_rate); clk_set_rate(sai->mclk, bclk_rate);
mclk_rate = clk_get_rate(sai->mclk); mclk_rate = clk_get_rate(sai->mclk);
if (mclk_rate < bclk_rate - CLK_SHIFT_RATE_HZ_MAX || div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
mclk_rate > bclk_rate + CLK_SHIFT_RATE_HZ_MAX) { mclk_req_rate = bclk_rate * div_bclk;
if (mclk_rate < mclk_req_rate - CLK_SHIFT_RATE_HZ_MAX ||
mclk_rate > mclk_req_rate + CLK_SHIFT_RATE_HZ_MAX) {
dev_err(sai->dev, "Mismatch mclk: %u, expected %u (+/- %dHz)\n", dev_err(sai->dev, "Mismatch mclk: %u, expected %u (+/- %dHz)\n",
mclk_rate, bclk_rate, CLK_SHIFT_RATE_HZ_MAX); mclk_rate, mclk_req_rate, CLK_SHIFT_RATE_HZ_MAX);
return -EINVAL; return -EINVAL;
} }
div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK, regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK,
SAI_CKR_MDIV(div_bclk)); SAI_CKR_MDIV(div_bclk));
} }