diff --git a/arch/arm64/boot/dts/amlogic/axg_a113d_skt.dts b/arch/arm64/boot/dts/amlogic/axg_a113d_skt.dts
index 9a0d0afd134e..23484f011e2a 100644
--- a/arch/arm64/boot/dts/amlogic/axg_a113d_skt.dts
+++ b/arch/arm64/boot/dts/amlogic/axg_a113d_skt.dts
@@ -147,6 +147,22 @@
 		};
 	};
 
+	ethmac: ethernet@0xff3f0000 {
+			compatible = "amlogic, gxbb-eth-dwmac";
+			status = "disable";
+			reg = <0x0 0xff3f0000 0x0 0x10000
+			0x0 0xff634540 0x0 0x8>;
+			interrupts = <0 8 1>;
+			pinctrl-names = "external_eth_pins";
+			pinctrl-0 = <&external_eth_pins>;
+			mc_val_internal_phy = <0x1800>;
+			mc_val_external_phy = <0x1621>;
+			interrupt-names = "macirq";
+			clocks = <&clkc CLKID_ETH_CORE>;
+			clock-names = "ethclk81";
+			internal_phy=<0>;
+	};
+
 	dwc3: dwc3@ff500000 {
 		compatible = "synopsys, dwc3";
 		status = "okay";
diff --git a/arch/arm64/boot/dts/amlogic/axg_s400.dts b/arch/arm64/boot/dts/amlogic/axg_s400.dts
index efad1170720d..341d19f24b28 100644
--- a/arch/arm64/boot/dts/amlogic/axg_s400.dts
+++ b/arch/arm64/boot/dts/amlogic/axg_s400.dts
@@ -144,6 +144,21 @@
 	};
 
 
+	ethmac: ethernet@0xff3f0000 {
+			compatible = "amlogic, gxbb-eth-dwmac";
+			reg = <0x0 0xff3f0000 0x0 0x10000
+			0x0 0xff634540 0x0 0x8>;
+			interrupts = <0 8 1>;
+			pinctrl-names = "external_eth_pins";
+			pinctrl-0 = <&external_eth_pins>;
+			mc_val_internal_phy = <0x1800>;
+			mc_val_external_phy = <0x1621>;
+			interrupt-names = "macirq";
+			clocks = <&clkc CLKID_ETH_CORE>;
+			clock-names = "ethclk81";
+			internal_phy=<0>;
+	};
+
 	dwc3: dwc3@ff500000 {
 		compatible = "synopsys, dwc3";
 		status = "okay";
diff --git a/arch/arm64/boot/dts/amlogic/axg_s420.dts b/arch/arm64/boot/dts/amlogic/axg_s420.dts
index 1294d558a1ce..85b774b70220 100644
--- a/arch/arm64/boot/dts/amlogic/axg_s420.dts
+++ b/arch/arm64/boot/dts/amlogic/axg_s420.dts
@@ -143,7 +143,20 @@
 			};
 		};
 	};
-
+	ethmac: ethernet@0xff3f0000 {
+			compatible = "amlogic, gxbb-eth-dwmac";
+			reg = <0x0 0xff3f0000 0x0 0x10000
+			0x0 0xff634540 0x0 0x8>;
+			interrupts = <0 8 1>;
+			pinctrl-names = "external_eth_pins";
+			pinctrl-0 = <&external_eth_pins>;
+			mc_val_internal_phy = <0x1800>;
+			mc_val_external_phy = <0x1621>;
+			interrupt-names = "macirq";
+			clocks = <&clkc CLKID_ETH_CORE>;
+			clock-names = "ethclk81";
+			internal_phy=<0>;
+	};
 	dwc3: dwc3@ff500000 {
 		compatible = "synopsys, dwc3";
 		status = "okay";
diff --git a/arch/arm64/boot/dts/amlogic/mesonaxg.dtsi b/arch/arm64/boot/dts/amlogic/mesonaxg.dtsi
index f0b81a95711e..e13e4a46b7ba 100644
--- a/arch/arm64/boot/dts/amlogic/mesonaxg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/mesonaxg.dtsi
@@ -526,6 +526,25 @@
 }; /* end of pinctrl_aobus */
 
 &pinctrl_periphs {
+	external_eth_pins:external_eth_pins {
+		mux {
+			groups = "GPIOY_0",
+				"GPIOY_1",
+				"GPIOY_2",
+				"GPIOY_3",
+				"GPIOY_4",
+				"GPIOY_5",
+				"GPIOY_6",
+				"GPIOY_7",
+				"GPIOY_8",
+				"GPIOY_9",
+				"GPIOY_10",
+				"GPIOY_11",
+				"GPIOY_12",
+				"GPIOY_13";
+			function = "eth";
+		};
+	};
 	ao_b_uart_pins:ao_b_uart {
 		mux {
 				pins = "GPIOZ_8",
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c
index 624f01c2f31c..d9bbcef62183 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c
@@ -34,6 +34,9 @@ struct meson_dwmac {
 
 static void meson6_dwmac_fix_mac_speed(void *priv, unsigned int speed)
 {
+#ifdef CONFIG_AMLOGIC_ETH_PRIVE
+
+#else
 	struct meson_dwmac *dwmac = priv;
 	unsigned int val;
 #ifdef CONFIG_AMLOGIC_ETH_PRIVE
@@ -51,6 +54,7 @@ static void meson6_dwmac_fix_mac_speed(void *priv, unsigned int speed)
 	}
 
 	writel(val, dwmac->reg);
+#endif
 }
 
 #ifdef CONFIG_AMLOGIC_ETH_PRIVE
@@ -91,11 +95,14 @@ static void __iomem *network_interface_setup(struct platform_device *pdev)
 	pr_debug("REG0:REG1 = %p :%p\n", PREG_ETH_REG0, PREG_ETH_REG1);
 
 	if (!of_property_read_u32(np, "internal_phy", &internal_phy)) {
+		res = NULL;
 		res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+		if (res) {
 		addr = devm_ioremap_resource(dev, res);
 		PREG_ETH_REG2 = addr;
 		PREG_ETH_REG3 = addr + 4;
 		PREG_ETH_REG4 = addr + 8;
+		}
 		if (internal_phy == 1) {
 			pr_debug("internal phy\n");
 			/* Get mec mode & ting value  set it in cbus2050 */
@@ -104,6 +111,7 @@ static void __iomem *network_interface_setup(struct platform_device *pdev)
 			} else {
 				writel(mc_val, PREG_ETH_REG0);
 			}
+			if (res) {
 			writel(ETH_REG2_REVERSED | INTERNAL_PHY_ID,
 			       PREG_ETH_REG2);
 			writel(PHY_ENABLE | USE_PHY_IP | CLK_IN_EN |
@@ -111,6 +119,7 @@ static void __iomem *network_interface_setup(struct platform_device *pdev)
 					ETH_REG3_19_RESVERD	| CFG_PHY_ADDR |
 					CFG_MODE | CFG_EN_HIGH |
 					ETH_REG3_2_RESERVED, PREG_ETH_REG3);
+			}
 			pin_ctl = devm_pinctrl_get_select
 				(&pdev->dev, "internal_eth_pins");
 		} else {
@@ -120,11 +129,13 @@ static void __iomem *network_interface_setup(struct platform_device *pdev)
 				writel(mc_val, PREG_ETH_REG0);
 			if (!of_property_read_u32(np, "cali_val", &cali_val))
 				writel(cali_val, PREG_ETH_REG1);
+			if (res) {
 			writel(ETH_REG2_REVERSED | INTERNAL_PHY_ID,
 			       PREG_ETH_REG2);
 			writel(CLK_IN_EN | ETH_REG3_19_RESVERD	|
 					CFG_PHY_ADDR | CFG_MODE | CFG_EN_HIGH |
 					ETH_REG3_2_RESERVED, PREG_ETH_REG3);
+			}
 			/* pull reset pin for resetting phy  */
 			gdesc = gpiod_get(&pdev->dev, "rst_pin",
 					  GPIOD_FLAGS_BIT_DIR_OUT);