diff --git a/drivers/phy/rockchip/phy-rockchip-dp.c b/drivers/phy/rockchip/phy-rockchip-dp.c
index f1c59f81670d..3f77ecb4a082 100644
--- a/drivers/phy/rockchip/phy-rockchip-dp.c
+++ b/drivers/phy/rockchip/phy-rockchip-dp.c
@@ -10,6 +10,7 @@
  */
 
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/mfd/syscon.h>
 #include <linux/module.h>
 #include <linux/of.h>
@@ -38,7 +39,8 @@ static int rockchip_dp_phy_power_on(struct phy *phy)
 	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
 	const struct rockchip_dp_phy_data *data = dp->data;
 
-	clk_prepare_enable(dp->phy_24m);
+	if (!__clk_is_enabled(dp->phy_24m))
+		clk_prepare_enable(dp->phy_24m);
 
 	if (dp->rst) {
 		/* EDP 24m clock domain software reset */
@@ -61,7 +63,8 @@ static int rockchip_dp_phy_power_off(struct phy *phy)
 	regmap_write(dp->grf, data->grf_reg_offset,
 		     BIT(data->iddq_shift) | BIT(16 + data->iddq_shift));
 
-	clk_disable_unprepare(dp->phy_24m);
+	if (__clk_is_enabled(dp->phy_24m))
+		clk_disable_unprepare(dp->phy_24m);
 
 	return 0;
 }
@@ -107,6 +110,12 @@ static int rockchip_dp_phy_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	ret = clk_prepare_enable(dp->phy_24m);
+	if (ret) {
+		dev_err(dev, "failed to enable phy 24m clock: %d\n", ret);
+		return ret;
+	}
+
 	dp->rst = devm_reset_control_get_optional(dev, "edp_24m");
 	if (IS_ERR(dp->rst)) {
 		ret = PTR_ERR(dp->rst);