From 1a20aa562163677d6f3f27d1f2cd17e957bdf702 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Thu, 12 Nov 2020 15:28:40 +0800 Subject: [PATCH] clk: rockchip: rk3568: fix up the pciephy_ref setting rate error Pmucru updates missing parts of the TRM. Signed-off-by: Elaine Zhang Change-Id: I8fdd5d2b1feed2ab40e2b00f77a30686df56dd96 --- drivers/clk/rockchip/clk-rk3568.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index eeb1f8e47e40..4dcb8b104980 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -1553,26 +1553,26 @@ static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = { RK3568_PMU_CLKGATE_CON(2), 6, GFLAGS), MUX(CLK_WIFI, "clk_wifi", clk_wifi_p, CLK_SET_RATE_PARENT, RK3568_PMU_CLKSEL_CON(8), 15, 1, MFLAGS), - COMPOSITE_NOMUX(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", "ppll", 0, + COMPOSITE_NOMUX(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", "ppll_ph0", 0, RK3568_PMU_CLKSEL_CON(9), 0, 3, DFLAGS, RK3568_PMU_CLKGATE_CON(2), 7, GFLAGS), GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 8, GFLAGS), - MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref", clk_pciephy0_ref_p, 0, + MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref", clk_pciephy0_ref_p, CLK_SET_RATE_PARENT, RK3568_PMU_CLKSEL_CON(9), 3, 1, MFLAGS), - COMPOSITE_NOMUX(CLK_PCIEPHY1_DIV, "clk_pciephy1_div", "ppll", 0, + COMPOSITE_NOMUX(CLK_PCIEPHY1_DIV, "clk_pciephy1_div", "ppll_ph0", 0, RK3568_PMU_CLKSEL_CON(9), 4, 3, DFLAGS, RK3568_PMU_CLKGATE_CON(2), 9, GFLAGS), GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 10, GFLAGS), - MUX(CLK_PCIEPHY1_REF, "clk_pciephy1_ref", clk_pciephy1_ref_p, 0, + MUX(CLK_PCIEPHY1_REF, "clk_pciephy1_ref", clk_pciephy1_ref_p, CLK_SET_RATE_PARENT, RK3568_PMU_CLKSEL_CON(9), 7, 1, MFLAGS), - COMPOSITE_NOMUX(CLK_PCIEPHY2_DIV, "clk_pciephy2_div", "ppll", 0, + COMPOSITE_NOMUX(CLK_PCIEPHY2_DIV, "clk_pciephy2_div", "ppll_ph0", 0, RK3568_PMU_CLKSEL_CON(9), 8, 3, DFLAGS, RK3568_PMU_CLKGATE_CON(2), 11, GFLAGS), GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 12, GFLAGS), - MUX(CLK_PCIEPHY2_REF, "clk_pciephy2_ref", clk_pciephy2_ref_p, 0, + MUX(CLK_PCIEPHY2_REF, "clk_pciephy2_ref", clk_pciephy2_ref_p, CLK_SET_RATE_PARENT, RK3568_PMU_CLKSEL_CON(9), 11, 1, MFLAGS), GATE(CLK_PCIE30PHY_REF_M, "clk_pcie30phy_ref_m", "ppll_ph0", 0, RK3568_PMU_CLKGATE_CON(2), 13, GFLAGS),