From 1a65cbed5a6fe68b341006bb8eb3c8e7871711f5 Mon Sep 17 00:00:00 2001 From: Chris Date: Wed, 24 Mar 2021 16:49:15 +0900 Subject: [PATCH] Revert "sound/soc/auge: fix clock for DD+" This reverts commit 3dabbe6096544135e563dcf079348151d949be57. Change-Id: I5384ea8672fabd68697ade9f97767e8d7259c765 --- sound/soc/amlogic/common/spdif_info.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/sound/soc/amlogic/common/spdif_info.c b/sound/soc/amlogic/common/spdif_info.c index efc1f46c14cd..97edbf81afa9 100644 --- a/sound/soc/amlogic/common/spdif_info.c +++ b/sound/soc/amlogic/common/spdif_info.c @@ -43,7 +43,8 @@ bool spdif_is_4x_clk(void) { bool is_4x = false; - if (IEC958_mode_codec == 7 || IEC958_mode_codec == 8) { + if (IEC958_mode_codec == 4 || IEC958_mode_codec == 5 || + IEC958_mode_codec == 7 || IEC958_mode_codec == 8) { is_4x = true; } @@ -84,6 +85,8 @@ void spdif_get_channel_status_info( } } else if (IEC958_mode_codec == 8 || IEC958_mode_codec == 7) { /* DTS-HD MA, TrueHD */ + chsts->chstat0_l = 0x8206; + chsts->chstat0_r = 0x8206; chsts->chstat1_l = 0x900; chsts->chstat1_r = 0x900; } else {