From 1aae5d1eedc447bb28cf7dfe8b24c8deb7542350 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 17 Apr 2019 11:35:24 +0800 Subject: [PATCH] clk: rockchip: rk3308: Remove the reduplicative dclk_vop_frac Fixes: 0ee785bb30eca ("clk: rockchip: Add supprot to limit input rate for fractional divider") Change-Id: Ifd387f4dd2cdddedda4cb65f36806260eb3e03ef Signed-off-by: Finley Xiao --- drivers/clk/rockchip/clk-rk3308.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3308.c b/drivers/clk/rockchip/clk-rk3308.c index 1e96895b514c..40966854ef1d 100644 --- a/drivers/clk/rockchip/clk-rk3308.c +++ b/drivers/clk/rockchip/clk-rk3308.c @@ -465,10 +465,6 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = { COMPOSITE(0, "dclk_vop_src", mux_dpll_vpll0_vpll1_p, 0, RK3308_CLKSEL_CON(8), 10, 2, MFLAGS, 0, 8, DFLAGS, RK3308_CLKGATE_CON(1), 6, GFLAGS), - COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT, - RK3308_CLKSEL_CON(9), 0, - RK3308_CLKGATE_CON(1), 7, GFLAGS, - &rk3308_dclk_vop_fracmux, 0), GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0, RK3308_CLKGATE_CON(1), 8, GFLAGS),