From 1ba6338e229afa7f8d8f0edaafd8b07b24c10e87 Mon Sep 17 00:00:00 2001
From: Wyon Bi <bivvy.bi@rock-chips.com>
Date: Wed, 22 Sep 2021 15:02:19 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add edp0 node

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ie3bf343524a958bb78842941bcb47f9e3cbe2262
---
 arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 005ac0418009..39743a6bba8a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -356,6 +356,11 @@
 		reg = <0x0 0xfd5a6000 0x0 0x2000>;
 	};
 
+	vo1_grf: syscon@fd5a8000 {
+		compatible = "rockchip,rk3588-vo-grf", "syscon";
+		reg = <0x0 0xfd5a8000 0x0 0x100>;
+	};
+
 	usb_grf: syscon@fd5ac000 {
 		compatible = "rockchip,rk3588-usb-grf", "syscon";
 		reg = <0x0 0xfd5ac000 0x0 0x4000>;
@@ -452,7 +457,7 @@
 
 	hdptxphy0_grf: syscon@fd5e0000 {
 		compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
-		reg = <0x0 0xfd5e0000 0x0 0x80>;
+		reg = <0x0 0xfd5e0000 0x0 0x100>;
 	};
 
 	ioc: syscon@fd5f0000 {
@@ -1106,6 +1111,22 @@
 		status = "disabled";
 	};
 
+	edp0: edp@fdec0000 {
+		compatible = "rockchip,rk3588-edp";
+		reg = <0x0 0xfdec0000 0x0 0x1000>;
+		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>,
+			 <&cru CLK_EDP0_200M>;
+		clock-names = "dp", "pclk", "spdif";
+		resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>;
+		reset-names = "dp", "apb";
+		phys = <&hdptxphy0>;
+		phy-names = "dp";
+		power-domains = <&power RK3588_PD_VO1>;
+		rockchip,grf = <&vo1_grf>;
+		status = "disabled";
+	};
+
 	pcie2x1l1: pcie@fe180000 {
 		compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
 		#address-cells = <3>;