From 6c47657a381c5b065b9b43dc50d4570c4988c023 Mon Sep 17 00:00:00 2001 From: Yandong Lin Date: Tue, 14 Jan 2025 15:42:48 +0800 Subject: [PATCH 01/12] video: rockchip: mpp: Fix missing enable_irq in timeout work Fixes: 4938e4ee1b60 ("video: rockchip: mpp: optimize the schedule of enc/dec") Change-Id: I0942d94ba92b972e557301d83d1e7962a1b8ea13 Signed-off-by: Yandong Lin --- drivers/video/rockchip/mpp/mpp_common.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/video/rockchip/mpp/mpp_common.c b/drivers/video/rockchip/mpp/mpp_common.c index db93061f34b9..ab02cea09f17 100644 --- a/drivers/video/rockchip/mpp/mpp_common.c +++ b/drivers/video/rockchip/mpp/mpp_common.c @@ -550,7 +550,9 @@ static void mpp_task_timeout_work(struct work_struct *work_s) } disable_irq(mpp->irq); if (test_and_set_bit(TASK_STATE_HANDLE, &task->state)) { - mpp_err("task has been handled\n"); + mpp_err("session %d:%d task %d has been handled\n", + session->device_type, session->index, task->task_index); + enable_irq(mpp->irq); return; } mpp_err("session %d:%d task %d processing time out!\n", From 5bb84d62da000dce0be513110765d39bb877a6b3 Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Mon, 15 Jul 2024 16:14:01 +0800 Subject: [PATCH 02/12] clk: rockchip: add enc/isp pvtpll clk for rv1103b Signed-off-by: Liang Chen Change-Id: If2d8e1674e4eb1a9ac0c771561187a0177289572 --- drivers/clk/rockchip/clk-pvtpll.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/clk/rockchip/clk-pvtpll.c b/drivers/clk/rockchip/clk-pvtpll.c index 0900b6716a61..2f00296a4b66 100644 --- a/drivers/clk/rockchip/clk-pvtpll.c +++ b/drivers/clk/rockchip/clk-pvtpll.c @@ -114,6 +114,16 @@ static struct pvtpll_table rv1103b_core_pvtpll_table[] = { ROCKCHIP_PVTPLL(816000000, 1, 60), }; +static struct pvtpll_table rv1103b_enc_pvtpll_table[] = { + /* rate_hz, ring_se, length */ + ROCKCHIP_PVTPLL(500000000, 1, 100), +}; + +static struct pvtpll_table rv1103b_isp_pvtpll_table[] = { + /* rate_hz, ring_se, length */ + ROCKCHIP_PVTPLL(400000000, 1, 160), +}; + static struct pvtpll_table rv1103b_npu_pvtpll_table[] = { /* rate_hz, ring_se, length */ ROCKCHIP_PVTPLL(1000000000, 1, 12), @@ -428,6 +438,18 @@ static const struct rockchip_clock_pvtpll_info rv1103b_core_pvtpll_data = { .table = rv1103b_core_pvtpll_table, }; +static const struct rockchip_clock_pvtpll_info rv1103b_enc_pvtpll_data = { + .config = rv1103b_pvtpll_configs, + .table_size = ARRAY_SIZE(rv1103b_enc_pvtpll_table), + .table = rv1103b_enc_pvtpll_table, +}; + +static const struct rockchip_clock_pvtpll_info rv1103b_isp_pvtpll_data = { + .config = rv1103b_pvtpll_configs, + .table_size = ARRAY_SIZE(rv1103b_isp_pvtpll_table), + .table = rv1103b_isp_pvtpll_table, +}; + static const struct rockchip_clock_pvtpll_info rv1103b_npu_pvtpll_data = { .config = rv1103b_pvtpll_configs, .table_size = ARRAY_SIZE(rv1103b_npu_pvtpll_table), @@ -448,6 +470,14 @@ static const struct of_device_id rockchip_clock_pvtpll_match[] = { .compatible = "rockchip,rv1103b-core-pvtpll", .data = (void *)&rv1103b_core_pvtpll_data, }, + { + .compatible = "rockchip,rv1103b-enc-pvtpll", + .data = (void *)&rv1103b_enc_pvtpll_data, + }, + { + .compatible = "rockchip,rv1103b-isp-pvtpll", + .data = (void *)&rv1103b_isp_pvtpll_data, + }, { .compatible = "rockchip,rv1103b-npu-pvtpll", .data = (void *)&rv1103b_npu_pvtpll_data, From 14752da8e74d528dcff00f239f8ab3d8440a49ec Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Sat, 21 Dec 2024 11:02:25 +0800 Subject: [PATCH 03/12] clk: rockchip: clk-pvtpll: update pvtpll config for rv1103b Change-Id: Ie4512b8dad3279eed059f4bd5bbfe5c450d00351 Signed-off-by: Liang Chen --- drivers/clk/rockchip/clk-pvtpll.c | 40 ++++++++++++++++++++----------- 1 file changed, 26 insertions(+), 14 deletions(-) diff --git a/drivers/clk/rockchip/clk-pvtpll.c b/drivers/clk/rockchip/clk-pvtpll.c index 2f00296a4b66..b32302ecaf8f 100644 --- a/drivers/clk/rockchip/clk-pvtpll.c +++ b/drivers/clk/rockchip/clk-pvtpll.c @@ -30,6 +30,7 @@ #define RV1103B_GCK_RING_LEN_SEL_MASK 0x1ff #define RV1103B_GCK_RING_SEL_OFFSET 10 #define RV1103B_GCK_RING_SEL_MASK 0x07 +#define RV1103B_PVTPLL_MAX_LENGTH 0x1ff #define RK3506_GRF_CORE_PVTPLL_CON0_L 0x00 #define RK3506_GRF_CORE_PVTPLL_CON0_H 0x04 @@ -56,6 +57,7 @@ struct rockchip_clock_pvtpll_info { struct pvtpll_table *table; unsigned int jm_table_size; struct pvtpll_table *jm_table; + unsigned int pvtpll_adjust_factor; int (*config)(struct rockchip_clock_pvtpll *pvtpll, struct pvtpll_table *table); int (*pvtpll_volt_sel_adjust)(struct rockchip_clock_pvtpll *pvtpll, @@ -105,13 +107,13 @@ struct otp_opp_info { static struct pvtpll_table rv1103b_core_pvtpll_table[] = { /* rate_hz, ring_sel, length */ - ROCKCHIP_PVTPLL(1608000000, 1, 6), - ROCKCHIP_PVTPLL(1512000000, 1, 6), - ROCKCHIP_PVTPLL(1416000000, 1, 6), - ROCKCHIP_PVTPLL(1296000000, 1, 6), - ROCKCHIP_PVTPLL(1200000000, 1, 14), - ROCKCHIP_PVTPLL(1008000000, 1, 32), - ROCKCHIP_PVTPLL(816000000, 1, 60), + ROCKCHIP_PVTPLL_VOLT_SEL(1608000000, 1, 6, 7), + ROCKCHIP_PVTPLL_VOLT_SEL(1512000000, 1, 6, 6), + ROCKCHIP_PVTPLL_VOLT_SEL(1416000000, 1, 6, 6), + ROCKCHIP_PVTPLL_VOLT_SEL(1296000000, 1, 6, 5), + ROCKCHIP_PVTPLL_VOLT_SEL(1200000000, 1, 6, 3), + ROCKCHIP_PVTPLL_VOLT_SEL(1008000000, 1, 26, 3), + ROCKCHIP_PVTPLL_VOLT_SEL(816000000, 1, 50, 3), }; static struct pvtpll_table rv1103b_enc_pvtpll_table[] = { @@ -126,10 +128,10 @@ static struct pvtpll_table rv1103b_isp_pvtpll_table[] = { static struct pvtpll_table rv1103b_npu_pvtpll_table[] = { /* rate_hz, ring_se, length */ - ROCKCHIP_PVTPLL(1000000000, 1, 12), - ROCKCHIP_PVTPLL(900000000, 1, 12), - ROCKCHIP_PVTPLL(800000000, 1, 16), - ROCKCHIP_PVTPLL(700000000, 1, 36), + ROCKCHIP_PVTPLL_VOLT_SEL(1000000000, 1, 12, 7), + ROCKCHIP_PVTPLL_VOLT_SEL(900000000, 1, 12, 6), + ROCKCHIP_PVTPLL_VOLT_SEL(800000000, 1, 12, 4), + ROCKCHIP_PVTPLL_VOLT_SEL(700000000, 1, 32, 4), }; static struct pvtpll_table rk3506_core_pvtpll_table[] = { @@ -312,12 +314,13 @@ static int clock_pvtpll_regitstor(struct device *dev, pvtpll->pvtpll_out); } -static int rk3506_pvtpll_volt_sel_adjust(struct rockchip_clock_pvtpll *pvtpll, +static int pvtpll_volt_sel_adjust_linear(struct rockchip_clock_pvtpll *pvtpll, u32 clock_id, u32 volt_sel) { struct pvtpll_table *table = pvtpll->info->table; unsigned int size = pvtpll->info->table_size; + unsigned int factor = pvtpll->info->pvtpll_adjust_factor; uint32_t delta_len = 0; int i; @@ -325,10 +328,14 @@ static int rk3506_pvtpll_volt_sel_adjust(struct rockchip_clock_pvtpll *pvtpll, if (!table[i].volt_sel_thr) continue; if (volt_sel >= table[i].volt_sel_thr) { - delta_len = volt_sel - table[i].volt_sel_thr + 1; + delta_len = (volt_sel - table[i].volt_sel_thr + 1) * factor; table[i].length += delta_len; if (table[i].length > RK3506_PVTPLL_MAX_LENGTH) table[i].length = RK3506_PVTPLL_MAX_LENGTH; + + /* update new pvtpll config for current rate */ + if (table[i].rate == pvtpll->cur_rate) + pvtpll->info->config(pvtpll, table + i); } } @@ -436,6 +443,8 @@ static const struct rockchip_clock_pvtpll_info rv1103b_core_pvtpll_data = { .config = rv1103b_pvtpll_configs, .table_size = ARRAY_SIZE(rv1103b_core_pvtpll_table), .table = rv1103b_core_pvtpll_table, + .pvtpll_adjust_factor = 4, + .pvtpll_volt_sel_adjust = pvtpll_volt_sel_adjust_linear, }; static const struct rockchip_clock_pvtpll_info rv1103b_enc_pvtpll_data = { @@ -454,6 +463,8 @@ static const struct rockchip_clock_pvtpll_info rv1103b_npu_pvtpll_data = { .config = rv1103b_pvtpll_configs, .table_size = ARRAY_SIZE(rv1103b_npu_pvtpll_table), .table = rv1103b_npu_pvtpll_table, + .pvtpll_adjust_factor = 6, + .pvtpll_volt_sel_adjust = pvtpll_volt_sel_adjust_linear, }; static const struct rockchip_clock_pvtpll_info rk3506_core_pvtpll_data = { @@ -462,7 +473,8 @@ static const struct rockchip_clock_pvtpll_info rk3506_core_pvtpll_data = { .table = rk3506_core_pvtpll_table, .jm_table_size = ARRAY_SIZE(rk3506j_core_pvtpll_table), .jm_table = rk3506j_core_pvtpll_table, - .pvtpll_volt_sel_adjust = rk3506_pvtpll_volt_sel_adjust, + .pvtpll_adjust_factor = 1, + .pvtpll_volt_sel_adjust = pvtpll_volt_sel_adjust_linear, }; static const struct of_device_id rockchip_clock_pvtpll_match[] = { From 6757ebf6a809c00367617dbbfc9b55691a51f2f3 Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Mon, 13 Jan 2025 11:37:49 +0800 Subject: [PATCH 04/12] clk: rockchip: clk-pvtpll: calibrate pvtpll init frequency for rv1103b Change-Id: Ic15b4645a2c4caadce9b870bd2d8a7960688b66d Signed-off-by: Liang Chen --- drivers/clk/rockchip/clk-pvtpll.c | 107 +++++++++++++++++++++++++++++- 1 file changed, 106 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-pvtpll.c b/drivers/clk/rockchip/clk-pvtpll.c index b32302ecaf8f..860993008ed9 100644 --- a/drivers/clk/rockchip/clk-pvtpll.c +++ b/drivers/clk/rockchip/clk-pvtpll.c @@ -31,6 +31,7 @@ #define RV1103B_GCK_RING_SEL_OFFSET 10 #define RV1103B_GCK_RING_SEL_MASK 0x07 #define RV1103B_PVTPLL_MAX_LENGTH 0x1ff +#define RV1103B_PVTPLL_GCK_CNT_AVG 0x54 #define RK3506_GRF_CORE_PVTPLL_CON0_L 0x00 #define RK3506_GRF_CORE_PVTPLL_CON0_H 0x04 @@ -58,8 +59,11 @@ struct rockchip_clock_pvtpll_info { unsigned int jm_table_size; struct pvtpll_table *jm_table; unsigned int pvtpll_adjust_factor; + unsigned int calibrate_length_step; + unsigned int calibrate_freq_per_step; int (*config)(struct rockchip_clock_pvtpll *pvtpll, struct pvtpll_table *table); + int (*pvtpll_calibrate)(struct rockchip_clock_pvtpll *pvtpll); int (*pvtpll_volt_sel_adjust)(struct rockchip_clock_pvtpll *pvtpll, u32 clock_id, u32 volt_sel); @@ -76,6 +80,7 @@ struct rockchip_clock_pvtpll { struct clk *pvtpll_clk; struct clk *pvtpll_out; struct notifier_block pvtpll_nb; + struct delayed_work pvtpll_calibrate_work; unsigned long cur_rate; u32 pvtpll_clk_id; }; @@ -118,7 +123,7 @@ static struct pvtpll_table rv1103b_core_pvtpll_table[] = { static struct pvtpll_table rv1103b_enc_pvtpll_table[] = { /* rate_hz, ring_se, length */ - ROCKCHIP_PVTPLL(500000000, 1, 100), + ROCKCHIP_PVTPLL(500000000, 1, 80), }; static struct pvtpll_table rv1103b_isp_pvtpll_table[] = { @@ -242,6 +247,15 @@ static int rockchip_clock_pvtpll_set_rate(struct clk_hw *hw, if (!pvtpll) return 0; + /* + * The calibration is only for the init frequency of pvtpll on the platform + * which regulator is fixed, if the frequency will be change, we assume that + * dvfs is working, so just cancel the calibration work and use the pvtpll + * configuration from pvtpll_table, it will match the opp-table. + */ + if (pvtpll->info->pvtpll_calibrate) + cancel_delayed_work_sync(&pvtpll->pvtpll_calibrate_work); + table = rockchip_get_pvtpll_settings(pvtpll, rate); if (!table) return 0; @@ -439,18 +453,99 @@ static void rockchip_adjust_pvtpll_by_otp(struct device *dev, } } +static int rv1103b_pvtpll_calibrate(struct rockchip_clock_pvtpll *pvtpll) +{ + unsigned int rate, delta, length, length_ori, val, i = 0; + unsigned int length_step = pvtpll->info->calibrate_length_step; + unsigned int freq_per_step = pvtpll->info->calibrate_freq_per_step; + unsigned long target_rate = pvtpll->cur_rate / MHz; + int ret; + + ret = regmap_read(pvtpll->regmap, RV1103B_PVTPLL_GCK_CNT_AVG, &rate); + if (ret) + return ret; + + if (rate < target_rate) + return 0; + + /* delta < (6.25% * target_rate) */ + if ((rate - target_rate) < (target_rate >> 4)) + return 0; + + ret = regmap_read(pvtpll->regmap, RV1103B_PVTPLL_GCK_LEN, &val); + if (ret) + return ret; + length_ori = (val >> RV1103B_GCK_RING_LEN_SEL_OFFSET) & RV1103B_GCK_RING_LEN_SEL_MASK; + length = length_ori; + delta = rate - target_rate; + length += (delta / freq_per_step) * length_step; + val = HIWORD_UPDATE(length, RV1103B_GCK_RING_LEN_SEL_MASK, + RV1103B_GCK_RING_LEN_SEL_OFFSET); + ret = regmap_write(pvtpll->regmap, RV1103B_PVTPLL_GCK_LEN, val); + if (ret) + return ret; + usleep_range(2000, 2100); + ret = regmap_read(pvtpll->regmap, RV1103B_PVTPLL_GCK_CNT_AVG, &rate); + if (ret) + return ret; + + while ((rate < target_rate) || ((rate - target_rate) > (target_rate >> 4))) { + if (i++ > 20) + break; + + if (rate > target_rate) + length += length_step; + else + length -= length_step; + if (length < length_ori) + break; + + val = HIWORD_UPDATE(length, RV1103B_GCK_RING_LEN_SEL_MASK, + RV1103B_GCK_RING_LEN_SEL_OFFSET); + ret = regmap_write(pvtpll->regmap, RV1103B_PVTPLL_GCK_LEN, val); + if (ret) + return ret; + usleep_range(2000, 2100); + ret = regmap_read(pvtpll->regmap, RV1103B_PVTPLL_GCK_CNT_AVG, &rate); + if (ret) + return ret; + } + + return 0; +} + +static void rockchip_pvtpll_calibrate(struct work_struct *work) +{ + struct rockchip_clock_pvtpll *pvtpll; + int ret; + + pvtpll = container_of(work, struct rockchip_clock_pvtpll, pvtpll_calibrate_work.work); + + if (pvtpll->info->pvtpll_calibrate) { + ret = pvtpll->info->pvtpll_calibrate(pvtpll); + if (ret) + dev_warn(pvtpll->dev, "%s: calibrate error, ret %d\n", __func__, ret); + } +} + static const struct rockchip_clock_pvtpll_info rv1103b_core_pvtpll_data = { .config = rv1103b_pvtpll_configs, .table_size = ARRAY_SIZE(rv1103b_core_pvtpll_table), .table = rv1103b_core_pvtpll_table, .pvtpll_adjust_factor = 4, .pvtpll_volt_sel_adjust = pvtpll_volt_sel_adjust_linear, + .calibrate_length_step = 2, + .calibrate_freq_per_step = 30, + .pvtpll_calibrate = rv1103b_pvtpll_calibrate, }; static const struct rockchip_clock_pvtpll_info rv1103b_enc_pvtpll_data = { .config = rv1103b_pvtpll_configs, .table_size = ARRAY_SIZE(rv1103b_enc_pvtpll_table), .table = rv1103b_enc_pvtpll_table, + .calibrate_length_step = 8, + .calibrate_freq_per_step = 25, + .pvtpll_calibrate = rv1103b_pvtpll_calibrate, }; static const struct rockchip_clock_pvtpll_info rv1103b_isp_pvtpll_data = { @@ -465,6 +560,9 @@ static const struct rockchip_clock_pvtpll_info rv1103b_npu_pvtpll_data = { .table = rv1103b_npu_pvtpll_table, .pvtpll_adjust_factor = 6, .pvtpll_volt_sel_adjust = pvtpll_volt_sel_adjust_linear, + .calibrate_length_step = 4, + .calibrate_freq_per_step = 25, + .pvtpll_calibrate = rv1103b_pvtpll_calibrate, }; static const struct rockchip_clock_pvtpll_info rk3506_core_pvtpll_data = { @@ -522,7 +620,9 @@ static int rockchip_clock_pvtpll_probe(struct platform_device *pdev) if (IS_ERR(pvtpll->regmap)) return PTR_ERR(pvtpll->regmap); + pvtpll->dev = dev; pvtpll->pvtpll_clk_id = UINT_MAX; + INIT_DELAYED_WORK(&pvtpll->pvtpll_calibrate_work, rockchip_pvtpll_calibrate); error = of_parse_phandle_with_args(np, "clocks", "#clock-cells", 0, &clkspec); @@ -543,6 +643,11 @@ static int rockchip_clock_pvtpll_probe(struct platform_device *pdev) return error; } + if (pvtpll->info->pvtpll_calibrate) + queue_delayed_work(system_freezable_wq, + &pvtpll->pvtpll_calibrate_work, + 0); + mutex_lock(&pvtpll_list_mutex); list_add(&pvtpll->list_head, &rockchip_clock_pvtpll_list); mutex_unlock(&pvtpll_list_mutex); From b125e2d8c7a8ea6ccac868a20673c23f54ebc7cd Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Thu, 16 Jan 2025 09:31:13 +0800 Subject: [PATCH 05/12] pwm: rockchip: add mask check for 'v' in macro HIWORD_UPDATE(v, l, h) Change-Id: Iaeb5f6f070914f208fe30929a638a92145a5164c Signed-off-by: Damon Ding --- drivers/pwm/pwm-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c index 3acae9805b21..6246c5182fd2 100644 --- a/drivers/pwm/pwm-rockchip.c +++ b/drivers/pwm/pwm-rockchip.c @@ -73,7 +73,7 @@ /* * regs for pwm v4 */ -#define HIWORD_UPDATE(v, l, h) (((v) << (l)) | (GENMASK(h, l) << 16)) +#define HIWORD_UPDATE(v, l, h) ((((v) << (l)) & GENMASK((h), (l))) | (GENMASK(h, l) << 16)) /* VERSION_ID */ #define VERSION_ID 0x0 From dfaa59878dbe3a3a419be604285f82225a95981e Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Thu, 16 Jan 2025 09:17:04 +0800 Subject: [PATCH 06/12] pwm: rockchip: fix the scaler calculation in &rockchip_pwm_funcs.set_wave() If the pc->clk_rate is the same as config->clk_rate, the scaler should be set to 0. However, using the previous calculation method, the result would incorrectly be 1. Fixes: 1504b8ffcf37 ("pwm: rockchip: add dclk scale config for wave generator mode") Change-Id: I876f7f530ab841b485b8d7f139adcf825955a160 Signed-off-by: Damon Ding --- drivers/pwm/pwm-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c index 6246c5182fd2..441512796e2e 100644 --- a/drivers/pwm/pwm-rockchip.c +++ b/drivers/pwm/pwm-rockchip.c @@ -1652,7 +1652,7 @@ int rockchip_pwm_set_wave(struct pwm_device *pwm, struct rockchip_pwm_wave_confi return -EINVAL; } - pc->scaler = DIV_ROUND_CLOSEST_ULL(pc->clk_rate, config->clk_rate * 2); + pc->scaler = DIV_ROUND_CLOSEST_ULL(pc->clk_rate, config->clk_rate) / 2; if (pc->scaler > 256) { dev_err(chip->dev, "Unsupported scale factor %d(max: 512) for PWM%d\n", pc->scaler * 2, pc->channel_id); From 40da609adad5594500467331fe53c660d4ca3b87 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Thu, 16 Jan 2025 10:47:32 +0800 Subject: [PATCH 07/12] pwm: rockchip: disable unused interrupt function for wave generator In order to avoid unnecessary interrupt handing behaviors, disable the interrupt for the wave generator. Change-Id: Ib397c9814775ca968b77c435db57a5b1ed5df7c6 Signed-off-by: Damon Ding --- drivers/pwm/pwm-rockchip.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c index 441512796e2e..820d26e42cb1 100644 --- a/drivers/pwm/pwm-rockchip.c +++ b/drivers/pwm/pwm-rockchip.c @@ -1621,8 +1621,6 @@ static int rockchip_pwm_set_wave_v4(struct pwm_chip *chip, struct pwm_device *pw writel_relaxed(middle, pc->base + WAVE_MIDDLE); writel_relaxed(rpt, pc->base + RPT); - writel_relaxed(WAVE_MAX_INT_EN(config->enable) | WAVE_MIDDLE_INT_EN(config->enable), - pc->base + INT_EN); pc->wave_en = config->enable; From 6dc017e3b3884252e3ff24b2a18ed563cfb113fb Mon Sep 17 00:00:00 2001 From: William Wu Date: Wed, 15 Jan 2025 18:04:39 +0800 Subject: [PATCH 08/12] arm64: dts: rockchip: rk3576s-evb: Remove u2phy1 Change-Id: If003ebf9d2a28709416686f8454db81f4e5a5106 Signed-off-by: William Wu --- arch/arm64/boot/dts/rockchip/rk3576s-evb.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576s-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3576s-evb.dtsi index 4df3eacfaa49..d743c12c4b82 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576s-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576s-evb.dtsi @@ -805,10 +805,6 @@ status = "okay"; }; -&u2phy1 { - status = "okay"; -}; - &u2phy0_otg { status = "okay"; }; From b58bf56d91ef054d62c5cfc29c6e8f9a0b75e7a1 Mon Sep 17 00:00:00 2001 From: William Wu Date: Wed, 15 Jan 2025 18:08:05 +0800 Subject: [PATCH 09/12] arm64: dts: rockchip: rk3576s: Delete u2phy1 node Change-Id: Ifb7c3f22c4caa75093daab77347e907b15870095 Signed-off-by: William Wu --- arch/arm64/boot/dts/rockchip/rk3576s.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576s.dtsi b/arch/arm64/boot/dts/rockchip/rk3576s.dtsi index 4a19f63614b9..7389b5451347 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576s.dtsi @@ -63,4 +63,5 @@ /delete-node/ &sata1; /delete-node/ &usb_drd1_dwc3; /delete-node/ &u2phy1_otg; +/delete-node/ &u2phy1; /delete-node/ &vopl; From e625024f13d3cf4a651bba156ccc7ac7af8d8a03 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Mon, 13 Jan 2025 23:28:06 +0800 Subject: [PATCH 10/12] mtd: spinand: xtx: Support new devices XT26G12DWSIGA, XT26Q12DWSIGA, XT26G11DWSIGA, XT26Q14DWSIGA. Change-Id: I733172ed78a95f4d2129c98c9d2c6b92525bde4c Signed-off-by: Jon Lin --- drivers/mtd/nand/spi/xtx.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/mtd/nand/spi/xtx.c b/drivers/mtd/nand/spi/xtx.c index ee705de096c9..7c60987cf569 100644 --- a/drivers/mtd/nand/spi/xtx.c +++ b/drivers/mtd/nand/spi/xtx.c @@ -404,6 +404,42 @@ static const struct spinand_info xtx_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)), + SPINAND_INFO("XT26G12DWSIGA", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)), + SPINAND_INFO("XT26Q12DWSIGA", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x55), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)), + SPINAND_INFO("XT26G11DWSIGA", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)), + SPINAND_INFO("XT26Q14DWSIGA", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x56), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)), }; static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = { From ba3c36d8c259fd49601487e54d5e2771fb6afd01 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Mon, 16 Dec 2024 10:20:23 +0800 Subject: [PATCH 11/12] mtd: spinand: UNIM: Support new device UM19A0XISW UM19A0HISW, UM19A0LISW. Change-Id: I29baad2badf95ce2bd6daeb8819e99efb7e1d3fd Signed-off-by: Jon Lin --- drivers/mtd/nand/spi/unim.c | 43 +++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/mtd/nand/spi/unim.c b/drivers/mtd/nand/spi/unim.c index 094983974468..f43513d8083d 100644 --- a/drivers/mtd/nand/spi/unim.c +++ b/drivers/mtd/nand/spi/unim.c @@ -183,6 +183,31 @@ static int um19a9xisw_ecc_get_status(struct spinand_device *spinand, } } +/* + * ecc bits: 0xC0[4,6] + * [0b000], No bit errors were detected; + * [0b001], Bit errors were detected and corrected; + * [0b010], Bit errors greater than ECC capability(8 bits) and not corrected; + * [0b011], Bit error count equals the bit flip detection threshold + * [0b100], Reserved; + * [0b101], Bit error count equals the bit flip detection threshold + * [0b110], Reserved; + * [0b111], Invalid; + */ +static int um19a0xisw_ecc_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + struct nand_device *nand = spinand_to_nand(spinand); + u8 eccsr = (status & GENMASK(6, 4)) >> 4; + + if (eccsr <= 1) + return eccsr; + else if (eccsr == 3 || eccsr == 5) + return nanddev_get_ecc_requirements(nand)->strength; + else + return -EBADMSG; +} + static const struct spinand_info unim_zl_spinand_table[] = { SPINAND_INFO("TX25G01", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF1), @@ -250,6 +275,24 @@ static const struct spinand_info unim_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&um19a1xisw_ooblayout, um19a9xisw_ecc_get_status)), + SPINAND_INFO("UM19A0HISW", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14), + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&um19a0xisw_ooblayout, um19a0xisw_ecc_ecc_get_status)), + SPINAND_INFO("UM19A0LISW", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15), + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&um19a0xisw_ooblayout, um19a0xisw_ecc_ecc_get_status)), }; static const struct spinand_manufacturer_ops unim_spinand_manuf_ops = { From af9ab5cb5812b2aa4220c05fce3eca85a8d24915 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Fri, 17 Jan 2025 00:09:53 +0800 Subject: [PATCH 12/12] mtd: spi-nor: xmc: Support XM25QU256C Change-Id: I2ad00d784627f2ca69c6bec46d97ab1415facc42 Signed-off-by: Jon Lin --- drivers/mtd/spi-nor/xmc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/spi-nor/xmc.c b/drivers/mtd/spi-nor/xmc.c index 747c0577aecf..c2a5ccbfee01 100644 --- a/drivers/mtd/spi-nor/xmc.c +++ b/drivers/mtd/spi-nor/xmc.c @@ -37,6 +37,9 @@ static const struct flash_info xmc_nor_parts[] = { { "XM25QU128C", INFO(0x204118, 0, 64 * 1024, 256) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { "XM25QU256C", INFO(0x204119, 0, 64 * 1024, 512) + NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | + SPI_NOR_QUAD_READ) }, }; const struct spi_nor_manufacturer spi_nor_xmc = {