From 1c2dcc6d2b2f4cf5c71667b5a9bb72a67188e7e0 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Thu, 20 Mar 2025 15:43:13 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3576-vehicle-evb-v20-serdes-mfd-display-maxim: remove assigned VPLL clk rate VPLL is initialized at uboot for dclk, If kernel assigned VPLL clk rate and different with uboot set rate, this will lead to VPLL reinitialized and lead to splash screen. Signed-off-by: Sandy Huang Change-Id: I501bf982b6016841ea046325d692aee73618357b --- .../rk3576-vehicle-evb-v20-serdes-mfd-display-maxim.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-serdes-mfd-display-maxim.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-serdes-mfd-display-maxim.dtsi index 47dd649fdda5..5c08a3329b03 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-serdes-mfd-display-maxim.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-serdes-mfd-display-maxim.dtsi @@ -1690,11 +1690,6 @@ status = "okay"; }; -&vop { - assigned-clocks = <&cru PLL_VPLL>; - assigned-clock-rates = <1150000000>; -}; - //edp &vp0 { assigned-clocks = <&cru DCLK_VP0_SRC>;