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arm64: dts: rockchip: rk3568: Add display subsystem dt node
The data route from vop vp to interface is shown as bellow.
+---------+
+------->+ HDMI |
| +---------+
+--------------+ |
| | | +---------+
| VP0 +------->-------->+ eDP |
| | | +---------+
+--------------+ |
| +---------+
+------->+ DSI |
+---------+
+---------+
+------>+ HDMI |
| +---------+
|
| +---------+
+-------------+ +------>+ eDP |
| | | +---------+
| VP1 +--------->+
| | | +---------+
+-------------+ +------>+ DSI |
| +---------+
|
| +---------+
+------>+ LVDS |
+---------+
+---------+
+------>+ LVDS |
| +---------+
+------------+ |
| | |
| VP2 +---------->-
| | |
+------------+ |
| +---------------+
+------>+RGB/BT656/1120 |
+---------------+
Change-Id: Ifd505a53303817b8f0785d5f0c5f22bcca590305
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
This commit is contained in:
Andy Yan
@@ -18,6 +18,8 @@
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#size-cells = <2>;
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aliases {
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dsi0 = &dsi0;
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dsi1 = &dsi1;
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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i2c0 = &i2c0;
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@@ -26,6 +28,8 @@
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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lvds0 = &lvds0;
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lvds1 = &lvds1;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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@@ -124,6 +128,11 @@
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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display_subsystem: display-subsystem {
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compatible = "rockchip,display-subsystem";
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ports = <&vop_out>;
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};
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mpp_srv: mpp-srv {
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compatible = "rockchip,mpp-service";
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rockchip,taskqueue-count = <5>;
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@@ -356,6 +365,85 @@
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compatible = "rockchip,rk3568-io-voltage-domain";
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status = "disabled";
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};
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lvds0: lvds0 {
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compatible = "rockchip,rk3568-lvds";
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phys = <&video_phy0>;
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phy-names = "phy";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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lvds0_in_vp1: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vp1_out_lvds0>;
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};
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lvds0_in_vp2: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vp2_out_lvds0>;
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};
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};
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};
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};
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lvds1: lvds1 {
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compatible = "rockchip,rk3568-lvds";
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phys = <&video_phy1>;
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phy-names = "phy";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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lvds1_in_vp1: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vp1_out_lvds1>;
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};
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lvds1_in_vp2: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vp2_out_lvds1>;
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};
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};
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};
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};
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rgb: rgb {
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compatible = "rockchip,rk3568-rgb";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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rgb_in_vp2: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vp2_out_rgb>;
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};
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};
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};
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};
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};
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pipe_phy_grf0: syscon@fdc70000 {
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@@ -840,6 +928,232 @@
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};
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};
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vop: vop@fe040000 {
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compatible = "rockchip,rk3568-vop";
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reg = <0x0 0xfe040000 0x0 0x3000>;
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reg-names = "regs";
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interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
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clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2";
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iommus = <&vop_mmu>;
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power-domains = <&power RK3568_PD_VO>;
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status = "disabled";
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vop_out: ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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vp0_out_dsi0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&dsi0_in_vp0>;
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};
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vp0_out_dsi1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&dsi1_in_vp0>;
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};
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vp0_out_edp: endpoint@2 {
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reg = <2>;
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remote-endpoint = <&edp_in_vp0>;
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};
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vp0_out_hdmi: endpoint@3 {
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reg = <3>;
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remote-endpoint = <&hdmi_in_vp0>;
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};
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};
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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vp1_out_dsi0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&dsi0_in_vp1>;
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};
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vp1_out_dsi1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&dsi1_in_vp1>;
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};
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vp1_out_edp: endpoint@2 {
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reg = <2>;
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remote-endpoint = <&edp_in_vp1>;
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};
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vp1_out_hdmi: endpoint@3 {
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reg = <3>;
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remote-endpoint = <&hdmi_in_vp1>;
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};
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vp1_out_lvds0: endpoint@4 {
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reg = <4>;
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remote-endpoint = <&lvds0_in_vp1>;
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};
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vp1_out_lvds1: endpoint@5 {
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reg = <5>;
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remote-endpoint = <&lvds1_in_vp1>;
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};
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};
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port@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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vp2_out_lvds0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&lvds0_in_vp2>;
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};
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vp2_out_lvds1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&lvds1_in_vp2>;
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};
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vp2_out_rgb: endpoint@2 {
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reg = <2>;
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remote-endpoint = <&rgb_in_vp2>;
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};
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};
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};
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};
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vop_mmu: iommu@fe043e00 {
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compatible = "rockchip,iommu-v2";
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reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
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interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "vop_mmu";
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clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
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clock-names = "aclk", "iface";
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#iommu-cells = <0>;
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status = "disabled";
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};
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dsi0: dsi@fe060000 {
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compatible = "rockchip,rk3568-mipi-dsi";
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reg = <0x0 0xfe060000 0x0 0x10000>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_DSITX_0>, <&mipi_dphy0>;
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clock-names = "pclk", "hs_clk";
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resets = <&cru SRST_P_DSITX_0>;
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reset-names = "apb";
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phys = <&mipi_dphy0>;
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phy-names = "mipi_dphy";
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power-domains = <&power RK3568_PD_VO>;
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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dsi0_in: port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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dsi0_in_vp0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vp0_out_dsi0>;
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};
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dsi0_in_vp1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vp1_out_dsi0>;
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};
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};
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};
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};
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dsi1: dsi@fe070000 {
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compatible = "rockchip,rk3568-mipi-dsi";
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reg = <0x0 0xfe070000 0x0 0x10000>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_DSITX_1>, <&mipi_dphy1>;
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clock-names = "pclk", "hs_clk";
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resets = <&cru SRST_P_DSITX_1>;
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reset-names = "apb";
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phys = <&mipi_dphy1>;
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phy-names = "mipi_dphy";
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power-domains = <&power RK3568_PD_VO>;
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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dsi1_in: port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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dsi1_in_vp0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vp0_out_dsi1>;
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};
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dsi1_in_vp1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vp1_out_dsi1>;
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};
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};
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};
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};
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hdmi: hdmi@fe0a0000 {
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compatible = "rockchip,rk3568-dw-hdmi";
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reg = <0x0 0xfe0a0000 0x0 0x20000>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_HDMI_HOST>,
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<&cru CLK_HDMI_SFR>,
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<&cru CLK_HDMI_CEC>;
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clock-names = "iahb", "isfr", "cec";
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power-domains = <&power RK3568_PD_VO>;
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reg-io-width = <4>;
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rockchip,grf = <&grf>;
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#sound-dai-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&hdmitx_scl &hdmitx_sda>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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hdmi_in: port {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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hdmi_in_vp0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vp0_out_hdmi>;
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};
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hdmi_in_vp1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vp1_out_hdmi>;
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};
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};
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};
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};
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edp: edp@fe0c0000 {
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compatible = "rockchip,rk3568-edp";
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reg = <0x0 0xfe0c0000 0x0 0x10000>;
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@@ -852,6 +1166,27 @@
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phy-names = "dp";
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power-domains = <&power RK3568_PD_VO>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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edp_in: port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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edp_in_vp0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vp0_out_edp>;
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};
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edp_in_vp1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vp1_out_edp>;
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};
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};
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};
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};
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qos_gpu: qos@fe128000 {
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@@ -1866,6 +2201,66 @@
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status = "disabled";
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};
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mipi_dphy0: mipi-dphy@fe850000 {
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compatible = "rockchip,rk3568-mipi-dphy";
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reg = <0x0 0xfe850000 0x0 0x10000>;
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clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
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clock-names = "ref", "pclk";
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clock-output-names = "mipi_dphy_pll";
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#clock-cells = <0>;
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resets = <&cru SRST_P_MIPIDSIPHY0>;
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reset-names = "apb";
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power-domains = <&power RK3568_PD_VO>;
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#phy-cells = <0>;
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rockchip,grf = <&grf>;
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status = "disabled";
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};
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video_phy0: video-phy@fe850000 {
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compatible = "rockchip,rk3568-video-phy";
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reg = <0x0 0xfe850000 0x0 0x10000>,
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<0x0 0xfe060000 0x0 0x10000>;
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clocks = <&pmucru CLK_MIPIDSIPHY0_REF>,
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<&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>;
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clock-names = "ref", "pclk_phy", "pclk_host";
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#clock-cells = <0>;
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resets = <&cru SRST_P_MIPIDSIPHY0>;
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reset-names = "rst";
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power-domains = <&power RK3568_PD_VO>;
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#phy-cells = <0>;
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status = "disabled";
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};
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mipi_dphy1: mipi-dphy@fe860000 {
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compatible = "rockchip,rk3568-mipi-dphy";
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reg = <0x0 0xfe860000 0x0 0x10000>;
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clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
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clock-names = "ref", "pclk";
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clock-output-names = "mipi_dphy1_pll";
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#clock-cells = <0>;
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resets = <&cru SRST_P_MIPIDSIPHY1>;
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reset-names = "apb";
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power-domains = <&power RK3568_PD_VO>;
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#phy-cells = <0>;
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rockchip,grf = <&grf>;
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status = "disabled";
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};
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video_phy1: video-phy@fe860000 {
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compatible = "rockchip,rk3568-video-phy";
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reg = <0x0 0xfe860000 0x0 0x10000>,
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<0x0 0xfe070000 0x0 0x10000>;
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clocks = <&pmucru CLK_MIPIDSIPHY1_REF>,
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<&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>;
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clock-names = "ref", "pclk_phy", "pclk_host";
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#clock-cells = <0>;
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resets = <&cru SRST_P_MIPIDSIPHY1>;
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reset-names = "rst";
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power-domains = <&power RK3568_PD_VO>;
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#phy-cells = <0>;
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status = "disabled";
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};
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usb2phy0: usb2-phy@fe8a0000 {
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compatible = "rockchip,rk3568-usb2phy";
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reg = <0x0 0xfe8a0000 0x0 0x10000>;
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