From 1cfd120ea47eb5528b72832e9ad2f67a3f80d180 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Thu, 1 Aug 2024 09:12:18 +0800 Subject: [PATCH] clk: rockchip: rk3576: add CLK_SET_RATE_PARENT for sclk_uart1 Signed-off-by: Elaine Zhang Change-Id: I34bf45a3565a7a72ee0f216e277699b979cd3af0 --- drivers/clk/rockchip/clk-rk3576.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3576.c b/drivers/clk/rockchip/clk-rk3576.c index cfc52555ce8f..450338d6b852 100644 --- a/drivers/clk/rockchip/clk-rk3576.c +++ b/drivers/clk/rockchip/clk-rk3576.c @@ -1646,7 +1646,7 @@ static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = { COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_pmu200m_pmu100m_pmu50m_24m_p, 0, RK3576_PMU_CLKSEL_CON(6), 7, 2, MFLAGS, RK3576_PMU_CLKGATE_CON(5), 2, GFLAGS), - COMPOSITE_NODIV(SCLK_UART1, "sclk_uart1", uart1_p, 0, + COMPOSITE_NODIV(SCLK_UART1, "sclk_uart1", uart1_p, CLK_SET_RATE_PARENT, RK3576_PMU_CLKSEL_CON(8), 0, 1, MFLAGS, RK3576_PMU_CLKGATE_CON(5), 5, GFLAGS), GATE(PCLK_UART1, "pclk_uart1", "pclk_pmu1_root", 0,