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add alc5621 and alc5631 codec support

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This commit is contained in:
陈辉
2011-04-19 09:38:09 +08:00
parent 9b54151daf
commit 1d3ee43b13
13 changed files with 5221 additions and 90 deletions
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2
arch/arm/configs/rk29_sdk_defconfig
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@@ -1309,6 +1309,8 @@ CONFIG_SND_RK29_SOC_I2S=y
CONFIG_SND_RK29_SOC_I2S_8CH=y
# CONFIG_SND_RK29_SOC_WM8988 is not set
CONFIG_SND_RK29_SOC_WM8900=y
# CONFIG_SND_RK29_SOC_alc5621 is not set
# CONFIG_SND_RK29_SOC_alc5631 is not set
# CONFIG_SND_RK29_SOC_WM8994 is not set
# CONFIG_SND_RK29_CODEC_SOC_MASTER is not set
CONFIG_SND_RK29_CODEC_SOC_SLAVE=y

14
arch/arm/mach-rk29/board-rk29sdk.c
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@@ -512,6 +512,20 @@ static struct i2c_board_info __initdata board_i2c0_devices[] = {
.flags = 0,
},
#endif
#if defined (CONFIG_SND_SOC_alc5621)
{
.type = "ALC5621",
.addr = 0x1a,
.flags = 0,
},
#endif
#if defined (CONFIG_SND_SOC_alc5631)
{
.type = "rt5631",
.addr = 0x1a,
.flags = 0,
},
#endif
#if defined (CONFIG_SND_SOC_RK1000)
{
.type = "rk1000_i2c_codec",

16
sound/soc/codecs/Kconfig
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@@ -42,6 +42,8 @@ config SND_SOC_ALL_CODECS
select SND_SOC_WM8753 if SND_SOC_I2C_AND_SPI
select SND_SOC_WM8776 if SND_SOC_I2C_AND_SPI
select SND_SOC_WM8900 if I2C
select SND_SOC_alc5621 if I2C
select SND_SOC_alc5631 if I2C
select SND_SOC_WM8903 if I2C
select SND_SOC_WM8940 if I2C
select SND_SOC_WM8960 if I2C
@@ -66,11 +68,13 @@ config SND_SOC_ALL_CODECS
be selected separately.
If unsure select "N".
select SND_SOC_ALC5623_RT if I2C
config SND_SOC_ALC5623
tristate
config SND_SOC_WM_HUBS
tristate
default y if SND_SOC_WM8993=y || SND_SOC_WM8994=y
default m if SND_SOC_WM8993=m || SND_SOC_WM8994=m
default y if SND_SOC_WM8993=y
default m if SND_SOC_WM8993=m
config SND_SOC_AC97_CODEC
tristate
@@ -179,6 +183,12 @@ config SND_SOC_WM8776
config SND_SOC_WM8900
tristate
config SND_SOC_alc5621
tristate
config SND_SOC_alc5631
tristate
config SND_SOC_WM8903
tristate

6
sound/soc/codecs/Makefile
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@@ -30,6 +30,8 @@ snd-soc-wm8750-objs := wm8750.o
snd-soc-wm8753-objs := wm8753.o
snd-soc-wm8776-objs := wm8776.o
snd-soc-wm8900-objs := wm8900.o
snd-soc-alc5621-objs := alc5621.o
snd-soc-alc5631-objs := rt5631.o
snd-soc-wm8903-objs := wm8903.o
snd-soc-wm8940-objs := wm8940.o
snd-soc-wm8960-objs := wm8960.o
@@ -49,6 +51,8 @@ snd-soc-rk1000-objs := rk1000_codec.o
# Amp
snd-soc-max9877-objs := max9877.o
snd-soc-alc5623-objs := alc5623_tuning.o
obj-$(CONFIG_SND_SOC_ALC5623) += snd-soc-alc5623.o
obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o
obj-$(CONFIG_SND_SOC_AD1836) += snd-soc-ad1836.o
obj-$(CONFIG_SND_SOC_AD1938) += snd-soc-ad1938.o
@@ -81,6 +85,8 @@ obj-$(CONFIG_SND_SOC_WM8750) += snd-soc-wm8750.o
obj-$(CONFIG_SND_SOC_WM8753) += snd-soc-wm8753.o
obj-$(CONFIG_SND_SOC_WM8776) += snd-soc-wm8776.o
obj-$(CONFIG_SND_SOC_WM8900) += snd-soc-wm8900.o
obj-$(CONFIG_SND_SOC_alc5621) += snd-soc-alc5621.o
obj-$(CONFIG_SND_SOC_alc5631) += snd-soc-alc5631.o
obj-$(CONFIG_SND_SOC_WM8903) += snd-soc-wm8903.o
obj-$(CONFIG_SND_SOC_WM8971) += snd-soc-wm8971.o
obj-$(CONFIG_SND_SOC_WM8974) += snd-soc-wm8974.o

1932
sound/soc/codecs/alc5621.c Normal file
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File diff suppressed because it is too large Load Diff

516
sound/soc/codecs/alc5621.h Normal file
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@@ -0,0 +1,516 @@
#ifndef _RT5621_H
#define _RT5621_H
#define RT5621_RESET 0X00 //RESET CODEC TO DEFAULT
#define RT5621_SPK_OUT_VOL 0X02 //SPEAKER OUT VOLUME
#define RT5621_HP_OUT_VOL 0X04 //HEADPHONE OUTPUT VOLUME
#define RT5621_MONO_AUX_OUT_VOL 0X06 //MONO OUTPUT/AUXOUT VOLUME
#define RT5621_AUXIN_VOL 0X08 //AUXIN VOLUME
#define RT5621_LINE_IN_VOL 0X0A //LINE IN VOLUME
#define RT5621_STEREO_DAC_VOL 0X0C //STEREO DAC VOLUME
#define RT5621_MIC_VOL 0X0E //MICROPHONE VOLUME
#define RT5621_MIC_ROUTING_CTRL 0X10 //MIC ROUTING CONTROL
#define RT5621_ADC_REC_GAIN 0X12 //ADC RECORD GAIN
#define RT5621_ADC_REC_MIXER 0X14 //ADC RECORD MIXER CONTROL
#define RT5621_SOFT_VOL_CTRL_TIME 0X16 //SOFT VOLUME CONTROL TIME
#define RT5621_OUTPUT_MIXER_CTRL 0X1C //OUTPUT MIXER CONTROL
#define RT5621_MIC_CTRL 0X22 //MICROPHONE CONTROL
#define RT5621_AUDIO_INTERFACE 0X34 //AUDIO INTERFACE
#define RT5621_STEREO_AD_DA_CLK_CTRL 0X36 //STEREO AD/DA CLOCK CONTROL
#define RT5621_COMPANDING_CTRL 0X38 //COMPANDING CONTROL
#define RT5621_PWR_MANAG_ADD1 0X3A //POWER MANAGMENT ADDITION 1
#define RT5621_PWR_MANAG_ADD2 0X3C //POWER MANAGMENT ADDITION 2
#define RT5621_PWR_MANAG_ADD3 0X3E //POWER MANAGMENT ADDITION 3
#define RT5621_ADD_CTRL_REG 0X40 //ADDITIONAL CONTROL REGISTER
#define RT5621_GLOBAL_CLK_CTRL_REG 0X42 //GLOBAL CLOCK CONTROL REGISTER
#define RT5621_PLL_CTRL 0X44 //PLL CONTROL
#define RT5621_GPIO_OUTPUT_PIN_CTRL 0X4A //GPIO OUTPUT PIN CONTROL
#define RT5621_GPIO_PIN_CONFIG 0X4C //GPIO PIN CONFIGURATION
#define RT5621_GPIO_PIN_POLARITY 0X4E //GPIO PIN POLARITY/TYPE
#define RT5621_GPIO_PIN_STICKY 0X50 //GPIO PIN STICKY
#define RT5621_GPIO_PIN_WAKEUP 0X52 //GPIO PIN WAKE UP
#define RT5621_GPIO_PIN_STATUS 0X54 //GPIO PIN STATUS
#define RT5621_GPIO_PIN_SHARING 0X56 //GPIO PIN SHARING
#define RT5621_OVER_TEMP_CURR_STATUS 0X58 //OVER TEMPERATURE AND CURRENT STATUS
#define RT5621_JACK_DET_CTRL 0X5A //JACK DETECT CONTROL REGISTER
#define RT5621_MISC_CTRL 0X5E //MISC CONTROL
#define RT5621_PSEDUEO_SPATIAL_CTRL 0X60 //PSEDUEO STEREO & SPATIAL EFFECT BLOCK CONTROL
#define RT5621_EQ_CTRL 0X62 //EQ CONTROL
#define RT5621_EQ_MODE_ENABLE 0X66 //EQ MODE CHANGE ENABLE
#define RT5621_AVC_CTRL 0X68 //AVC CONTROL
#define RT5621_HID_CTRL_INDEX 0X6A //HIDDEN CONTROL INDEX PORT
#define RT5621_HID_CTRL_DATA 0X6C //HIDDEN CONTROL DATA PORT
#define RT5621_VENDOR_ID1 0x7C //VENDOR ID1
#define RT5621_VENDOR_ID2 0x7E //VENDOR ID2
//global definition
#define RT_L_MUTE (0x1<<15) //MUTE LEFT CONTROL BIT
#define RT_L_ZC (0x1<<14) //LEFT ZERO CROSS CONTROL BIT
#define RT_L_SM (0x1<<13) //LEFT SOFTMUTE CONTROL BIT
#define RT_R_MUTE (0x1<<7) //MUTE RIGHT CONTROL BIT
#define RT_R_ZC (0x1<<6) //RIGHT ZERO CROSS CONTROL BIT
#define RT_R_SM (0x1<<5) //RIGHT SOFTMUTE CONTROL BIT
#define RT_M_HP_MIXER (0x1<<15) //Mute source to HP Mixer
#define RT_M_SPK_MIXER (0x1<<14) //Mute source to Speaker Mixer
#define RT_M_MONO_MIXER (0x1<<13) //Mute source to Mono Mixer
#define SPK_CLASS_AB 0
#define SPK_CLASS_D 1
//Mic Routing Control(0x10)
#define M_MIC1_TO_HP_MIXER (0x1<<15) //Mute MIC1 to HP mixer
#define M_MIC1_TO_SPK_MIXER (0x1<<14) //Mute MiC1 to SPK mixer
#define M_MIC1_TO_MONO_MIXER (0x1<<13) //Mute MIC1 to MONO mixer
#define MIC1_DIFF_INPUT_CTRL (0x1<<12) //MIC1 different input control
#define M_MIC2_TO_HP_MIXER (0x1<<7) //Mute MIC2 to HP mixer
#define M_MIC2_TO_SPK_MIXER (0x1<<6) //Mute MiC2 to SPK mixer
#define M_MIC2_TO_MONO_MIXER (0x1<<5) //Mute MIC2 to MONO mixer
#define MIC2_DIFF_INPUT_CTRL (0x1<<4) //MIC2 different input control
//ADC Record Gain(0x12)
#define M_ADC_L_TO_HP_MIXER (0x1<<15) //Mute left of ADC to HP Mixer
#define M_ADC_R_TO_HP_MIXER (0x1<<14) //Mute right of ADC to HP Mixer
#define M_ADC_L_TO_MONO_MIXER (0x1<<13) //Mute left of ADC to MONO Mixer
#define M_ADC_R_TO_MONO_MIXER (0x1<<12) //Mute right of ADC to MONO Mixer
#define ADC_L_GAIN_MASK (0x1f<<7) //ADC Record Gain Left channel Mask
#define ADC_L_ZC_DET (0x1<<6) //ADC Zero-Cross Detector Control
#define ADC_R_ZC_DET (0x1<<5) //ADC Zero-Cross Detector Control
#define ADC_R_GAIN_MASK (0x1f<<0) //ADC Record Gain Right channel Mask
//ADC Input Mixer Control(0x14)
#define M_MIC1_TO_ADC_L_MIXER (0x1<<14) //Mute mic1 to left channel of ADC mixer
#define M_MIC2_TO_ADC_L_MIXER (0x1<<13) //Mute mic2 to left channel of ADC mixer
#define M_LINEIN_L_TO_ADC_L_MIXER (0x1<<12) //Mute line In left channel to left channel of ADC mixer
#define M_AUXIN_L_TO_ADC_L_MIXER (0x1<<11) //Mute aux In left channel to left channel of ADC mixer
#define M_HPMIXER_L_TO_ADC_L_MIXER (0x1<<10) //Mute HP mixer left channel to left channel of ADC mixer
#define M_SPKMIXER_L_TO_ADC_L_MIXER (0x1<<9) //Mute SPK mixer left channel to left channel of ADC mixer
#define M_MONOMIXER_L_TO_ADC_L_MIXER (0x1<<8) //Mute MONO mixer left channel to left channel of ADC mixer
#define M_MIC1_TO_ADC_R_MIXER (0x1<<6) //Mute mic1 to right channel of ADC mixer
#define M_MIC2_TO_ADC_R_MIXER (0x1<<5) //Mute mic2 to right channel of ADC mixer
#define M_LINEIN_R_TO_ADC_R_MIXER (0x1<<4) //Mute lineIn right channel to right channel of ADC mixer
#define M_AUXIN_R_TO_ADC_R_MIXER (0x1<<3) //Mute aux In right channel to right channel of ADC mixer
#define M_HPMIXER_R_TO_ADC_R_MIXER (0x1<<2) //Mute HP mixer right channel to right channel of ADC mixer
#define M_SPKMIXER_R_TO_ADC_R_MIXER (0x1<<1) //Mute SPK mixer right channel to right channel of ADC mixer
#define M_MONOMIXER_R_TO_ADC_R_MIXER (0x1<<0) //Mute MONO mixer right channel to right channel of ADC mixer
//Output Mixer Control(0x1C)
#define SPKOUT_N_SOUR_MASK (0x3<<14)
#define SPKOUT_N_SOUR_LN (0x2<<14)
#define SPKOUT_N_SOUR_RP (0x1<<14)
#define SPKOUT_N_SOUR_RN (0x0<<14)
#define SPK_OUTPUT_CLASS_AB (0x0<<13)
#define SPK_OUTPUT_CLASS_D (0x1<<13)
#define SPK_CLASS_AB_S_AMP (0x0<<12)
#define SPK_CALSS_AB_W_AMP (0x1<<12)
#define SPKOUT_INPUT_SEL_MASK (0x3<<10)
#define SPKOUT_INPUT_SEL_MONOMIXER (0x3<<10)
#define SPKOUT_INPUT_SEL_SPKMIXER (0x2<<10)
#define SPKOUT_INPUT_SEL_HPMIXER (0x1<<10)
#define SPKOUT_INPUT_SEL_VMID (0x0<<10)
#define HPL_INPUT_SEL_HPLMIXER (0x1<<9)
#define HPR_INPUT_SEL_HPRMIXER (0x1<<8)
#define MONO_AUX_INPUT_SEL_MASK (0x3<<6)
#define MONO_AUX_INPUT_SEL_MONO (0x3<<6)
#define MONO_AUX_INPUT_SEL_SPK (0x2<<6)
#define MONO_AUX_INPUT_SEL_HP (0x1<<6)
#define MONO_AUX_INPUT_SEL_VMID (0x0<<6)
//Micphone Control define(0x22)
#define MIC1 1
#define MIC2 2
#define MIC_BIAS_90_PRECNET_AVDD 1
#define MIC_BIAS_75_PRECNET_AVDD 2
#define MIC1_BOOST_CTRL_MASK (0x3<<10)
#define MIC1_BOOST_CTRL_BYPASS (0x0<<10)
#define MIC1_BOOST_CTRL_20DB (0x1<<10)
#define MIC1_BOOST_CTRL_30DB (0x2<<10)
#define MIC1_BOOST_CTRL_40DB (0x3<<10)
#define MIC2_BOOST_CTRL_MASK (0x3<<8)
#define MIC2_BOOST_CTRL_BYPASS (0x0<<8)
#define MIC2_BOOST_CTRL_20DB (0x1<<8)
#define MIC2_BOOST_CTRL_30DB (0x2<<8)
#define MIC2_BOOST_CTRL_40DB (0x3<<8)
#define MICBIAS_VOLT_CTRL_MASK (0x1<<5)
#define MICBIAS_VOLT_CTRL_90P (0x0<<5)
#define MICBIAS_VOLT_CTRL_75P (0x1<<5)
#define MICBIAS_SHORT_CURR_DET_MASK (0x3)
#define MICBIAS_SHORT_CURR_DET_600UA (0x0)
#define MICBIAS_SHORT_CURR_DET_1200UA (0x1)
#define MICBIAS_SHORT_CURR_DET_1800UA (0x2)
//Audio Interface(0x34)
#define SDP_MASTER_MODE (0x0<<15) //Main I2S interface select Master mode
#define SDP_SLAVE_MODE (0x1<<15) //Main I2S interface select Slave mode
#define I2S_PCM_MODE (0x1<<14) //PCM 0:mode A ,1:mode B
#define MAIN_I2S_BCLK_POL_CTRL (0x1<<7) //0:Normal 1:Invert
#define ADC_DATA_L_R_SWAP (0x1<<5) //0:ADC data appear at left phase of LRCK
//1:ADC data appear at right phase of LRCK
#define DAC_DATA_L_R_SWAP (0x1<<4) //0:DAC data appear at left phase of LRCK
//1:DAC data appear at right phase of LRCK
//Data Length Slection
#define I2S_DL_MASK (0x3<<2) //main i2s Data Length mask
#define I2S_DL_16 (0x0<<2) //16 bits
#define I2S_DL_20 (0x1<<2) //20 bits
#define I2S_DL_24 (0x2<<2) //24 bits
#define I2S_DL_32 (0x3<<2) //32 bits
//PCM Data Format Selection
#define I2S_DF_MASK (0x3) //main i2s Data Format mask
#define I2S_DF_I2S (0x0) //I2S FORMAT
#define I2S_DF_RIGHT (0x1) //RIGHT JUSTIFIED format
#define I2S_DF_LEFT (0x2) //LEFT JUSTIFIED format
#define I2S_DF_PCM (0x3) //PCM format
//Stereo AD/DA Clock Control(0x36h)
#define I2S_PRE_DIV_MASK (0x7<<12)
#define I2S_PRE_DIV_1 (0x0<<12) //DIV 1
#define I2S_PRE_DIV_2 (0x1<<12) //DIV 2
#define I2S_PRE_DIV_4 (0x2<<12) //DIV 4
#define I2S_PRE_DIV_8 (0x3<<12) //DIV 8
#define I2S_PRE_DIV_16 (0x4<<12) //DIV 16
#define I2S_PRE_DIV_32 (0x5<<12) //DIV 32
#define I2S_SCLK_DIV_MASK (0x7<<9)
#define I2S_SCLK_DIV_1 (0x0<<9) //DIV 1
#define I2S_SCLK_DIV_2 (0x1<<9) //DIV 2
#define I2S_SCLK_DIV_3 (0x2<<9) //DIV 3
#define I2S_SCLK_DIV_4 (0x3<<9) //DIV 4
#define I2S_SCLK_DIV_6 (0x4<<9) //DIV 6
#define I2S_SCLK_DIV_8 (0x5<<9) //DIV 8
#define I2S_SCLK_DIV_12 (0x6<<9) //DIV 12
#define I2S_SCLK_DIV_16 (0x7<<9) //DIV 16
#define I2S_WCLK_DIV_PRE_MASK (0xF<<5)
#define I2S_WCLK_PRE_DIV_1 (0x0<<5) //DIV 1
#define I2S_WCLK_PRE_DIV_2 (0x1<<5) //DIV 2
#define I2S_WCLK_PRE_DIV_3 (0x2<<5) //DIV 3
#define I2S_WCLK_PRE_DIV_4 (0x3<<5) //DIV 4
#define I2S_WCLK_PRE_DIV_5 (0x4<<5) //DIV 5
#define I2S_WCLK_PRE_DIV_6 (0x5<<5) //DIV 6
#define I2S_WCLK_PRE_DIV_7 (0x6<<5) //DIV 7
#define I2S_WCLK_PRE_DIV_8 (0x7<<5) //DIV 8
//........................
#define I2S_WCLK_DIV_MASK (0x7<<2)
#define I2S_WCLK_DIV_2 (0x0<<2) //DIV 2
#define I2S_WCLK_DIV_4 (0x1<<2) //DIV 4
#define I2S_WCLK_DIV_8 (0x2<<2) //DIV 8
#define I2S_WCLK_DIV_16 (0x3<<2) //DIV 16
#define I2S_WCLK_DIV_32 (0x4<<2) //DIV 32
#define ADDA_FILTER_CLK_SEL_256FS (0<<1) //256FS
#define ADDA_FILTER_CLK_SEL_384FS (1<<1) //384FS
#define ADDA_OSR_SEL_64FS (0) //64FS
#define ADDA_OSR_SEL_128FS (1) //128FS
//Power managment addition 1 (0x3A),0:Disable,1:Enable
#define PWR_MAIN_I2S_EN (0x1<<15)
#define PWR_ZC_DET_PD_EN (0x1<<14)
#define PWR_MIC1_BIAS_EN (0x1<<11)
#define PWR_SHORT_CURR_DET_EN (0x1<<10)
#define PWR_SOFTGEN_EN (0x1<<8)
#define PWR_DEPOP_BUF_HP (0x1<<6)
#define PWR_HP_OUT_AMP (0x1<<5)
#define PWR_HP_OUT_ENH_AMP (0x1<<4)
#define PWR_DEPOP_BUF_AUX (0x1<<2)
#define PWR_AUX_OUT_AMP (0x1<<1)
#define PWR_AUX_OUT_ENH_AMP (0x1)
//Power managment addition 2(0x3C),0:Disable,1:Enable
#define PWR_CLASS_AB (0x1<<15)
#define PWR_CLASS_D (0x1<<14)
#define PWR_VREF (0x1<<13)
#define PWR_PLL (0x1<<12)
#define PWR_DAC_REF_CIR (0x1<<10)
#define PWR_L_DAC_CLK (0x1<<9)
#define PWR_R_DAC_CLK (0x1<<8)
#define PWR_L_ADC_CLK_GAIN (0x1<<7)
#define PWR_R_ADC_CLK_GAIN (0x1<<6)
#define PWR_L_HP_MIXER (0x1<<5)
#define PWR_R_HP_MIXER (0x1<<4)
#define PWR_SPK_MIXER (0x1<<3)
#define PWR_MONO_MIXER (0x1<<2)
#define PWR_L_ADC_REC_MIXER (0x1<<1)
#define PWR_R_ADC_REC_MIXER (0x1)
//Power managment addition 3(0x3E),0:Disable,1:Enable
#define PWR_MAIN_BIAS (0x1<<15)
#define PWR_AUXOUT_L_VOL_AMP (0x1<<14)
#define PWR_AUXOUT_R_VOL_AMP (0x1<<13)
#define PWR_SPK_OUT (0x1<<12)
#define PWR_HP_L_OUT_VOL (0x1<<10)
#define PWR_HP_R_OUT_VOL (0x1<<9)
#define PWR_LINEIN_L_VOL (0x1<<7)
#define PWR_LINEIN_R_VOL (0x1<<6)
#define PWR_AUXIN_L_VOL (0x1<<5)
#define PWR_AUXIN_R_VOL (0x1<<4)
#define PWR_MIC1_FUN_CTRL (0x1<<3)
#define PWR_MIC2_FUN_CTRL (0x1<<2)
#define PWR_MIC1_BOOST_MIXER (0x1<<1)
#define PWR_MIC2_BOOST_MIXER (0x1)
//Additional Control Register(0x40)
#define AUXOUT_SEL_DIFF (0x1<<15) //Differential Mode
#define AUXOUT_SEL_SE (0x1<<15) //Single-End Mode
#define SPK_AB_AMP_CTRL_MASK (0x7<<12)
#define SPK_AB_AMP_CTRL_RATIO_225 (0x0<<12) //2.25 Vdd
#define SPK_AB_AMP_CTRL_RATIO_200 (0x1<<12) //2.00 Vdd
#define SPK_AB_AMP_CTRL_RATIO_175 (0x2<<12) //1.75 Vdd
#define SPK_AB_AMP_CTRL_RATIO_150 (0x3<<12) //1.50 Vdd
#define SPK_AB_AMP_CTRL_RATIO_125 (0x4<<12) //1.25 Vdd
#define SPK_AB_AMP_CTRL_RATIO_100 (0x5<<12) //1.00 Vdd
#define SPK_D_AMP_CTRL_MASK (0x3<<10)
#define SPK_D_AMP_CTRL_RATIO_175 (0x0<<10) //1.75 Vdd
#define SPK_D_AMP_CTRL_RATIO_150 (0x1<<10) //1.50 Vdd
#define SPK_D_AMP_CTRL_RATIO_125 (0x2<<10) //1.25 Vdd
#define SPK_D_AMP_CTRL_RATIO_100 (0x3<<10) //1.00 Vdd
#define STEREO_DAC_HI_PASS_FILTER_EN (0x1<<9) //Stereo DAC high pass filter enable
#define STEREO_ADC_HI_PASS_FILTER_EN (0x1<<8) //Stereo ADC high pass filter enable
#define DIG_VOL_BOOST_MASK (0x3<<4) //Digital volume Boost mask
#define DIG_VOL_BOOST_0DB (0x0<<4) //Digital volume Boost 0DB
#define DIG_VOL_BOOST_6DB (0x1<<4) //Digital volume Boost 6DB
#define DIG_VOL_BOOST_12DB (0x2<<4) //Digital volume Boost 12DB
#define DIG_VOL_BOOST_18DB (0x3<<4) //Digital volume Boost 18DB
//Global Clock Control Register(0x42)
#define SYSCLK_SOUR_SEL_MASK (0x1<<15)
#define SYSCLK_SOUR_SEL_MCLK (0x0<<15) //system Clock source from MCLK
#define SYSCLK_SOUR_SEL_PLL (0x1<<15) //system Clock source from PLL
#define PLLCLK_SOUR_SEL_MCLK (0x0<<14) //PLL clock source from MCLK
#define PLLCLK_SOUR_SEL_BITCLK (0x1<<14) //PLL clock source from BITCLK
#define PLLCLK_DIV_RATIO_MASK (0x3<<1)
#define PLLCLK_DIV_RATIO_DIV1 (0x0<<1) //DIV 1
#define PLLCLK_DIV_RATIO_DIV2 (0x1<<1) //DIV 2
#define PLLCLK_DIV_RATIO_DIV4 (0x2<<1) //DIV 4
#define PLLCLK_DIV_RATIO_DIV8 (0x3<<1) //DIV 8
#define PLLCLK_PRE_DIV1 (0x0) //DIV 1
#define PLLCLK_PRE_DIV2 (0x1) //DIV 2
//PLL Control(0x44)
#define PLL_CTRL_M_VAL(m) ((m)&0xf)
#define PLL_CTRL_K_VAL(k) (((k)&0x7)<<4)
#define PLL_CTRL_N_VAL(n) (((n)&0xff)<<8)
//GPIO Pin Configuration(0x4C)
#define GPIO_PIN_MASK (0x1<<1)
#define GPIO_PIN_SET_INPUT (0x1<<1)
#define GPIO_PIN_SET_OUTPUT (0x0<<1)
//Pin Sharing(0x56)
#define LINEIN_L_PIN_SHARING (0x1<<15)
#define LINEIN_L_PIN_AS_LINEIN_L (0x0<<15)
#define LINEIN_L_PIN_AS_JD1 (0x1<<15)
#define LINEIN_R_PIN_SHARING (0x1<<14)
#define LINEIN_R_PIN_AS_LINEIN_R (0x0<<14)
#define LINEIN_R_PIN_AS_JD2 (0x1<<14)
#define GPIO_PIN_SHARING (0x3)
#define GPIO_PIN_AS_GPIO (0x0)
#define GPIO_PIN_AS_IRQOUT (0x1)
#define GPIO_PIN_AS_PLLOUT (0x3)
//Jack Detect Control Register(0x5A)
#define JACK_DETECT_MASK (0x3<<14)
#define JACK_DETECT_USE_JD2 (0x3<<14)
#define JACK_DETECT_USE_JD1 (0x2<<14)
#define JACK_DETECT_USE_GPIO (0x1<<14)
#define JACK_DETECT_OFF (0x0<<14)
#define SPK_EN_IN_HI (0x1<<11)
#define AUX_R_EN_IN_HI (0x1<<10)
#define AUX_L_EN_IN_HI (0x1<<9)
#define HP_EN_IN_HI (0x1<<8)
#define SPK_EN_IN_LO (0x1<<7)
#define AUX_R_EN_IN_LO (0x1<<6)
#define AUX_L_EN_IN_LO (0x1<<5)
#define HP_EN_IN_LO (0x1<<4)
////MISC CONTROL(0x5E)
#define DISABLE_FAST_VREG (0x1<<15)
#define SPK_CLASS_AB_OC_PD (0x1<<13)
#define SPK_CLASS_AB_OC_DET (0x1<<12)
#define HP_DEPOP_MODE3_EN (0x1<<10)
#define HP_DEPOP_MODE2_EN (0x1<<9)
#define HP_DEPOP_MODE1_EN (0x1<<8)
#define AUXOUT_DEPOP_MODE3_EN (0x1<<6)
#define AUXOUT_DEPOP_MODE2_EN (0x1<<5)
#define AUXOUT_DEPOP_MODE1_EN (0x1<<4)
#define M_DAC_L_INPUT (0x1<<3)
#define M_DAC_R_INPUT (0x1<<2)
#define IRQOUT_INV_CTRL (0x1<<0)
//Psedueo Stereo & Spatial Effect Block Control(0x60)
#define SPATIAL_CTRL_EN (0x1<<15)
#define ALL_PASS_FILTER_EN (0x1<<14)
#define PSEUDO_STEREO_EN (0x1<<13)
#define STEREO_EXPENSION_EN (0x1<<12)
#define GAIN_3D_PARA_L_MASK (0x7<<9)
#define GAIN_3D_PARA_L_1_00 (0x0<<9)
#define GAIN_3D_PARA_L_1_25 (0x1<<9)
#define GAIN_3D_PARA_L_1_50 (0x2<<9)
#define GAIN_3D_PARA_L_1_75 (0x3<<9)
#define GAIN_3D_PARA_L_2_00 (0x4<<9)
#define GAIN_3D_PARA_R_MASK (0x7<<6)
#define GAIN_3D_PARA_R_1_00 (0x0<<6)
#define GAIN_3D_PARA_R_1_25 (0x1<<6)
#define GAIN_3D_PARA_R_1_50 (0x2<<6)
#define GAIN_3D_PARA_R_1_75 (0x3<<6)
#define GAIN_3D_PARA_R_2_00 (0x4<<6)
#define RATIO_3D_L_MASK (0x3<<4)
#define RATIO_3D_L_0_0 (0x0<<4)
#define RATIO_3D_L_0_66 (0x1<<4)
#define RATIO_3D_L_1_0 (0x2<<4)
#define RATIO_3D_R_MASK (0x3<<2)
#define RATIO_3D_R_0_0 (0x0<<2)
#define RATIO_3D_R_0_66 (0x1<<2)
#define RATIO_3D_R_1_0 (0x2<<2)
#define APF_MASK (0x3)
#define APF_FOR_48K (0x3)
#define APF_FOR_44_1K (0x2)
#define APF_FOR_32K (0x1)
//EQ CONTROL(0x62)
#define EN_HW_EQ_BLK (0x1<<15) //HW EQ block control
#define EN_HW_EQ_HPF_MODE (0x1<<14) //High Frequency shelving filter mode
#define EN_HW_EQ_SOUR (0x1<<11) //0:DAC PATH,1:ADC PATH
#define EN_HW_EQ_HPF (0x1<<4) //EQ High Pass Filter Control
#define EN_HW_EQ_BP3 (0x1<<3) //EQ Band-3 Control
#define EN_HW_EQ_BP2 (0x1<<2) //EQ Band-2 Control
#define EN_HW_EQ_BP1 (0x1<<1) //EQ Band-1 Control
#define EN_HW_EQ_LPF (0x1<<0) //EQ Low Pass Filter Control
//EQ Mode Change Enable(0x66)
#define EQ_HPF_CHANGE_EN (0x1<<4) //EQ High Pass Filter Mode Change Enable
#define EQ_BP3_CHANGE_EN (0x1<<3) //EQ Band-3 Pass Filter Mode Change Enable
#define EQ_BP2_CHANGE_EN (0x1<<2) //EQ Band-2 Pass Filter Mode Change Enable
#define EQ_BP1_CHANGE_EN (0x1<<1) //EQ Band-1 Pass Filter Mode Change Enable
#define EQ_LPF_CHANGE_EN (0x1<<0) //EQ Low Pass Filter Mode Change Enable
//AVC Control(0x68)
#define AVC_ENABLE (0x1<<15)
#define AVC_TARTGET_SEL_MASK (0x1<<14)
#define AVC_TARTGET_SEL_R (0x1<<14)
#define AVC_TARTGET_SEL_L (0x0<<14)
struct rt5621_setup_data {
unsigned short i2c_address;
unsigned short i2c_bus;
};
#define RT5621_PLL_FR_MCLK 0
#define RT5621_PLL_FR_BCLK 1
#define USE_DAPM_CONTROL 0
#define REALTEK_HWDEP 0
//WaveOut channel for realtek codec
enum
{
RT_WAVOUT_SPK =(0x1<<0),
RT_WAVOUT_SPK_R =(0x1<<1),
RT_WAVOUT_SPK_L =(0x1<<2),
RT_WAVOUT_HP =(0x1<<3),
RT_WAVOUT_HP_R =(0x1<<4),
RT_WAVOUT_HP_L =(0x1<<5),
RT_WAVOUT_MONO =(0x1<<6),
RT_WAVOUT_AUXOUT =(0x1<<7),
RT_WAVOUT_AUXOUT_R =(0x1<<8),
RT_WAVOUT_AUXOUT_L =(0x1<<9),
RT_WAVOUT_LINEOUT =(0x1<<10),
RT_WAVOUT_LINEOUT_R =(0x1<<11),
RT_WAVOUT_LINEOUT_L =(0x1<<12),
RT_WAVOUT_DAC =(0x1<<13),
RT_WAVOUT_ALL_ON =(0x1<<14),
};
//WaveIn channel for realtek codec
enum
{
RT_WAVIN_R_MONO_MIXER =(0x1<<0),
RT_WAVIN_R_SPK_MIXER =(0x1<<1),
RT_WAVIN_R_HP_MIXER =(0x1<<2),
RT_WAVIN_R_PHONE =(0x1<<3),
RT_WAVIN_R_AUXIN =(0x1<<3),
RT_WAVIN_R_LINE_IN =(0x1<<4),
RT_WAVIN_R_MIC2 =(0x1<<5),
RT_WAVIN_R_MIC1 =(0x1<<6),
RT_WAVIN_L_MONO_MIXER =(0x1<<8),
RT_WAVIN_L_SPK_MIXER =(0x1<<9),
RT_WAVIN_L_HP_MIXER =(0x1<<10),
RT_WAVIN_L_PHONE =(0x1<<11),
RT_WAVIN_L_AUXIN =(0x1<<11),
RT_WAVIN_L_LINE_IN =(0x1<<12),
RT_WAVIN_L_MIC2 =(0x1<<13),
RT_WAVIN_L_MIC1 =(0x1<<14),
};
enum
{
POWER_STATE_D0=0,
POWER_STATE_D1,
POWER_STATE_D1_PLAYBACK,
POWER_STATE_D1_RECORD,
POWER_STATE_D2,
POWER_STATE_D2_PLAYBACK,
POWER_STATE_D2_RECORD,
POWER_STATE_D3,
POWER_STATE_D4
};
#if REALTEK_HWDEP
struct rt56xx_reg_state
{
unsigned int reg_index;
unsigned int reg_value;
};
struct rt56xx_cmd
{
size_t number;
struct rt56xx_reg_state __user *buf;
};
enum
{
RT_READ_CODEC_REG_IOCTL = _IOR('R', 0x01, struct rt56xx_cmd),
RT_READ_ALL_CODEC_REG_IOCTL = _IOR('R', 0x02, struct rt56xx_cmd),
RT_WRITE_CODEC_REG_IOCTL = _IOW('R', 0x03, struct rt56xx_cmd),
};
#endif
extern struct snd_soc_dai rt5621_dai;
extern struct snd_soc_codec_device soc_codec_dev_rt5621;
#endif

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#ifndef __RTCODEC5631_H__
#define __RTCODEC5631_H__
#define RT5631_RESET 0X00 //RESET CODEC TO DEFAULT
#define RT5631_SPK_OUT_VOL 0X02 //SPEAKER OUT VOLUME
#define RT5631_HP_OUT_VOL 0X04 //HEADPHONE OUTPUT VOLUME
#define RT5631_MONO_AXO_1_2_VOL 0X06 //MONO/AUXOUT OUTPUT VOLUME
#define RT5631_AUX_IN_VOL 0X0A //AUX IN VOLUME
#define RT5631_STEREO_DAC_VOL_1 0X0C //STEREO DAC VOLUME 1
#define RT5631_MIC_CTRL_1 0X0E //MICROPHONE CONTROL 1
#define RT5631_STEREO_DAC_VOL_2 0X10 //STEREO DAC VOLUME 2
#define RT5631_ADC_CTRL_1 0X12 //STEREO ADC CONTROL 1
#define RT5631_ADC_REC_MIXER 0X14 //ADC RECORD MIXER CONTROL
#define RT5631_ADC_CTRL_2 0X16 //STEREO ADC CONTROL 2
#define RT5631_OUTMIXER_L_CTRL 0X1A //LEFT OUTPUT MIXER CONTROL
#define RT5631_OUTMIXER_R_CTRL 0X1C //RIGHT OUTPUT MIXER CONTROL
#define RT5631_AXO1MIXER_CTRL 0X1E //LOUT MIXER CONTROL
#define RT5631_AXO2MIXER_CTRL 0X20 //LOUT MIXER CONTROL
#define RT5631_MIC_CTRL_2 0X22 //MICROPHONE CONTROL 2
#define RT5631_DIG_MIC_CTRL 0X24 //DIGITAL MICROPHONE CONTROL
#define RT5631_MONO_INPUT_VOL 0X26 //MONO INPUT VOLUME
#define RT5631_SPK_MIXER_CTRL 0X28 //SPEAKER MIXER CONTROL
#define RT5631_SPK_MONO_OUT_CTRL 0X2A //SPEAKER/MONO OUTPUT CONTROL
#define RT5631_SPK_MONO_HP_OUT_CTRL 0X2C //SPEAKER/MONO/HP OUTPUT CONTROL
#define RT5631_SDP_CTRL 0X34 //STEREO I2S SERIAL DATA PORT CONTROL
#define RT5631_STEREO_AD_DA_CLK_CTRL 0X38 //STEREO AD/DA CLOCK CONTROL
#define RT5631_PWR_MANAG_ADD1 0X3A //POWER MANAGMENT ADDITION 1
#define RT5631_PWR_MANAG_ADD2 0X3B //POWER MANAGMENT ADDITION 2
#define RT5631_PWR_MANAG_ADD3 0X3C //POWER MANAGMENT ADDITION 3
#define RT5631_PWR_MANAG_ADD4 0X3E //POWER MANAGMENT ADDITION 4
#define RT5631_GEN_PUR_CTRL_REG 0X40 //GENERAL PURPOSE CONTROL REGISTER
#define RT5631_GLOBAL_CLK_CTRL 0X42 //GLOBAL CLOCK CONTROL
#define RT5631_PLL_CTRL 0X44 //PLL CONTROL
#define RT5631_INT_ST_IRQ_CTRL_1 0X48 //INTERNAL STATUS AND IRQ CONTROL 1
#define RT5631_INT_ST_IRQ_CTRL_2 0X4A //INTERNAL STATUS AND IRQ CONTROL 2
#define RT5631_GPIO_CTRL 0X4C //GPIO OUTPUT CONTROL
#define RT5631_MISC_CTRL 0X52 //MISC CONTROL
#define RT5631_DEPOP_FUN_CTRL_1 0X54 //DE-POP FUNCTION CONTROL 1
#define RT5631_DEPOP_FUN_CTRL_2 0X56 //DE-POP FUNCTION CONTROL 2
#define RT5631_JACK_DET_CTRL 0X5A //JACK DETECT CONTROL REGISTER
#define RT5631_SOFT_VOL_CTRL 0X5C //SOFT VOLUME CONTROL
#define RT5631_ALC_CTRL_1 0X64 //ALC CONTROL 1
#define RT5631_ALC_CTRL_2 0X65 //ALC CONTROL 2
#define RT5631_ALC_CTRL_3 0X66 //ALC CONTROL 3
#define RT5631_PSEUDO_SPATL_CTRL 0X68 //PSEUDO STEREO AND SPATIAL EFFECT CONTROL
#define RT5631_INDEX_ADD 0X6A //INDEX ADDRESS
#define RT5631_INDEX_DATA 0X6C //INDEX DATA
#define RT5631_EQ_CTRL 0X6E //EQ CONTROL
#define RT5631_VENDOR_ID1 0x7C //VENDOR ID1
#define RT5631_VENDOR_ID2 0x7E //VENDOR ID2
//global definition
#define RT_L_MUTE (0x1<<15) //MUTE LEFT CONTROL BIT
#define RT_R_MUTE (0x1<<7) //MUTE RIGHT CONTROL BIT
//Speaker Output Control(0x02)
#define SPK_L_VOL_SEL_MASK (0x1<<14) //Speaker left channel volume input select MASK
#define SPK_L_VOL_SEL_VMID (0x0<<14) //Speaker left channel volume input select VMID
#define SPK_L_VOL_SEL_SPKMIX_L (0x1<<14) //Speaker left channel volume input select SPKMIXER LEFT
#define SPK_R_VOL_SEL_MASK (0x1<< 6) //Speaker right channel volume input select MASK
#define SPK_R_VOL_SEL_VMID (0x0<< 6) //Speaker right channel volume input select VMID
#define SPK_R_VOL_SEL_SPKMIX_R (0x1<< 6) //Speaker right channel volume input select SPKMIXER RIGHT
//Headphone Output Control(0x04)
#define HP_L_VOL_SEL_MASK (0x1<<14) //HP left channel volume input select MASK
#define HP_L_VOL_SEL_VMID (0x0<<14) //HP left channel volume input select VMID
#define HP_L_VOL_SEL_OUTMIX_L (0x1<<14) //HP left channel volume input select OUTMIXER LEFT
#define HP_R_VOL_SEL_MASK (0x1<< 6) //HP right channel volume input select MASK
#define HP_R_VOL_SEL_VMID (0x0<< 6) //HP right channel volume input select VMID
#define HP_R_VOL_SEL_OUTMIX_R (0x1<< 6) //HP right channel volume input select OUTMIXER RIGHT
//Output Control for AUXOUT/MONO(0x06)
#define AUXOUT_1_VOL_SEL_MASK (0x1<<14) //LOUT channel volume input select MASK
#define AUXOUT_1_VOL_SEL_VMID (0x0<<14) //LOUT channel volume input select VMID
#define AUXOUT_1_VOL_SEL_OUTMIX_L (0x1<<14) //LOUT channel volume input select OUTMIXER LEFT
#define MUTE_MONO (0x1<<13) //Mute Mono control
#define AUXOUT_2_VOL_SEL_MASK (0x1<< 6) //ROUT channel volume input select MASK
#define AUXOUT_2_VOL_SEL_VMID (0x0<< 6) //ROUT channel volume input select VMID
#define AUXOUT_2_VOL_SEL_OUTMIX_R (0x1<< 6) //ROUT channel volume input select OUTMIXER RIGHT
//Microphone Input Control 1(0x0E)
#define MIC1_DIFF_INPUT_CTRL (0x1<<15) //MIC1 different input control
#define MIC2_DIFF_INPUT_CTRL (0x1<< 7) //MIC2 different input control
//ADC Recording Mixer Control(0x14)
#define M_OUTMIXER_L_TO_RECMIXER_L (0x1<<15) //Mute left OUTMIXER to left RECMIXER
#define M_MIC1_TO_RECMIXER_L (0x1<<14) //Mute mic1 to left RECMIXER
#define M_AXIL_TO_RECMIXER_L (0x1<<13) //Mute AXIL to left RECMIXER
#define M_MONO_IN_TO_RECMIXER_L (0x1<<12) //Mute BB_RX to left RECMIXER
#define M_OUTMIXER_R_TO_RECMIXER_R (0x1<< 7) //Mute right OUTMIXER to right RECMIXER
#define M_MIC2_TO_RECMIXER_R (0x1<< 6) //Mute mic2 to right RECMIXER
#define M_AXIR_TO_RECMIXER_R (0x1<< 5) //Mute AXIR to right RECMIXER
#define M_MONO_IN_TO_RECMIXER_R (0x1<< 4) //Mute BB_RX to right RECMIXER
//Left Output Mixer Control(0x1A)
#define M_RECMIXER_L_TO_OUTMIXER_L (0x1<<15) //Mute Left RecMixer to Left OutMixer
#define M_RECMIXER_R_TO_OUTMIXER_L (0x1<<14) //Mute Right RecMixer to Left OutMixer
#define M_DAC_L_TO_OUTMIXER_L (0x1<<13) //Mute Left Dac to Left OutMixer
#define M_MIC1_TO_OUTMIXER_L (0x1<<12) //Mute Mic1 to Left OutMixer
#define M_MIC2_TO_OUTMIXER_L (0x1<<11) //Mute Mic2 to Left OutMixer
#define M_MONO_IN_P_TO_OUTMIXER_L (0x1<<10) //Mute MONO IN positive to Left OutMixer
#define M_AXIL_TO_OUTMIXER_L (0x1<< 9) //Mute AXIL to Left OutMixer
#define M_AXIR_TO_OUTMIXER_L (0x1<< 8) //Mute AXIR to Left OutMixer
//Right Output Mixer Control(0x1C)
#define M_RECMIXER_L_TO_OUTMIXER_R (0x1<<15) //Mute Left RecMixer to Right OutMixer
#define M_RECMIXER_R_TO_OUTMIXER_R (0x1<<14) //Mute Right RecMixer to Right OutMixer
#define M_DAC_R_TO_OUTMIXER_R (0x1<<13) //Mute Left Dac to Right OutMixer
#define M_MIC1_TO_OUTMIXER_R (0x1<<12) //Mute Mic1 to Right OutMixer
#define M_MIC2_TO_OUTMIXER_R (0x1<<11) //Mute Mic2 to Right OutMixer
#define M_MONO_IN_N_TO_OUTMIXER_R (0x1<<10) //Mute MONO IN Negative to Right OutMixer
#define M_AXIL_TO_OUTMIXER_R (0x1<< 9) //Mute AXIL to Right OutMixer
#define M_AXIR_TO_OUTMIXER_R (0x1<< 8) //Mute AXIR to Right OutMixer
//Lout Mixer Control(0x1E)
#define M_MIC1_TO_AXO1MIXER (0x1<<15) //Mute MIC1 to LOUT Mixer
#define M_MIC2_TO_AXO1MIXER (0x1<<11) //Mute MIC2 to LOUT Mixer
#define M_OUTMIXER_L_TO_AXO1MIXER (0x1<< 7) //Mute Left Output mixer to LOUT Mixer
#define M_OUTMIXER_R_TO_AXO1MIXER (0x1<< 6) //Mute Right Output mixer to LOUT Mixer
//Rout Mixer Control(0x20)
#define M_MIC1_TO_AXO2MIXER (0x1<<15) //Mute MIC1 to ROUT Mixer
#define M_MIC2_TO_AXO2MIXER (0x1<<11) //Mute MIC2 to ROUT Mixer
#define M_OUTMIXER_L_TO_AXO2MIXER (0x1<< 7) //Mute Left Output mixer to ROUT Mixer
#define M_OUTMIXER_R_TO_AXO2MIXER (0x1<< 6) //Mute Right Output mixer to ROUT Mixer
//Micphone Input Control 2(0x22)
#define MIC_BIAS_90_PRECNET_AVDD 1
#define MIC_BIAS_75_PRECNET_AVDD 2
#define MIC1_BOOST_CTRL_MASK (0xf<<12)
#define MIC1_BOOST_CTRL_BYPASS (0x0<<12)
#define MIC1_BOOST_CTRL_20DB (0x1<<12)
#define MIC1_BOOST_CTRL_24DB (0x2<<12)
#define MIC1_BOOST_CTRL_30DB (0x3<<12)
#define MIC1_BOOST_CTRL_35DB (0x4<<12)
#define MIC1_BOOST_CTRL_40DB (0x5<<12)
#define MIC1_BOOST_CTRL_34DB (0x6<<12)
#define MIC1_BOOST_CTRL_50DB (0x7<<12)
#define MIC1_BOOST_CTRL_52DB (0x8<<12)
#define MIC2_BOOST_CTRL_MASK (0xf<< 8)
#define MIC2_BOOST_CTRL_BYPASS (0x0<< 8)
#define MIC2_BOOST_CTRL_20DB (0x1<< 8)
#define MIC2_BOOST_CTRL_24DB (0x2<< 8)
#define MIC2_BOOST_CTRL_30DB (0x3<< 8)
#define MIC2_BOOST_CTRL_35DB (0x4<< 8)
#define MIC2_BOOST_CTRL_40DB (0x5<< 8)
#define MIC2_BOOST_CTRL_34DB (0x6<< 8)
#define MIC2_BOOST_CTRL_50DB (0x7<< 8)
#define MIC2_BOOST_CTRL_52DB (0x8<< 8)
#define MICBIAS1_VOLT_CTRL_MASK (0x1<< 7)
#define MICBIAS1_VOLT_CTRL_90P (0x0<< 7)
#define MICBIAS1_VOLT_CTRL_75P (0x1<< 7)
#define MICBIAS1_S_C_DET_MASK (0x1<< 6)
#define MICBIAS1_S_C_DET_DIS (0x0<< 6)
#define MICBIAS1_S_C_DET_ENA (0x1<< 6)
#define MICBIAS1_SHORT_CURR_DET_MASK (0x3<< 4)
#define MICBIAS1_SHORT_CURR_DET_600UA (0x0<< 4)
#define MICBIAS1_SHORT_CURR_DET_1500UA (0x1<< 4)
#define MICBIAS1_SHORT_CURR_DET_2000UA (0x2<< 4)
#define MICBIAS2_VOLT_CTRL_MASK (0x1<< 3)
#define MICBIAS2_VOLT_CTRL_90P (0x0<< 3)
#define MICBIAS2_VOLT_CTRL_75P (0x1<< 3)
#define MICBIAS2_S_C_DET_MASK (0x1<< 2)
#define MICBIAS2_S_C_DET_DIS (0x0<< 2)
#define MICBIAS2_S_C_DET_ENA (0x1<< 2)
#define MICBIAS2_SHORT_CURR_DET_MASK (0x3)
#define MICBIAS2_SHORT_CURR_DET_600UA (0x0)
#define MICBIAS2_SHORT_CURR_DET_1500UA (0x1)
#define MICBIAS2_SHORT_CURR_DET_2000UA (0x2)
//Digital Microphone Control(0x24)
#define DMIC_ENA_MASK (0x1<<15)
#define DMIC_ENA (0x1<<15) //use DMIC to ADC Digital filter
#define DMIC_DIS (0x0<<15) //use ADC mixer to ADC Digital filter
#define DMIC_L_CH_MUTE_MASK (0x1<<13)
#define DMIC_L_CH_UNMUTE (0x0<<13)
#define DMIC_L_CH_MUTE (0x1<<13)
#define DMIC_R_CH_MUTE_MASK (0x1<<12)
#define DMIC_R_CH_UNMUTE (0x0<<12)
#define DMIC_R_CH_MUTE (0x1<<12)
#define DMIC_L_CH_LATCH_MASK (0x1<< 9)
#define DMIC_L_CH_LATCH_RISING (0x1<< 9)
#define DMIC_L_CH_LATCH_FALLING (0x0<< 9)
#define DMIC_R_CH_LATCH_MASK (0x1<< 8)
#define DMIC_R_CH_LATCH_RISING (0x1<< 8)
#define DMIC_R_CH_LATCH_FALLING (0x0<< 8)
#define DMIC_CLK_CTRL_MASK (0x3<<4)
#define DMIC_CLK_CTRL_TO_128FS (0x0<<4)
#define DMIC_CLK_CTRL_TO_64FS (0x1<<4)
#define DMIC_CLK_CTRL_TO_32FS (0x2<<4)
//Speaker Mixer Control(0x28)
#define M_RECMIXER_L_TO_SPKMIXER_L (0x1<<15) //Mute Left RecMixer to Left Speaker Mixer
#define M_MIC1_P_TO_SPKMIXER_L (0x1<<14) //Mute MIC1 Positive to Left Speaker Mixer
#define M_DAC_L_TO_SPKMIXER_L (0x1<<13) //Mute Left Dac to Left Speaker Mixer
#define M_OUTMIXER_L_TO_SPKMIXER_L (0x1<<12) //Mute Left OutMixer to Left Speaker Mixer
#define M_RECMIXER_R_TO_SPKMIXER_R (0x1<< 7) //Mute Right RecMixer to Right Speaker Mixer
#define M_MIC2_P_TO_SPKMIXER_R (0x1<< 6) //Mute MIC1 Positive to Right Speaker Mixer
#define M_DAC_R_TO_SPKMIXER_R (0x1<< 5) //Mute Right Dac to Right Speaker Mixer
#define M_OUTMIXER_R_TO_SPKMIXER_R (0x1<< 4) //Mute Right OutMixer to Right Speaker Mixer
//Speaker/Mono Output Control(0x2A)
#define M_SPKVOL_L_TO_SPOL_MIXER (0x1<<15) //Mute Left Speaker Volume to SPOL Mixer
#define M_SPKVOL_R_TO_SPOL_MIXER (0x1<<14) //Mute Right Speaker Volume to SPOL Mixer
#define M_SPKVOL_L_TO_SPOR_MIXER (0x1<<13) //Mute Left Speaker Volume to SPOR Mixer
#define M_SPKVOL_R_TO_SPOR_MIXER (0x1<<12) //Mute Right Speaker Volume to SPOR Mixer
#define M_OUTVOL_L_TO_MONOMIXER (0x1<<11) //Mute Left Output Volume to Mono Mixer
#define M_OUTVOL_R_TO_MONOMIXER (0x1<<10) //Mute Right Output Volume to Mono Mixer
//Speaker/Mono/HP Output Control(0x2C)
#define SPK_L_MUX_SEL_MASK (0x3<<14) //Left Speaker mux select Mask
#define SPK_L_MUX_SEL_SPKMIXER_L (0x0<<14) //Left Speaker mux select Speaker mixer left
#define SPK_L_MUX_SEL_MONO_IN (0x1<<14) //Left Speaker mux select MONO input
#define SPK_L_MUX_SEL_DAC_L (0x3<<14) //Left Speaker mux select Dac left
#define SPK_R_MUX_SEL_MASK (0x3<<10) //Right Speaker mux select Mask
#define SPK_R_MUX_SEL_SPKMIXER_R (0x0<<10) //Right Speaker mux select Speaker mixer right
#define SPK_R_MUX_SEL_MONO_IN (0x1<<10) //Right Speaker mux select MONO input
#define SPK_R_MUX_SEL_DAC_R (0x3<<10) //Right Speaker mux select Dac right
#define MONO_MUX_SEL_MASK (0x3<< 6) //Monoout mux select Mask
#define MONO_MUX_SEL_MONOMIXER (0x0<< 6) //Monoout mux select Mono Mixer
#define MONO_MUX_SEL_MONO_IN (0x1<< 6) //Monoout mux select MONO input
#define HP_L_MUX_SEL_MASK (0x1<< 3) //HP left mux select Mask
#define HP_L_MUX_SEL_HPVOL_L (0x0<< 3) //HP left mux select left HP output volume
#define HP_L_MUX_SEL_DAC_L (0x1<< 3) //HP left mux select Dac left channel
#define HP_R_MUX_SEL_MASK (0x1<< 2) //HP left mux select Mask
#define HP_R_MUX_SEL_HPVOL_R (0x0<< 2) //HP left mux select left HP output volume
#define HP_R_MUX_SEL_DAC_R (0x1<< 2) //HP left mux select Dac left channel
//Stereo I2S Serial Data Port Control(0x34)
#define SDP_MODE_SEL_MASK (0x1<<15) //Main I2S interface select MASK
#define SDP_MODE_SEL_MASTER (0x0<<15) //Main I2S interface select MASTER MODE
#define SDP_MODE_SEL_SLAVE (0x1<<15) //Main I2S interface select SLAVE MODE
#define SDP_ADC_CPS_SEL_MASK (0x3<<10) //ADC Compress select Mask
#define SDP_ADC_CPS_SEL_OFF (0x0<<10) //ADC Compress select OFF
#define SDP_ADC_CPS_SEL_U_LAW (0x1<<10) //ADC Compress select u_law
#define SDP_ADC_CPS_SEL_A_LAW (0x2<<10) //ADC Compress select a_law
#define SDP_DAC_CPS_SEL_MASK (0x3<< 8) //DAC Compress select Mask
#define SDP_DAC_CPS_SEL_OFF (0x0<< 8) //DAC Compress select OFF
#define SDP_DAC_CPS_SEL_U_LAW (0x1<< 8) //DAC Compress select u_law
#define SDP_DAC_CPS_SEL_A_LAW (0x2<< 8) //DAC Compress select a_law
#define SDP_I2S_BCLK_POL_CTRL (0x1<<7) //0:Normal 1:Invert
#define SDP_DAC_R_INV (0x1<<6) //0:Normal 1:Invert
#define SDP_ADC_DATA_L_R_SWAP (0x1<<5) //0:ADC data appear at left phase of LRCK
//1:ADC data appear at right phase of LRCK
#define SDP_DAC_DATA_L_R_SWAP (0x1<<4) //0:DAC data appear at left phase of LRCK
//1:DAC data appear at right phase of LRCK
//Data Length Slection
#define SDP_I2S_DL_MASK (0x3<<2) //Stereo Serial Data Length mask
#define SDP_I2S_DL_16 (0x0<<2) //16 bits
#define SDP_I2S_DL_20 (0x1<<2) //20 bits
#define SDP_I2S_DL_24 (0x2<<2) //24 bits
#define SDP_I2S_DL_8 (0x3<<2) //8 bits
//PCM Data Format Selection
#define SDP_I2S_DF_MASK (0x3) //main i2s Data Format mask
#define SDP_I2S_DF_I2S (0x0) //I2S FORMAT
#define SDP_I2S_DF_LEFT (0x1) //Left JUSTIFIED
#define SDP_I2S_DF_PCM_A (0x2) //PCM format A
#define SDP_I2S_DF_PCM_B (0x3) //PCM format B
//Stereo AD/DA Clock Control(0x38h)
#define I2S_PRE_DIV_MASK (0x7<<13)
#define I2S_PRE_DIV_1 (0x0<<13) //DIV 1
#define I2S_PRE_DIV_2 (0x1<<13) //DIV 2
#define I2S_PRE_DIV_4 (0x2<<13) //DIV 4
#define I2S_PRE_DIV_8 (0x3<<13) //DIV 8
#define I2S_PRE_DIV_16 (0x4<<13) //DIV 16
#define I2S_PRE_DIV_32 (0x5<<13) //DIV 32
#define I2S_LRCK_SEL_N_BCLK_MASK (0x1<<12) //CLOCK RELATIVE OF BCLK AND LCRK
#define I2S_LRCK_SEL_64_BCLK (0x0<<12) //64FS
#define I2S_LRCK_SEL_32_BCLK (0x1<<12) //32FS
#define DAC_OSR_SEL_MASK (0x3<<10)
#define DAC_OSR_SEL_128FS (0x3<<10)
#define DAC_OSR_SEL_64FS (0x3<<10)
#define DAC_OSR_SEL_32FS (0x3<<10)
#define DAC_OSR_SEL_16FS (0x3<<10)
#define ADC_OSR_SEL_MASK (0x3<< 8)
#define ADC_OSR_SEL_128FS (0x3<< 8)
#define ADC_OSR_SEL_64FS (0x3<< 8)
#define ADC_OSR_SEL_32FS (0x3<< 8)
#define ADC_OSR_SEL_16FS (0x3<< 8)
#define ADDA_FILTER_CLK_SEL_256FS (0<<7) //256FS
#define ADDA_FILTER_CLK_SEL_384FS (1<<7) //384FS
//Power managment addition 1 (0x3A),0:Disable,1:Enable
#define PWR_MAIN_I2S_EN (0x1<<15)
#define PWR_CLASS_D (0x1<<12)
#define PWR_ADC_L_CLK (0x1<<11)
#define PWR_ADC_R_CLK (0x1<<10)
#define PWR_DAC_L_CLK (0x1<< 9)
#define PWR_DAC_R_CLK (0x1<< 8)
#define PWR_DAC_REF (0x1<< 7)
#define PWR_DAC_L_TO_MIXER (0x1<< 6)
#define PWR_DAC_R_TO_MIXER (0x1<<5)
//Power managment addition 2 (0x3B),0:Disable,1:Enable
#define PWR_OUTMIXER_L (0x1<<15)
#define PWR_OUTMIXER_R (0x1<<14)
#define PWR_SPKMIXER_L (0x1<<13)
#define PWR_SPKMIXER_R (0x1<<12)
#define PWR_RECMIXER_L (0x1<<11)
#define PWR_RECMIXER_R (0x1<<10)
#define PWR_MIC1_BOOT_GAIN (0x1<< 5)
#define PWR_MIC2_BOOT_GAIN (0x1<< 4)
#define PWR_MICBIAS1_VOL (0x1<< 3)
#define PWR_MICBIAS2_VOL (0x1<< 2)
#define PWR_PLL (0x1<< 1)
//Power managment addition 3(0x3C),0:Disable,1:Enable
#define PWR_VREF (0x1<<15)
#define PWR_FAST_VREF_CTRL (0x1<<14)
#define PWR_MAIN_BIAS (0x1<<13)
#define PWR_AXO1MIXER (0x1<<11)
#define PWR_AXO2MIXER (0x1<<10)
#define PWR_MONOMIXER (0x1<< 9)
#define PWR_MONO_DEPOP_DIS (0x1<< 8)
#define PWR_MONO_AMP_EN (0x1<< 7)
#define PWR_CHARGE_PUMP (0x1<<4)
#define PWR_HP_L_AMP (0x1<<3)
#define PWR_HP_R_AMP (0x1<<2)
#define PWR_HP_DEPOP_DIS (0x1<<1)
#define PWR_HP_AMP_DRIVING (0x1)
//Power managment addition 4(0x3E),0:Disable,1:Enable
#define PWR_SPK_L_VOL (0x1<<15)
#define PWR_SPK_R_VOL (0x1<<14)
#define PWR_LOUT_VOL (0x1<<13)
#define PWR_ROUT_VOL (0x1<<12)
#define PWR_HP_L_OUT_VOL (0x1<<11)
#define PWR_HP_R_OUT_VOL (0x1<<10)
#define PWR_AXIL_IN_VOL (0x1<< 9)
#define PWR_AXIR_IN_VOL (0x1<< 8)
#define PWR_MONO_IN_P_VOL (0x1<< 7)
#define PWR_MONO_IN_N_VOL (0x1<< 6)
//General Purpose Control Register(0x40)
#define SPK_AMP_AUTO_RATIO_EN (0x1<<15) //Speaker Amplifier Auto Ratio Gain Control
#define SPK_AMP_RATIO_CTRL_MASK (0x7<<12)
#define SPK_AMP_RATIO_CTRL_2_34 (0x0<<12) //7.40DB
#define SPK_AMP_RATIO_CTRL_1_99 (0x1<<12) //5.99DB
#define SPK_AMP_RATIO_CTRL_1_68 (0x2<<12) //4.50DB
#define SPK_AMP_RATIO_CTRL_1_56 (0x3<<12) //3.86DB
#define SPK_AMP_RATIO_CTRL_1_44 (0x4<<12) //3.16DB
#define SPK_AMP_RATIO_CTRL_1_27 (0x5<<12) //2.10DB
#define SPK_AMP_RATIO_CTRL_1_09 (0x6<<12) //0.80DB
#define SPK_AMP_RATIO_CTRL_1_00 (0x7<<12) //0.00DB
#define STEREO_DAC_HI_PASS_FILT_EN (0x1<<11) //Stereo DAC high pass filter enable
#define STEREO_ADC_HI_PASS_FILT_EN (0x1<<10) //Stereo ADC high pass filter enable
#define ADC_WIND_FILT_MASK (0x3<<4) //Select ADC Wind Filter Clock type
#define ADC_WIND_FILT_8_16_32K (0x0<<4) //8/16/32k
#define ADC_WIND_FILT_11_22_44K (0x1<<4) //11/22/44k
#define ADC_WIND_FILT_12_24_48K (0x2<<4) //12/24/48k
#define ADC_WIND_FILT_EN (0x1<<3) //Enable ADC Wind Filter
#define ADC_WIND_CNR_FREQ_MASK (0x7<<0) //SelectADC Wind Filter Corner Frequency
#define ADC_WIND_CNR_FREQ_82_113_122 (0x0<<0) //82/113/122 Hz
#define ADC_WIND_CNR_FREQ_102_141_153 (0x1<<0) //102/141/153 Hz
#define ADC_WIND_CNR_FREQ_131_180_156 (0x2<<0) //131/180/156 Hz
#define ADC_WIND_CNR_FREQ_163_225_245 (0x3<<0) //163/225/245 Hz
#define ADC_WIND_CNR_FREQ_204_281_306 (0x4<<0) //204/281/306 Hz
#define ADC_WIND_CNR_FREQ_261_360_392 (0x5<<0) //261/360/392 Hz
#define ADC_WIND_CNR_FREQ_327_450_490 (0x6<<0) //327/450/490 Hz
#define ADC_WIND_CNR_FREQ_408_563_612 (0x7<<0) //408/563/612 Hz
//Global Clock Control Register(0x42)
#define SYSCLK_SOUR_SEL_MASK (0x1<<14)
#define SYSCLK_SOUR_SEL_MCLK (0x0<<14) //system Clock source from MCLK
#define SYSCLK_SOUR_SEL_PLL (0x1<<14) //system Clock source from PLL
#define SYSCLK_SOUR_SEL_PLL_TCK (0x2<<14) //system Clock source from PLL track
#define PLLCLK_SOUR_SEL_MCLK (0x0<<12) //PLL clock source from MCLK
#define PLLCLK_SOUR_SEL_BITCLK (0x1<<12) //PLL clock source from BITCLK
#define PLLCLK_PRE_DIV1 (0x0<<11) //DIV 1
#define PLLCLK_PRE_DIV2 (0x1<<11) //DIV 2
//PLL Control(0x44)
#define PLL_CTRL_M_VAL(m) ((m)&0xf) //M code for analog PLL
#define PLL_CTRL_K_VAL(k) (((k)&0x7)<<4) //K code for analog PLL
#define PLL_CTRL_N_VAL(n) (((n)&0xff)<<8) //N code for analog PLL
//GPIO Pin Configuration(0x4C)
#define GPIO_PIN_FUN_SEL_MASK (0x1<<15)
#define GPIO_PIN_FUN_SEL_IRQ (0x1<<15) //GPIO pin SELECT IRQ
#define GPIO_PIN_FUN_SEL_GPIO_DIMC (0x0<<15) //GPIO PIN SELECT GPIO_DMIC
#define GPIO_DMIC_FUN_SEL_MASK (0x1<<3)
#define GPIO_DMIC_FUN_SEL_DIMC (0x1<<3) //GPIO pin SELECT DMIC
#define GPIO_DMIC_FUN_SEL_GPIO (0x0<<3) //GPIO PIN SELECT GPIO
#define GPIO_PIN_CON_MASK (0x1<<2)
#define GPIO_PIN_SET_INPUT (0x0<<2) //GPIO pin select input
#define GPIO_PIN_SET_OUTPUT (0x1<<2) //GPIO pin select output
//De-POP function Control 1(0x54)
#define POW_ON_SOFT_GEN (0x1<<15) //POWER ON SOFT GENERATOR
#define EN_MUTE_UNMUTE_DEPOP (0x1<<14) //Enable mute/unmute depop
#define EN_DEPOP2_FOR_HP (0x1<<7) //Enable depop 2 for HP
#define PD_HPAMP_L_ST_UP (0x1<<5) //Power Down HPAMP_L Starts Up Signal
#define PD_HPAMP_R_ST_UP (0x1<<4) //Power Down HPAMP_R Starts Up Signal
#define EN_HP_L_M_UN_MUTE_DEPOP (0x1<<1) //Enable left HP mute/unmute depop
#define EN_HP_R_M_UN_MUTE_DEPOP (0x1<<0) //Enable right HP mute/unmute depop
//De-POP Fnction Control(0x56)
#define ENA_CAP_FREE_DEPOP (0x1<<14) //enable depop for Capfree block
//Jack Detect Control Register(0x5A)
#define JD_USE_MASK (0x3<<14) //JD Pin select
#define JD_USE_JD2 (0x3<<14) //select JD2
#define JD_USE_JD1 (0x2<<14) //select JD1
#define JD_USE_GPIO (0x1<<14) //select GPIO
#define JD_OFF (0x0<<14) //off
#define JD_HP_EN (0x1<<11) //JD trigger enable for HP
#define JD_HP_TRI_MASK (0x1<<10) //Trigger mask
#define JD_HP_TRI_HI (0x1<<10) //high trigger
#define JD_HP_TRI_LO (0x1<<10) //low trigger
#define JD_SPK_L_EN (0x1<<9) //JD trigger enable for speaker LP/LN
#define JD_SPK_L_TRI_MASK (0x1<<8) //Trigger mask
#define JD_SPK_L_TRI_HI (0x1<<8) //high trigger
#define JD_SPK_L_TRI_LO (0x0<<8) //low trigger
#define JD_SPK_R_EN (0x1<<7) //JD trigger enable for speaker RP/RN
#define JD_SPK_R_TRI_MASK (0x1<<6) //Trigger mask
#define JD_SPK_R_TRI_HI (0x1<<6) //high trigger
#define JD_SPK_R_TRI_LO (0x0<<6) //low trigger
#define JD_MONO_EN (0x1<<5) //JD trigger enable for monoout
#define JD_MONO_TRI_MASK (0x1<<4) //Trigger mask
#define JD_MONO_TRI_HI (0x1<<4) //high trigger
#define JD_MONO_TRI_LO (0x0<<4) //low trigger
#define JD_AUX_1_EN (0x1<<3) //JD trigger enable for Lout
#define JD_AUX_1_MASK (0x1<<2) //Trigger mask
#define JD_AUX_1_TRI_HI (0x1<<2) //high trigger
#define JD_AUX_1_TRI_LO (0x0<<2) //low trigger
#define JD_AUX_2_EN (0x1<<1) //JD trigger enable for Rout
#define JD_AUX_2_MASK (0x1<<0) //Trigger mask
#define JD_AUX_2_TRI_HI (0x1<<0) //high trigger
#define JD_AUX_2_TRI_LO (0x0<<0) //low trigger
////ALC CONTROL 1(0x64)
#define ALC_ATTACK_RATE_MASK (0x1F<<8) //select ALC attack rate
#define ALC_RECOVERY_RATE_MASK (0x1F<<0) //select ALC Recovery rate
////ALC CONTROL 2(0x65)
#define ALC_COM_NOISE_GATE_MASK (0xF<<0) //select Compensation gain for Noise gate function
////ALC CONTROL 3(0x66)
#define ALC_FUN_MASK (0x3<<14) //select ALC path
#define ALC_FUN_DIS (0x0<<14) //disable
#define ALC_ENA_DAC_PATH (0x1<<14) //DAC path
#define ALC_ENA_ADC_PATH (0x3<<14) //ADC path
#define ALC_PARA_UPDATE (0x1<<13) //update ALC parameter
#define ALC_LIMIT_LEVEL_MASK (0x1F<<8) //ALC limit level
#define ALC_NOISE_GATE_FUN_MASK (0x1<<7) //ALC noise gate function
#define ALC_NOISE_GATE_FUN_DIS (0x0<<7) //disable
#define ALC_NOISE_GATE_FUN_ENA (0x1<<7) //enable
#define ALC_NOISE_GATE_H_D_MASK (0x1<<6) //ALC noise gate hold data function
#define ALC_NOISE_GATE_H_D_DIS (0x0<<6) //disable
#define ALC_NOISE_GATE_H_D_ENA (0x1<<6) //enable
//Psedueo Stereo & Spatial Effect Block Control(0x68)
#define SPATIAL_CTRL_EN (0x1<<15) //enable Spatial effect
#define ALL_PASS_FILTER_EN (0x1<<14) //enable all pass filter
#define PSEUDO_STEREO_EN (0x1<<13) //enable pseudo stereo block
#define STEREO_EXPENSION_EN (0x1<<12) //enable stereo expansion block
#define GAIN_3D_PARA_MASK (0x3<<6) //3D gain parameter
#define GAIN_3D_PARA_1_00 (0x0<<6) //3D gain 1.0
#define GAIN_3D_PARA_1_50 (0x1<<6) //3D gain 1.5
#define GAIN_3D_PARA_2_00 (0x2<<6) //3D gain 2.0
#define RATIO_3D_MASK (0x3<<4) //3D ratio parameter
#define RATIO_3D_0_0 (0x0<<4) //3D ratio 0.0
#define RATIO_3D_0_66 (0x1<<4) //3D ratio 0.66
#define RATIO_3D_1_0 (0x2<<4) //3D ratio 1.0
#define APF_FUN_SLE_MASK (0x3<<0) //select samplerate for all pass filter
#define APF_FUN_SEL_48K (0x3<<0) //select 48k
#define APF_FUN_SEL_44_1K (0x2<<0) //select 44.1k
#define APF_FUN_SEL_32K (0x1<<0) //select 32k
#define APF_FUN_DIS (0x0<<0) //disable
//EQ CONTROL 1(0x6E)
#define HW_EQ_PATH_SEL_MASK (0x1<<15) //HW EQ FUN SEL
#define HW_EQ_PATH_SEL_DAC (0x0<<15) //HW EQ FOR DAC PATH
#define HW_EQ_PATH_SEL_ADC (0x1<<15) //HW EQ FOR ADC PATH
#define HW_EQ_UPDATE_CTRL (0x1<<14) //HW EQ Update CTRL
#define EN_HW_EQ_HPF2 (0x1<<5) //EQ High Pass Filter 2 Control
#define EN_HW_EQ_HPF1 (0x1<<4) //EQ High Pass Filter 1 Control
#define EN_HW_EQ_BP3 (0x1<<3) //EQ Band-3 Control
#define EN_HW_EQ_BP2 (0x1<<2) //EQ Band-2 Control
#define EN_HW_EQ_BP1 (0x1<<1) //EQ Band-1 Control
#define EN_HW_EQ_LPF (0x1<<0) //EQ Low Pass Filter Control
#define REALTEK_HWDEP 0
struct rt5631_setup_data {
int i2c_address;
int i2c_bus;
};
extern struct snd_soc_dai rt5631_dai[];
extern struct snd_soc_codec_device soc_codec_dev_rt5631;
#endif //__RTCODEC5631_H__

19
sound/soc/rk29/Kconfig Executable file → Normal file
View File

@@ -40,7 +40,22 @@ config SND_RK29_SOC_WM8900
help
Say Y if you want to add support for SoC audio on rockchip
with the WM8900.
config SND_RK29_SOC_alc5621
tristate "SoC I2S Audio support for rockchip - alc5621"
depends on SND_RK29_SOC && I2C_RK29
select SND_RK29_SOC_I2S
select SND_SOC_alc5621
help
Say Y if you want to add support for SoC audio on rockchip
with the alc5621.
config SND_RK29_SOC_alc5631
tristate "SoC I2S Audio support for rockchip - alc5631"
depends on SND_RK29_SOC && I2C_RK29
select SND_RK29_SOC_I2S
select SND_SOC_alc5631
help
Say Y if you want to add support for SoC audio on rockchip
with the alc5631.
config SND_RK29_SOC_WM8994
tristate "SoC I2S Audio support for rockchip - WM8994"
depends on SND_RK29_SOC && I2C_RK29
@@ -59,7 +74,7 @@ config SND_RK29_SOC_RK1000
Say Y if you want to add support for SoC audio on rockchip
with the RK1000.
if SND_RK29_SOC_WM8988 || SND_RK29_SOC_RK1000 || SND_RK29_SOC_WM8994 || SND_RK29_SOC_WM8900
if SND_RK29_SOC_WM8988 || SND_RK29_SOC_RK1000 || SND_RK29_SOC_WM8994 || SND_RK29_SOC_WM8900 || SND_RK29_SOC_alc5621 || SND_RK29_SOC_alc5631
choice
prompt "Set i2s type"
config SND_RK29_CODEC_SOC_MASTER

4
sound/soc/rk29/Makefile Executable file → Normal file
View File

@@ -7,6 +7,8 @@ obj-$(CONFIG_SND_RK29_SOC_I2S) += snd-soc-rockchip-i2s.o
# ROCKCHIP Machine Support
snd-soc-wm8900-objs := rk29_wm8900.o
snd-soc-alc5621-objs := rk29_alc5621.o
snd-soc-alc5631-objs := rk29_rt5631.o
snd-soc-wm8988-objs := rk29_wm8988.o
snd-soc-rk1000-objs := rk29_rk1000codec.o
snd-soc-wm8994-objs := rk29_wm8994.o
@@ -14,4 +16,6 @@ snd-soc-wm8994-objs := rk29_wm8994.o
obj-$(CONFIG_SND_RK29_SOC_WM8994) += snd-soc-wm8994.o
obj-$(CONFIG_SND_RK29_SOC_WM8988) += snd-soc-wm8988.o
obj-$(CONFIG_SND_RK29_SOC_WM8900) += snd-soc-wm8900.o
obj-$(CONFIG_SND_RK29_SOC_alc5621) += snd-soc-alc5621.o
obj-$(CONFIG_SND_RK29_SOC_alc5631) += snd-soc-alc5631.o
obj-$(CONFIG_SND_RK29_SOC_RK1000) += snd-soc-rk1000.o

249
sound/soc/rk29/rk29_alc5621.c Normal file
View File

@@ -0,0 +1,249 @@
/*
* rk29_wm8900.c -- SoC audio for rockchip
*
* Driver for rockchip alc5623 audio
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*
*/
#include <linux/module.h>
#include <linux/device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <asm/io.h>
#include <mach/hardware.h>
#include <mach/rk29_iomap.h>
#include "../codecs/alc5621.h"
#include "rk29_pcm.h"
#include "rk29_i2s.h"
#if 1
#define DBG(x...) printk(KERN_INFO x)
#else
#define DBG(x...)
#endif
static int rk29_hw_params_alc5623(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
unsigned int pll_out = 0i,sys_clk;
int ret;
DBG("rk29_hw_params for rk29_alc5623\n");
/*by Vincent Hsiung for EQ Vol Change*/
#define HW_PARAMS_FLAG_EQVOL_ON 0x21
#define HW_PARAMS_FLAG_EQVOL_OFF 0x22
if ((params->flags == HW_PARAMS_FLAG_EQVOL_ON)||(params->flags == HW_PARAMS_FLAG_EQVOL_OFF))
{
ret = codec_dai->ops->hw_params(substream, params, codec_dai); //by Vincent
DBG("rk29_hw_params set EQ vol for rk29_alc5623\n");
}
else
{
/* set codec DAI configuration for codec side */
#if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE)
DBG("rk29_hw_params for rk29_alc5623 codec as slave\n");
ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
#endif
#if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER)
ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM );
#endif
if (ret < 0)return ret;
/* set cpu DAI configuration */
#if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE)
DBG("rk29_hw_params for rk29_alc5623 cpu as master\n");
ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
#endif
#if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER)
ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
#endif
if (ret < 0)return ret;
}
switch(params_rate(params)) {
case 8000:
sys_clk= 12288000;
pll_out = 12288000;
break;
case 16000:
sys_clk= 11289600;
pll_out = 12288000;
break;
case 24000:
sys_clk = 24576000;
pll_out = 12288000;
break;
case 32000:
sys_clk= 12288000;
pll_out = 12288000;
case 48000:
sys_clk = 12288000;
pll_out = 12288000;
break;
/*------------------------------*/
case 11025:
sys_clk = 11289600;
pll_out = 11289600;
break;
case 22050:
sys_clk = 11289600;
pll_out = 11289600;
break;
case 44100:
sys_clk = 11289600;
pll_out = 11289600;
break;
default:
DBG("rk29_hw_params for rk29_alc5623,invalid sapmleRate:%d\n",params_rate(params));
return -EINVAL;
break;
}
DBG("rk29_hw_params for rk29_alc5623, sapmleRate:%d\n",params_rate(params));
/*Set the system clk for codec*/
ret=snd_soc_dai_set_sysclk(codec_dai, 0,sys_clk,SND_SOC_CLOCK_IN);//ALC5621 system clk from MCLK or PLL
if (ret < 0)
{
DBG("rk29_hw_params_alc5623:failed to set the sysclk for codec side\n");
return ret;
}
/*Set the pll of alc5621,the Pll source from MCLK no matter slave or master mode*/
ret=snd_soc_dai_set_pll(codec_dai,RT5621_PLL_FR_BCLK,params_rate(params)*64,sys_clk);
if (ret < 0)
{
DBG("rk29_hw_params_alc5623:failed to set the pll for codec side\n");
return ret;
}
#if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER)
snd_soc_dai_set_clkdiv(codec_dai, ALC5623_BCLK_DIV, ALC5623_BCLK_DIV_4);
snd_soc_dai_set_clkdiv(codec_dai, ALC5623_DAC_LRCLK,(pll_out/4)/params_rate(params));
snd_soc_dai_set_clkdiv(codec_dai, ALC5623_ADC_LRCLK,(pll_out/4)/params_rate(params));
#endif
#if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE)
snd_soc_dai_set_sysclk(cpu_dai, 0, pll_out, 0);
snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_BCLK, (pll_out/4)/params_rate(params)-1);
snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_MCLK, 3);
#endif
DBG("rk29_hw_params_alc5623:,LRCK=%d\n",(pll_out/4)/params_rate(params));
return 0;
}
static const struct snd_soc_dapm_widget alc5623_dapm_widgets[] = {
SND_SOC_DAPM_LINE("Audio Out", NULL),
SND_SOC_DAPM_LINE("Line in", NULL),
SND_SOC_DAPM_MIC("Micn", NULL),
SND_SOC_DAPM_MIC("Micp", NULL),
};
static const struct snd_soc_dapm_route audio_map[]= {
{"Audio Out", NULL, "HP_L"},
{"Audio Out", NULL, "HP_R"},
{"Line in", NULL, "RINPUT1"},
{"Line in", NULL, "LINPUT1"},
{"Micn", NULL, "RINPUT2"},
{"Micp", NULL, "LINPUT2"},
};
/*
* Logic for a wm8900 as connected on a rockchip board.
*/
static int rk29_alc5623_init(struct snd_soc_codec *codec)
{
DBG("rk29_alc5623_init\n");
/* Add specific widgets */
snd_soc_dapm_new_controls(codec, alc5623_dapm_widgets, ARRAY_SIZE(alc5623_dapm_widgets));
/* Set up specific audio path audio_mapnects */
snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
snd_soc_dapm_nc_pin(codec, "HP_L");
snd_soc_dapm_nc_pin(codec, "HP_R");
snd_soc_dapm_sync(codec);
DBG("rk29_alc5623_init end\n");
return 0;
}
static struct snd_soc_ops rk29_ops = {
.hw_params = rk29_hw_params_alc5623,
};
static struct snd_soc_dai_link rk29_dai_alc5623 = {
.name = "ALC5623",
.stream_name = "ALC5623 PCM",
.cpu_dai = &rk29_i2s_dai[0],
.codec_dai = &rt5621_dai,
.init = rk29_alc5623_init,
.ops = &rk29_ops,
};
static struct snd_soc_card snd_soc_card_rk29_alc5623 = {
.name = "RK29_ALC5623",
.platform = &rk29_soc_platform,
.dai_link = &rk29_dai_alc5623,
.num_links = 1,
};
static struct snd_soc_device rk29_snd_devdata_alc5623 = {
.card = &snd_soc_card_rk29_alc5623,
.codec_dev = &soc_codec_dev_rt5621,
};
static struct platform_device *rk29_snd_device_alc5623;
static int __init audio_card_init_alc5623(void)
{
int ret =0;
DBG("audio_card_init_alc5623\n");
rk29_snd_device_alc5623 = platform_device_alloc("soc-audio", -1);
if (!rk29_snd_device_alc5623) {
DBG("audio_card_init_alc5623:platform device allocation failed\n");
ret = -ENOMEM;
return ret;
}
platform_set_drvdata(rk29_snd_device_alc5623, &rk29_snd_devdata_alc5623);
rk29_snd_devdata_alc5623.dev = &rk29_snd_device_alc5623->dev;
ret = platform_device_add(rk29_snd_device_alc5623);
if (ret) {
DBG("audio_card_init_alc5623:platform device add failed\n");
platform_device_put(rk29_snd_device_alc5623);
}
return ret;
}
static void __exit audio_card_exit_alc5623(void)
{
platform_device_unregister(rk29_snd_device_alc5623);
}
module_init(audio_card_init_alc5623);
module_exit(audio_card_exit_alc5623);
/* Module information */
MODULE_AUTHOR("rockchip");
MODULE_DESCRIPTION("ROCKCHIP i2s ASoC Interface");
MODULE_LICENSE("GPL");

161
sound/soc/rk29/rk29_i2s.c Executable file → Normal file
View File

@@ -123,86 +123,93 @@ static struct rockchip_pcm_dma_params rockchip_i2s_pcm_stereo_in[MAX_I2S] = {
/*
*Turn on or off the transmission path.
*/
static int flag_i2s_tx = 0;
static int flag_i2s_rx = 0;
static void rockchip_snd_txctrl(struct rk29_i2s_info *i2s, int on)
{
u32 opr,xfer,fifosts;
int xor=0;
u32 opr,xfer,fifosts;
opr = readl(&(pheadi2s->I2S_DMACR));
xfer = readl(&(pheadi2s->I2S_XFER));
opr &= ~I2S_TRAN_DMA_ENABLE;
xfer &= ~I2S_RX_TRAN_START;
xfer &= ~I2S_TX_TRAN_START;
opr = readl(&(pheadi2s->I2S_DMACR));
xfer = readl(&(pheadi2s->I2S_XFER));
if(xfer & I2S_RX_TRAN_START) {
xor = 1;
}
if (on)
{
I2S_DBG("rockchip_snd_txctrl: on\n");
opr &= ~I2S_TRAN_DMA_ENABLE;
xfer &= ~I2S_TX_TRAN_START;
//stop tx
if ((flag_i2s_rx == 0) && (flag_i2s_tx == 0))
writel(xfer, &(pheadi2s->I2S_XFER));
writel(opr, &(pheadi2s->I2S_DMACR));
//start tx
opr |= I2S_TRAN_DMA_ENABLE;
xfer |= I2S_TX_TRAN_START;
xfer |= I2S_RX_TRAN_START;
writel(opr, &(pheadi2s->I2S_DMACR));
writel(xfer, &(pheadi2s->I2S_XFER));
flag_i2s_tx = 1;
}
else
{
//stop tx
flag_i2s_tx = 0;
if (on)
{
if(xor) {
xfer &= ~I2S_RX_TRAN_START;
}
writel(0, &(pheadi2s->I2S_XFER));
writel(opr, &(pheadi2s->I2S_DMACR));
if ((flag_i2s_rx == 0) && (flag_i2s_tx == 0))
writel(xfer, &(pheadi2s->I2S_XFER));
udelay(5);
writel(opr, &(pheadi2s->I2S_DMACR));
opr |= I2S_TRAN_DMA_ENABLE;
xfer |= I2S_TX_TRAN_START;
if(xor) {
xfer |= I2S_RX_TRAN_START;
}
writel(opr, &(pheadi2s->I2S_DMACR));
writel(xfer, &(pheadi2s->I2S_XFER));
}
else
{
writel(xfer, &(pheadi2s->I2S_XFER));
udelay(5);
writel(opr, &(pheadi2s->I2S_DMACR));
}
I2S_DBG("Enter %s, %d, opr=0x%08X, xfer=0x%08X\n", __func__, __LINE__, opr, xfer);
I2S_DBG("rockchip_snd_txctrl: off\n");
}
}
static void rockchip_snd_rxctrl(struct rk29_i2s_info *i2s, int on)
{
u32 opr,xfer,fifosts;
int xor=0;
opr = readl(&(pheadi2s->I2S_DMACR));
xfer = readl(&(pheadi2s->I2S_XFER));
u32 opr,xfer,fifosts;
if(xfer & I2S_TX_TRAN_START){
xor = 1;
}
opr = readl(&(pheadi2s->I2S_DMACR));
xfer = readl(&(pheadi2s->I2S_XFER));
opr &= ~I2S_RECE_DMA_ENABLE;
xfer &= ~I2S_RX_TRAN_START;
xfer &= ~I2S_TX_TRAN_START;
if (on)
{
I2S_DBG("rockchip_snd_rxctrl: on\n");
//stop rx
if ((flag_i2s_rx == 0) && (flag_i2s_tx == 0))
writel(xfer, &(pheadi2s->I2S_XFER));
writel(opr, &(pheadi2s->I2S_DMACR));
//start rx
opr |= I2S_RECE_DMA_ENABLE;
xfer |= I2S_TX_TRAN_START;
xfer |= I2S_RX_TRAN_START;
writel(opr, &(pheadi2s->I2S_DMACR));
writel(xfer, &(pheadi2s->I2S_XFER));
flag_i2s_rx = 1;
}
else
{
//stop rx
flag_i2s_rx = 0;
opr &= ~I2S_RECE_DMA_ENABLE;
xfer &= ~I2S_RX_TRAN_START;
if (on)
{
if(xor) {
xfer &= ~I2S_TX_TRAN_START;
}
writel(0, &(pheadi2s->I2S_XFER));
writel(opr, &(pheadi2s->I2S_DMACR));
opr |= I2S_RECE_DMA_ENABLE;
xfer |= I2S_RX_TRAN_START;
if(xor) {
xfer |= I2S_TX_TRAN_START;
}
writel(opr, &(pheadi2s->I2S_DMACR));
writel(xfer, &(pheadi2s->I2S_XFER));
}
else
{
writel(xfer, &(pheadi2s->I2S_XFER));
udelay(5);
writel(opr, &(pheadi2s->I2S_DMACR));
}
I2S_DBG("Enter %s, %d, opr=0x%08X, xfer=0x%08X\n", __func__, __LINE__, opr, xfer);
if ((flag_i2s_rx == 0) && (flag_i2s_tx == 0))
writel(xfer, &(pheadi2s->I2S_XFER));
udelay(5);
writel(opr, &(pheadi2s->I2S_DMACR));
I2S_DBG("rockchip_snd_rxctrl: off\n");
}
}
/*
@@ -569,8 +576,6 @@ static int __devinit rockchip_i2s_probe(struct platform_device *pdev)
{
struct rk29_i2s_info *i2s;
struct snd_soc_dai *dai;
struct clk *general_pll;
unsigned long i2smclk;
int ret;
I2S_DBG("Enter %s, %d pdev->id = %d >>>>>>>>>>>\n", __func__, __LINE__, pdev->id);
@@ -633,21 +638,7 @@ static int __devinit rockchip_i2s_probe(struct platform_device *pdev)
}
clk_enable(i2s->iis_clk);
general_pll=clk_get(NULL, "general_pll");
if(clk_get_rate(general_pll)>260000000)
{
i2smclk=11289600;
}
else if(clk_get_rate(general_pll)>130000000)
{
i2smclk=11289600/2;
}
else
{
i2smclk=11289600/4;
}
I2S_DBG("func is %s,general pll=%ld,mclk=%ld\n",__FUNCTION__,clk_get_rate(general_pll),i2smclk);
clk_set_rate(i2s->iis_clk, i2smclk);
clk_set_rate(i2s->iis_clk, 11289600);
ret = rk29_i2s_probe(pdev, dai, i2s, 0);
if (ret)
goto err_clk;

258
sound/soc/rk29/rk29_rt5631.c Normal file
View File

@@ -0,0 +1,258 @@
/*
* rk29_rt5631.c -- SoC audio for rockchip
*
* Driver for rockchip rt5631 audio
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*
*/
#include <linux/module.h>
#include <linux/device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <asm/io.h>
#include <mach/hardware.h>
#include <mach/rk29_iomap.h>
#include "../codecs/rt5631.h"
#include "rk29_pcm.h"
#include "rk29_i2s.h"
#if 0
#define DBG(x...) printk(KERN_INFO x)
#else
#define DBG(x...)
#endif
static int rk29_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
unsigned int pll_out = 0;
unsigned int lrclk = 0;
int ret;
DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
/*by Vincent Hsiung for EQ Vol Change*/
#define HW_PARAMS_FLAG_EQVOL_ON 0x21
#define HW_PARAMS_FLAG_EQVOL_OFF 0x22
if ((params->flags == HW_PARAMS_FLAG_EQVOL_ON)||(params->flags == HW_PARAMS_FLAG_EQVOL_OFF))
{
ret = codec_dai->ops->hw_params(substream, params, codec_dai); //by Vincent
DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
}
else
{
/* set codec DAI configuration */
#if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE)
ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
#endif
#if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER)
ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM );
#endif
if (ret < 0)
return ret;
/* set cpu DAI configuration */
#if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE)
ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
#endif
#if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER)
ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
#endif
if (ret < 0)
return ret;
}
switch(params_rate(params)) {
case 8000:
case 16000:
case 24000:
case 32000:
case 48000:
pll_out = 12288000;
break;
case 11025:
case 22050:
case 44100:
pll_out = 11289600;
break;
default:
DBG("Enter:%s, %d, Error rate=%d\n",__FUNCTION__,__LINE__,params_rate(params));
return -EINVAL;
break;
}
DBG("Enter:%s, %d, rate=%d\n",__FUNCTION__,__LINE__,params_rate(params));
#if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE)
#if 0 //use pll from blck
/*Set the pll of rt5631,the Pll source from BITCLK on CPU is master mode*/
//bitclk is 64fs
ret=snd_soc_dai_set_pll(codec_dai,0,params_rate(params)*64,pll_out);
if (ret < 0)
{
DBG("rk29_hw_params_rt5631:failed to set the pll for codec side\n");
return ret;
}
#endif
/*Set the system clk for codec*/
ret=snd_soc_dai_set_sysclk(codec_dai, 0,pll_out,SND_SOC_CLOCK_IN);
if (ret < 0)
{
DBG("rk29_hw_params_rt5631:failed to set the sysclk for codec side\n");
return ret;
}
#endif
/*
#if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER)
if((24576000%params_rate(params))==0) //for 8k,16k,32k,48k
{
snd_soc_dai_set_pll(codec_dai,0,pll_out, 24576000);
snd_soc_dai_set_sysclk(codec_dai,0, 24576000, SND_SOC_CLOCK_IN);
}
else if((22579200%params_rate(params))==0) //for 11k,22k,44k
{
snd_soc_dai_set_pll(codec_dai,0,pll_out, 22579200);
snd_soc_dai_set_sysclk(codec_dai,0, 22579200, SND_SOC_CLOCK_IN);
}
#endif
*/
#if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE)
snd_soc_dai_set_sysclk(cpu_dai, 0, pll_out, 0);
snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_BCLK, (pll_out/4)/params_rate(params)-1);
snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_MCLK, 3);
#endif
DBG("Enter:%s, %d, LRCK=%d\n",__FUNCTION__,__LINE__,(pll_out/4)/params_rate(params));
return 0;
}
static const struct snd_soc_dapm_widget rt5631_dapm_widgets[] = {
SND_SOC_DAPM_MIC("Mic Jack", NULL),
SND_SOC_DAPM_SPK("Ext Spk", NULL),
SND_SOC_DAPM_HP("Headphone Jack", NULL),
};
static const struct snd_soc_dapm_route audio_map[]={
/* Mic Jack --> MIC_IN*/
{"Mic Bias1", NULL, "Mic Jack"},
{"MIC1", NULL, "Mic Bias1"},
/* HP_OUT --> Headphone Jack */
{"Headphone Jack", NULL, "HPOL"},
{"Headphone Jack", NULL, "HPOR"},
/* LINE_OUT --> Ext Speaker */
{"Ext Spk", NULL, "SPOL"},
{"Ext Spk", NULL, "SPOR"},
} ;
/*
* Logic for a rt5631 as connected on a rockchip board.
*/
static int rk29_rt5631_init(struct snd_soc_codec *codec)
{
struct snd_soc_dai *codec_dai = &codec->dai[0];
int ret;
DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
/* Add specific widgets */
snd_soc_dapm_new_controls(codec, rt5631_dapm_widgets,
ARRAY_SIZE(rt5631_dapm_widgets));
DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
/* Set up specific audio path audio_mapnects */
snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
// snd_soc_dapm_nc_pin(codec, "HP_L");
DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
// snd_soc_dapm_nc_pin(codec, "HP_R");
DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
snd_soc_dapm_sync(codec);
DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
return 0;
}
static struct snd_soc_ops rk29_ops = {
.hw_params = rk29_hw_params,
};
static struct snd_soc_dai_link rk29_dai = {
.name = "RT5631",
.stream_name = "RT5631 PCM",
.cpu_dai = &rk29_i2s_dai[0],
.codec_dai = &rt5631_dai,
.init = rk29_rt5631_init,
.ops = &rk29_ops,
};
static struct snd_soc_card snd_soc_card_rk29 = {
.name = "RK29_RT5631",
.platform = &rk29_soc_platform,
.dai_link = &rk29_dai,
.num_links = 1,
};
static struct snd_soc_device rk29_snd_devdata = {
.card = &snd_soc_card_rk29,
.codec_dev = &soc_codec_dev_rt5631,
};
static struct platform_device *rk29_snd_device;
static int __init audio_card_init(void)
{
int ret =0;
DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
rk29_snd_device = platform_device_alloc("soc-audio", -1);
if (!rk29_snd_device) {
DBG("platform device allocation failed\n");
ret = -ENOMEM;
return ret;
}
platform_set_drvdata(rk29_snd_device, &rk29_snd_devdata);
rk29_snd_devdata.dev = &rk29_snd_device->dev;
ret = platform_device_add(rk29_snd_device);
if (ret) {
DBG("platform device add failed\n");
platform_device_put(rk29_snd_device);
}
return ret;
}
static void __exit audio_card_exit(void)
{
platform_device_unregister(rk29_snd_device);
}
module_init(audio_card_init);
module_exit(audio_card_exit);
/* Module information */
MODULE_AUTHOR("rockchip");
MODULE_DESCRIPTION("ROCKCHIP i2s ASoC Interface");
MODULE_LICENSE("GPL");