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drm/rockchip: dsi: fix phy power-on sequence

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Change-Id: I0ceaedb71776747e8951a75409bcc2521252dd18
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
2018-05-21 08:30:44 +08:00
committed by Tao Huang
parent 2c659c75a6
commit 1df398e95a
1 changed files with 49 additions and 10 deletions
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59
drivers/gpu/drm/rockchip/dw-mipi-dsi.c
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@@ -173,14 +173,10 @@
#define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
#define DSI_PHY_RSTZ 0xa0 #define DSI_PHY_RSTZ 0xa0
#define PHY_DISFORCEPLL 0
#define PHY_ENFORCEPLL BIT(3) #define PHY_ENFORCEPLL BIT(3)
#define PHY_DISABLECLK 0
#define PHY_ENABLECLK BIT(2) #define PHY_ENABLECLK BIT(2)
#define PHY_RSTZ 0 #define PHY_RSTZ BIT(1)
#define PHY_UNRSTZ BIT(1) #define PHY_SHUTDOWNZ BIT(0)
#define PHY_SHUTDOWNZ 0
#define PHY_UNSHUTDOWNZ BIT(0)
#define DSI_PHY_IF_CFG 0xa4 #define DSI_PHY_IF_CFG 0xa4
#define N_LANES(n) ((((n) - 1) & 0x3) << 0) #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
@@ -480,6 +476,44 @@ static int genif_wait_write_fifo_empty(struct dw_mipi_dsi *dsi)
return 0; return 0;
} }
static inline void mipi_dphy_enableclk_assert(struct dw_mipi_dsi *dsi)
{
regmap_update_bits(dsi->regmap, DSI_PHY_RSTZ,
PHY_ENABLECLK, PHY_ENABLECLK);
udelay(1);
}
static inline void mipi_dphy_enableclk_deassert(struct dw_mipi_dsi *dsi)
{
regmap_update_bits(dsi->regmap, DSI_PHY_RSTZ, PHY_ENABLECLK, 0);
udelay(1);
}
static inline void mipi_dphy_shutdownz_assert(struct dw_mipi_dsi *dsi)
{
regmap_update_bits(dsi->regmap, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0);
udelay(1);
}
static inline void mipi_dphy_shutdownz_deassert(struct dw_mipi_dsi *dsi)
{
regmap_update_bits(dsi->regmap, DSI_PHY_RSTZ,
PHY_SHUTDOWNZ, PHY_SHUTDOWNZ);
udelay(1);
}
static inline void mipi_dphy_rstz_assert(struct dw_mipi_dsi *dsi)
{
regmap_update_bits(dsi->regmap, DSI_PHY_RSTZ, PHY_RSTZ, 0);
udelay(1);
}
static inline void mipi_dphy_rstz_deassert(struct dw_mipi_dsi *dsi)
{
regmap_update_bits(dsi->regmap, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ);
udelay(1);
}
static inline void testif_testclk_assert(struct dw_mipi_dsi *dsi) static inline void testif_testclk_assert(struct dw_mipi_dsi *dsi)
{ {
regmap_update_bits(dsi->regmap, DSI_PHY_TST_CTRL0, regmap_update_bits(dsi->regmap, DSI_PHY_TST_CTRL0,
@@ -583,8 +617,8 @@ static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi)
unsigned int val, mask; unsigned int val, mask;
int ret; int ret;
regmap_write(dsi->regmap, DSI_PHY_RSTZ, PHY_ENFORCEPLL | mipi_dphy_shutdownz_deassert(dsi);
PHY_ENABLECLK | PHY_UNRSTZ | PHY_UNSHUTDOWNZ); mipi_dphy_rstz_deassert(dsi);
usleep_range(1500, 2000); usleep_range(1500, 2000);
if (dsi->dphy.phy) if (dsi->dphy.phy)
@@ -598,6 +632,8 @@ static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi)
return ret; return ret;
} }
usleep_range(100, 200);
mask = PHY_STOPSTATELANE; mask = PHY_STOPSTATELANE;
ret = regmap_read_poll_timeout(dsi->regmap, DSI_PHY_STATUS, ret = regmap_read_poll_timeout(dsi->regmap, DSI_PHY_STATUS,
val, (val & mask) == mask, val, (val & mask) == mask,
@@ -1002,6 +1038,9 @@ static void mipi_dphy_init(struct dw_mipi_dsi *dsi)
{ {
u32 map[] = {0x1, 0x3, 0x7, 0xf}; u32 map[] = {0x1, 0x3, 0x7, 0xf};
mipi_dphy_shutdownz_assert(dsi);
mipi_dphy_rstz_assert(dsi);
/* Configures DPHY to work as a Master */ /* Configures DPHY to work as a Master */
grf_field_write(dsi, MASTERSLAVEZ, 1); grf_field_write(dsi, MASTERSLAVEZ, 1);
@@ -1023,6 +1062,8 @@ static void mipi_dphy_init(struct dw_mipi_dsi *dsi)
/* Enable Clock Lane Module */ /* Enable Clock Lane Module */
grf_field_write(dsi, ENABLECLK, 1); grf_field_write(dsi, ENABLECLK, 1);
mipi_dphy_enableclk_assert(dsi);
} }
static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
@@ -1030,8 +1071,6 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
u32 esc_clk_div; u32 esc_clk_div;
regmap_write(dsi->regmap, DSI_PWR_UP, RESET); regmap_write(dsi->regmap, DSI_PWR_UP, RESET);
regmap_write(dsi->regmap, DSI_PHY_RSTZ, PHY_DISFORCEPLL |
PHY_DISABLECLK | PHY_RSTZ | PHY_SHUTDOWNZ);
/* The maximum value of the escape clock frequency is 20MHz */ /* The maximum value of the escape clock frequency is 20MHz */
esc_clk_div = DIV_ROUND_UP(dsi->lane_mbps >> 3, 20); esc_clk_div = DIV_ROUND_UP(dsi->lane_mbps >> 3, 20);