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UPSTREAM: arm64: errata: Add newer ARM cores to the spectre_bhb_loop_affected() lists
commit a5951389e58d2e816eed3dbec5877de9327fd881 upstream. When comparing to the ARM list [1], it appears that several ARM cores were missing from the lists in spectre_bhb_loop_affected(). Add them. NOTE: for some of these cores it may not matter since other ways of clearing the BHB may be used (like the CLRBHB instruction or ECBHB), but it still seems good to have all the info from ARM's whitepaper included. [1] https://developer.arm.com/Arm%20Security%20Center/Spectre-BHB Fixes:558c303c97("arm64: Mitigate spectre style branch history side channels") Cc: stable@vger.kernel.org Change-Id: I4c4178a7d4883cf3cd02fc7c83569b438cfd9a08 Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: James Morse <james.morse@arm.com> Link: https://lore.kernel.org/r/20250107120555.v4.5.I4a9a527e03f663040721c5401c41de587d015c82@changeid Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commita53b3599d9) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
4c7f06c5da
commit
1e50e672f2
@@ -911,6 +911,7 @@ static u8 spectre_bhb_loop_affected(void)
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};
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static const struct midr_range spectre_bhb_k24_list[] = {
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A76AE),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
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MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_GOLD),
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@@ -926,7 +927,11 @@ static u8 spectre_bhb_loop_affected(void)
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{},
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};
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if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k32_list))
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if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k132_list))
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k = 132;
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else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k38_list))
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k = 38;
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else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k32_list))
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k = 32;
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else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k24_list))
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k = 24;
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