From 1e72e1fb4093ee841f5ca510d3d8bc3df139355f Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Thu, 17 Sep 2020 11:32:25 +0800 Subject: [PATCH] video/rockchip: rga2: Support A+B->C blend mode. The mode A is src, B is src1, and C is dst. Signed-off-by: Yu Qiaowei Change-Id: I124665d7b727d921b33c0efbe5f3b048141a3879 --- drivers/video/rockchip/rga2/rga2_drv.c | 9 ++++++ drivers/video/rockchip/rga2/rga2_mmu_info.c | 2 +- drivers/video/rockchip/rga2/rga2_reg_info.c | 31 +++++++++++++-------- drivers/video/rockchip/rga2/rga2_reg_info.h | 4 +++ 4 files changed, 34 insertions(+), 12 deletions(-) diff --git a/drivers/video/rockchip/rga2/rga2_drv.c b/drivers/video/rockchip/rga2/rga2_drv.c index 6f9a44960fc3..2a16b22dd42f 100644 --- a/drivers/video/rockchip/rga2/rga2_drv.c +++ b/drivers/video/rockchip/rga2/rga2_drv.c @@ -318,6 +318,15 @@ static void print_debug_info(struct rga2_req *req) req->src.act_w, req->src.act_h, req->src.vir_w, req->src.vir_h, req->src.x_offset, req->src.y_offset, rga2_get_format_name(req->src.format)); + if (req->src1.yrgb_addr != 0 || + req->src1.uv_addr != 0 || + req->src1.v_addr != 0) { + INFO("src1 : y=%lx uv=%lx v=%lx aw=%d ah=%d vw=%d vh=%d xoff=%d yoff=%d format=%s\n", + req->src1.yrgb_addr, req->src1.uv_addr, req->src1.v_addr, + req->src1.act_w, req->src1.act_h, req->src1.vir_w, req->src1.vir_h, + req->src1.x_offset, req->src1.y_offset, + rga2_get_format_name(req->src1.format)); + } INFO("dst : y=%lx uv=%lx v=%lx aw=%d ah=%d vw=%d vh=%d xoff=%d yoff=%d format=%s\n", req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr, req->dst.act_w, req->dst.act_h, req->dst.vir_w, req->dst.vir_h, diff --git a/drivers/video/rockchip/rga2/rga2_mmu_info.c b/drivers/video/rockchip/rga2/rga2_mmu_info.c index 22cfd8a13ed8..6c5d2f356ac3 100644 --- a/drivers/video/rockchip/rga2/rga2_mmu_info.c +++ b/drivers/video/rockchip/rga2/rga2_mmu_info.c @@ -749,7 +749,7 @@ static int rga2_mmu_info_BitBlt_mode(struct rga2_reg *reg, struct rga2_req *req) /* change the buf address in req struct */ req->mmu_info.src1_base_addr = ((unsigned long)(MMU_Base_phys + Src0MemSize)); - req->src1.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)); + req->src1.yrgb_addr = (req->src1.yrgb_addr & (~PAGE_MASK)); } if (DstMemSize) { if (req->sg_dst) { diff --git a/drivers/video/rockchip/rga2/rga2_reg_info.c b/drivers/video/rockchip/rga2/rga2_reg_info.c index 0d2962455b4d..dcb74e389d0a 100644 --- a/drivers/video/rockchip/rga2/rga2_reg_info.c +++ b/drivers/video/rockchip/rga2/rga2_reg_info.c @@ -266,13 +266,7 @@ static void RGA2_set_reg_src_info(RK_U8 *base, struct rga2_req *msg) reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP)) | (s_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP(src0_rb_swp))); reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP)) | (s_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP(msg->alpha_swp))); reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP)) | (s_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP(src0_cbcr_swp))); - if(msg->src.format <= RGA2_FORMAT_BGRA_4444) - reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE(0))); - else - if(msg->dst.format >= RGA2_FORMAT_YCbCr_422_SP) - reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE(0))); - else - reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE(msg->yuv2rgb_mode))); + reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE(msg->yuv2rgb_mode))); reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE(msg->rotate_mode & 0x3))); reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE((msg->rotate_mode >> 4) & 0x3))); @@ -412,8 +406,11 @@ static void RGA2_set_reg_dst_info(u8 *base, struct rga2_req *msg) reg = ((reg & (~m_RGA2_DST_INFO_SW_DITHER_UP_E)) | (s_RGA2_DST_INFO_SW_DITHER_UP_E(msg->alpha_rop_flag >> 5))); reg = ((reg & (~m_RGA2_DST_INFO_SW_DITHER_DOWN_E)) | (s_RGA2_DST_INFO_SW_DITHER_DOWN_E(msg->alpha_rop_flag >> 6))); reg = ((reg & (~m_RGA2_DST_INFO_SW_DITHER_MODE)) | (s_RGA2_DST_INFO_SW_DITHER_MODE(msg->dither_mode))); - reg = ((reg & (~m_RGA2_DST_INFO_SW_DST_CSC_MODE)) | (s_RGA2_DST_INFO_SW_DST_CSC_MODE(msg->yuv2rgb_mode >> 4))); - reg = ((reg & (~m_RGA2_DST_INFO_SW_CSC_CLIP_MODE)) | (s_RGA2_DST_INFO_SW_CSC_CLIP_MODE(msg->yuv2rgb_mode >> 6))); + reg = ((reg & (~m_RGA2_DST_INFO_SW_DST_CSC_MODE)) | (s_RGA2_DST_INFO_SW_DST_CSC_MODE(msg->yuv2rgb_mode >> 2))); + reg = ((reg & (~m_RGA2_DST_INFO_SW_CSC_CLIP_MODE)) | (s_RGA2_DST_INFO_SW_CSC_CLIP_MODE(msg->yuv2rgb_mode >> 4))); + /* Some older chips do not support src1 csc mode, they do not have these two registers. */ + reg = ((reg & (~m_RGA2_DST_INFO_SW_SRC1_CSC_MODE)) | (s_RGA2_DST_INFO_SW_SRC1_CSC_MODE(msg->yuv2rgb_mode >> 5))); + reg = ((reg & (~m_RGA2_DST_INFO_SW_SRC1_CSC_CLIP_MODE)) | (s_RGA2_DST_INFO_SW_SRC1_CSC_CLIP_MODE(msg->yuv2rgb_mode >> 7))); *bRGA_DST_INFO = reg; @@ -1048,6 +1045,7 @@ void RGA_MSG_2_RGA2_MSG(struct rga_req *req_rga, struct rga2_req *req) format_name_convert(&req->src.format, req_rga->src.format); format_name_convert(&req->dst.format, req_rga->dst.format); + format_name_convert(&req->src1.format, req_rga->pat.format); if(req_rga->rotate_mode == 1) { if(req_rga->sina == 0 && req_rga->cosa == 65536) { @@ -1111,7 +1109,10 @@ void RGA_MSG_2_RGA2_MSG(struct rga_req *req_rga, struct rga2_req *req) memcpy(&req->gr_color, &req_rga->gr_color, sizeof(req_rga->gr_color)); req->palette_mode = req_rga->palette_mode; - req->yuv2rgb_mode = req_rga->yuv2rgb_mode + 1; + if ((req_rga->yuv2rgb_mode & 0x3) != 0) + req->yuv2rgb_mode = req_rga->yuv2rgb_mode + 1; + else + req->yuv2rgb_mode = req_rga->yuv2rgb_mode; req->endian_mode = req_rga->endian_mode; req->rgb2yuv_mode = 0; @@ -1224,6 +1225,11 @@ void RGA_MSG_2_RGA2_MSG(struct rga_req *req_rga, struct rga2_req *req) req->mmu_info.dst_mmu_flag = 0; req->dst.yrgb_addr = req_rga->dst.yrgb_addr - 0x60000000; } + + if (req_rga->pat.yrgb_addr >= 0xa0000000) { + req->mmu_info.src1_mmu_flag = 0; + req->src1.yrgb_addr = req_rga->pat.yrgb_addr - 0x60000000; + } } } } @@ -1318,7 +1324,10 @@ void RGA_MSG_2_RGA2_MSG_32(struct rga_req_32 *req_rga, struct rga2_req *req) req->bg_color = req_rga->bg_color; memcpy(&req->gr_color, &req_rga->gr_color, sizeof(req_rga->gr_color)); req->palette_mode = req_rga->palette_mode; - req->yuv2rgb_mode = req_rga->yuv2rgb_mode + 1; + if ((req_rga->yuv2rgb_mode & 0x3) != 0) + req->yuv2rgb_mode = req_rga->yuv2rgb_mode + 1; + else + req->yuv2rgb_mode = req_rga->yuv2rgb_mode; req->endian_mode = req_rga->endian_mode; req->rgb2yuv_mode = 0; req->fading_alpha_value = 0; diff --git a/drivers/video/rockchip/rga2/rga2_reg_info.h b/drivers/video/rockchip/rga2/rga2_reg_info.h index 586603e5ca92..bd525a97dd72 100644 --- a/drivers/video/rockchip/rga2/rga2_reg_info.h +++ b/drivers/video/rockchip/rga2/rga2_reg_info.h @@ -142,6 +142,8 @@ #define m_RGA2_DST_INFO_SW_DITHER_MODE ( 0x3<<14) #define m_RGA2_DST_INFO_SW_DST_CSC_MODE ( 0x3<<16) //add #define m_RGA2_DST_INFO_SW_CSC_CLIP_MODE ( 0x1<<18) +#define m_RGA2_DST_INFO_SW_SRC1_CSC_MODE ( 0x3<<20) //add +#define m_RGA2_DST_INFO_SW_SRC1_CSC_CLIP_MODE ( 0x1<<22) #define s_RGA2_DST_INFO_SW_DST_FMT(x) ( (x&0xf)<<0 ) #define s_RGA2_DST_INFO_SW_DST_RB_SWAP(x) ( (x&0x1)<<4 ) @@ -155,6 +157,8 @@ #define s_RGA2_DST_INFO_SW_DITHER_MODE(x) ( (x&0x3)<<14) #define s_RGA2_DST_INFO_SW_DST_CSC_MODE(x) ( (x&0x3)<<16) //add #define s_RGA2_DST_INFO_SW_CSC_CLIP_MODE(x) ( (x&0x1)<<18) +#define s_RGA2_DST_INFO_SW_SRC1_CSC_MODE(x) ( (x&0x3)<<20) //add +#define s_RGA2_DST_INFO_SW_SRC1_CSC_CLIP_MODE(x) ( (x&0x1)<<22) /* RGA_ALPHA_CTRL0 */