From 1ea14f41e66aa157c86b891a038934ead3b78ca6 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Mon, 20 Mar 2023 09:06:05 +0800 Subject: [PATCH] drm/rockchip: vop3: rk3562: remove unused defined Signed-off-by: Sandy Huang Change-Id: Ibe0b2e3ce9358c8509630aa00167264f675fa7c3 --- drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 64 -------------------- 1 file changed, 64 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index d9aae6a98560..fadb52c659c1 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -1029,70 +1029,6 @@ static const struct vop2_video_port_regs rk3562_vop_vp0_regs = { .layer_sel = VOP_REG(RK3528_OVL_PORT0_LAYER_SEL, 0xffff, 0), }; -static const struct vop2_video_port_regs rk3562_vop_vp1_regs = { - .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 1), - .overlay_mode = VOP_REG(RK3528_OVL_PORT1_CTRL, 0x1, 0), - .dsp_background = VOP_REG(RK3568_VP1_DSP_BG, 0xffffffff, 0), - .out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0), - .core_dclk_div = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 4), - .p2i_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 5), - .dsp_filed_pol = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 6), - .dsp_interlace = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 7), - .dsp_data_swap = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1f, 8), - .dsp_x_mir_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 13), - .post_dsp_out_r2y = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 15), - .pre_dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 16), - .dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17), - .dither_down_sel = VOP_REG(RK3568_VP1_DSP_CTRL, 0x3, 18), - .dither_down_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 20), - .gamma_update_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 22), - .dsp_lut_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 28), - .standby = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31), - .bg_mix_ctrl = VOP_REG(RK3528_OVL_PORT1_BG_MIX_CTRL, 0xffff, 0), - .bg_dly = VOP_REG(RK3528_OVL_PORT1_BG_MIX_CTRL, 0xff, 24), - .pre_scan_htiming = VOP_REG(RK3568_VP1_PRE_SCAN_HTIMING, 0x1fff1fff, 0), - .hpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_HACT_INFO, 0x1fff1fff, 0), - .vpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO, 0x1fff1fff, 0), - .post_scl_factor = VOP_REG(RK3568_VP1_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), - .post_scl_ctrl = VOP_REG(RK3568_VP1_POST_SCL_CTRL, 0x3, 0), - .htotal_pw = VOP_REG(RK3568_VP1_DSP_HTOTAL_HS_END, 0xffffffff, 0), - .hact_st_end = VOP_REG(RK3568_VP1_DSP_HACT_ST_END, 0xffffffff, 0), - .dsp_vtotal = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 16), - .sw_dsp_vtotal_imd = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1, 15), - .dsp_vs_end = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 0), - .vact_st_end = VOP_REG(RK3568_VP1_DSP_VACT_ST_END, 0x1fff1fff, 0), - .vact_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), - .vs_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VS_ST_END_F1, 0x1fff1fff, 0), - .vpost_st_end_f1 = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), - .bcsh_brightness = VOP_REG(RK3568_VP1_BCSH_BCS, 0xff, 0), - .bcsh_contrast = VOP_REG(RK3568_VP1_BCSH_BCS, 0x1ff, 8), - .bcsh_sat_con = VOP_REG(RK3568_VP1_BCSH_BCS, 0x3ff, 20), - .bcsh_out_mode = VOP_REG(RK3568_VP1_BCSH_BCS, 0x3, 30), - .bcsh_sin_hue = VOP_REG(RK3568_VP1_BCSH_H, 0x1ff, 0), - .bcsh_cos_hue = VOP_REG(RK3568_VP1_BCSH_H, 0x1ff, 16), - .bcsh_r2y_csc_mode = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x3, 6), - .bcsh_r2y_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 4), - .bcsh_y2r_csc_mode = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x3, 2), - .bcsh_y2r_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 0), - .bcsh_en = VOP_REG(RK3568_VP1_BCSH_COLOR_BAR, 0x1, 31), - .edpi_te_en = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 28), - .edpi_wms_hold_en = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 30), - .edpi_wms_fs = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 31), - .lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4), - .mcu_pix_total = VOP_REG(RK3562_VP1_MCU_CTRL, 0x3f, 0), - .mcu_cs_pst = VOP_REG(RK3562_VP1_MCU_CTRL, 0xf, 6), - .mcu_cs_pend = VOP_REG(RK3562_VP1_MCU_CTRL, 0x3f, 10), - .mcu_rw_pst = VOP_REG(RK3562_VP1_MCU_CTRL, 0xf, 16), - .mcu_rw_pend = VOP_REG(RK3562_VP1_MCU_CTRL, 0x3f, 20), - .mcu_hold_mode = VOP_REG(RK3562_VP1_MCU_CTRL, 0x1, 27), - .mcu_frame_st = VOP_REG(RK3562_VP1_MCU_CTRL, 0x1, 28), - .mcu_rs = VOP_REG(RK3562_VP1_MCU_CTRL, 0x1, 29), - .mcu_bypass = VOP_REG(RK3562_VP1_MCU_CTRL, 0x1, 30), - .mcu_type = VOP_REG(RK3562_VP1_MCU_CTRL, 0x1, 31), - .mcu_rw_bypass_port = VOP_REG(RK3562_VP1_MCU_RW_BYPASS_PORT, 0xffffffff, 0), - .layer_sel = VOP_REG(RK3528_OVL_PORT1_LAYER_SEL, 0xffff, 0), -}; - static const struct vop2_video_port_data rk3562_vop_video_ports[] = { { .id = 0,