diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index f09f21a5aa1a..d78ec603cdf4 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -620,8 +620,8 @@ struct vop2_video_port_regs { struct vop_reg core_dclk_div; struct vop_reg p2i_en; - struct vop_reg mipi_dual_en; - struct vop_reg mipi_dual_channel_swap; + struct vop_reg dual_channel_en; + struct vop_reg dual_channel_swap; struct vop_reg dsp_lut_en; struct vop_reg dclk_div2; @@ -960,6 +960,10 @@ struct vop2_ctrl { struct vop_reg lvds_dual_mode; struct vop_reg lvds_dual_channel_swap; + struct vop_reg dp_dual_en; + struct vop_reg edp_dual_en; + struct vop_reg hdmi_dual_en; + struct vop_reg hdmi0_dclk_div; struct vop_reg hdmi0_pixclk_div; struct vop_reg edp0_dclk_div; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index cd8ab6ec1332..d0bd7cc73545 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -5157,6 +5157,32 @@ static void vop2_crtc_enable_dsc(struct drm_crtc *crtc, struct drm_crtc_state *o dsc->enabled = true; } +static void vop2_setup_dual_channel_if(struct drm_crtc *crtc) +{ + struct vop2_video_port *vp = to_vop2_video_port(crtc); + struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); + struct vop2 *vop2 = vp->vop2; + int output_type = vcstate->output_type; + + VOP_MODULE_SET(vop2, vp, dual_channel_en, 1); + if (vcstate->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) + VOP_MODULE_SET(vop2, vp, dual_channel_swap, 1); + + switch (output_type) { + case DRM_MODE_CONNECTOR_DisplayPort: + VOP_CTRL_SET(vop2, dp_dual_en, 1); + break; + case DRM_MODE_CONNECTOR_eDP: + VOP_CTRL_SET(vop2, edp_dual_en, 1); + break; + case DRM_MODE_CONNECTOR_HDMIA: + VOP_CTRL_SET(vop2, hdmi_dual_en, 1); + break; + default: + break; + } +} + /* * MIPI port mux on rk3588: * 0: Video Port2 @@ -5345,11 +5371,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state VOP_CTRL_SET(vop2, mipi_dclk_pol, dclk_inv); } - if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { - VOP_MODULE_SET(vop2, vp, mipi_dual_en, 1); - if (vcstate->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) - VOP_MODULE_SET(vop2, vp, mipi_dual_channel_swap, 1); - } + if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) + vop2_setup_dual_channel_if(crtc); if (vcstate->output_if & VOP_OUTPUT_IF_eDP0) { ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_eDP0, &if_pixclk, &if_dclk); diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index 1a2258fcd0bb..c2f5ce23aab3 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -630,8 +630,8 @@ static const struct vop2_video_port_regs rk3568_vop_vp0_regs = { .out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0), .standby = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31), .core_dclk_div = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 4), - .dclk_div2 = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 4), - .dclk_div2_phase_lock = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 5), + .dclk_div2 = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 4), + .dclk_div2_phase_lock = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 5), .p2i_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 5), .dsp_filed_pol = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 6), .dsp_interlace = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 7), @@ -654,8 +654,8 @@ static const struct vop2_video_port_regs rk3568_vop_vp0_regs = { .dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17), .dither_down_sel = VOP_REG(RK3568_VP0_DSP_CTRL, 0x3, 18), .dither_down_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 20), - .mipi_dual_en = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 20), - .mipi_dual_channel_swap = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 21), + .dual_channel_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 20), + .dual_channel_swap = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 21), .dsp_lut_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 28), .hdr10_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 4), .hdr_lut_update_en = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 0), @@ -712,8 +712,8 @@ static const struct vop2_video_port_regs rk3568_vop_vp1_regs = { .out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0), .standby = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31), .core_dclk_div = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 4), - .dclk_div2 = VOP_REG(RK3568_VP1_MIPI_CTRL, 0x1, 4), - .dclk_div2_phase_lock = VOP_REG(RK3568_VP1_MIPI_CTRL, 0x1, 5), + .dclk_div2 = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 4), + .dclk_div2_phase_lock = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 5), .p2i_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 5), .dsp_filed_pol = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 6), .dsp_interlace = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 7), @@ -736,8 +736,8 @@ static const struct vop2_video_port_regs rk3568_vop_vp1_regs = { .dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17), .dither_down_sel = VOP_REG(RK3568_VP1_DSP_CTRL, 0x3, 18), .dither_down_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 20), - .mipi_dual_en = VOP_REG(RK3568_VP1_MIPI_CTRL, 0x1, 20), - .mipi_dual_channel_swap = VOP_REG(RK3568_VP1_MIPI_CTRL, 0x1, 21), + .dual_channel_en = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 20), + .dual_channel_swap = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 21), .bcsh_brightness = VOP_REG(RK3568_VP1_BCSH_BCS, 0xff, 0), .bcsh_contrast = VOP_REG(RK3568_VP1_BCSH_BCS, 0x1ff, 8), @@ -761,8 +761,8 @@ static const struct vop2_video_port_regs rk3568_vop_vp2_regs = { .out_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0xf, 0), .standby = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 31), .core_dclk_div = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 4), - .dclk_div2 = VOP_REG(RK3568_VP2_MIPI_CTRL, 0x1, 4), - .dclk_div2_phase_lock = VOP_REG(RK3568_VP2_MIPI_CTRL, 0x1, 5), + .dclk_div2 = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 4), + .dclk_div2_phase_lock = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 5), .p2i_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 5), .dsp_filed_pol = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 6), .dsp_interlace = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 7), @@ -785,8 +785,8 @@ static const struct vop2_video_port_regs rk3568_vop_vp2_regs = { .dither_down_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 17), .dither_down_sel = VOP_REG(RK3568_VP2_DSP_CTRL, 0x3, 18), .dither_down_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 20), - .mipi_dual_en = VOP_REG(RK3568_VP2_MIPI_CTRL, 0x1, 20), - .mipi_dual_channel_swap = VOP_REG(RK3568_VP2_MIPI_CTRL, 0x1, 21), + .dual_channel_en = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 20), + .dual_channel_swap = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 21), .bcsh_brightness = VOP_REG(RK3568_VP2_BCSH_BCS, 0xff, 0), .bcsh_contrast = VOP_REG(RK3568_VP2_BCSH_BCS, 0x1ff, 8), @@ -872,8 +872,8 @@ static const struct vop2_video_port_regs rk3588_vop_vp0_regs = { .vact_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), .vs_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VS_ST_END_F1, 0x1fff1fff, 0), .vpost_st_end_f1 = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), - .mipi_dual_en = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 20), - .mipi_dual_channel_swap = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 21), + .dual_channel_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 20), + .dual_channel_swap = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 21), .hdr10_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 4), .hdr_lut_update_en = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 0), .hdr_lut_mode = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 1), @@ -954,8 +954,8 @@ static const struct vop2_video_port_regs rk3588_vop_vp1_regs = { .vact_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), .vs_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VS_ST_END_F1, 0x1fff1fff, 0), .vpost_st_end_f1 = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), - .mipi_dual_en = VOP_REG(RK3568_VP1_MIPI_CTRL, 0x1, 20), - .mipi_dual_channel_swap = VOP_REG(RK3568_VP1_MIPI_CTRL, 0x1, 21), + .dual_channel_en = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 20), + .dual_channel_swap = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 21), .hdr10_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 24), .hdr_lut_update_en = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 0), .hdr_lut_mode = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 1), @@ -1032,8 +1032,8 @@ static const struct vop2_video_port_regs rk3588_vop_vp2_regs = { .vact_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), .vs_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VS_ST_END_F1, 0x1fff1fff, 0), .vpost_st_end_f1 = VOP_REG(RK3568_VP2_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), - .mipi_dual_en = VOP_REG(RK3568_VP2_MIPI_CTRL, 0x1, 20), - .mipi_dual_channel_swap = VOP_REG(RK3568_VP2_MIPI_CTRL, 0x1, 21), + .dual_channel_en = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 20), + .dual_channel_swap = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 21), .bcsh_brightness = VOP_REG(RK3568_VP2_BCSH_BCS, 0xff, 0), .bcsh_contrast = VOP_REG(RK3568_VP2_BCSH_BCS, 0x1ff, 8), .bcsh_sat_con = VOP_REG(RK3568_VP2_BCSH_BCS, 0x3ff, 20), @@ -1080,8 +1080,8 @@ static const struct vop2_video_port_regs rk3588_vop_vp3_regs = { .vact_st_end_f1 = VOP_REG(RK3588_VP3_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), .vs_st_end_f1 = VOP_REG(RK3588_VP3_DSP_VS_ST_END_F1, 0x1fff1fff, 0), .vpost_st_end_f1 = VOP_REG(RK3588_VP3_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), - .mipi_dual_en = VOP_REG(RK3588_VP3_MIPI_CTRL, 0x1, 20), - .mipi_dual_channel_swap = VOP_REG(RK3588_VP3_MIPI_CTRL, 0x1, 21), + .dual_channel_en = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 20), + .dual_channel_swap = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 21), .bcsh_brightness = VOP_REG(RK3588_VP3_BCSH_BCS, 0xff, 0), .bcsh_contrast = VOP_REG(RK3588_VP3_BCSH_BCS, 0x1ff, 8), .bcsh_sat_con = VOP_REG(RK3588_VP3_BCSH_BCS, 0x3ff, 20), @@ -2398,6 +2398,9 @@ static const struct vop2_ctrl rk3588_vop_ctrl = { .mipi1_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 21), .bt656_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 1), .bt1120_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 5), + .hdmi_dual_en = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 8), + .edp_dual_en = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 8), + .dp_dual_en = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 9), .mipi0_ds_mode = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 11), .mipi1_ds_mode = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 12), .hdmi0_dclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 16), diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index d98010162547..b8c866cb8322 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -1108,7 +1108,7 @@ /* Video Port registers definition */ #define RK3568_VP0_DSP_CTRL 0xC00 -#define RK3568_VP0_MIPI_CTRL 0xC04 +#define RK3568_VP0_DUAL_CHANNEL_CTRL 0xC04 #define RK3568_VP0_COLOR_BAR_CTRL 0xC08 #define RK3568_VP0_CLK_CTRL 0xC0C #define RK3568_VP0_3D_LUT_CTRL 0xC10 @@ -1132,7 +1132,7 @@ #define RK3568_VP0_BCSH_COLOR_BAR 0xC6C #define RK3568_VP1_DSP_CTRL 0xD00 -#define RK3568_VP1_MIPI_CTRL 0xD04 +#define RK3568_VP1_DUAL_CHANNEL_CTRL 0xD04 #define RK3568_VP1_COLOR_BAR_CTRL 0xD08 #define RK3568_VP1_CLK_CTRL 0xD0C #define RK3568_VP1_DSP_BG 0xD2C @@ -1156,7 +1156,7 @@ #define RK3568_VP1_BCSH_COLOR_BAR 0xD6C #define RK3568_VP2_DSP_CTRL 0xE00 -#define RK3568_VP2_MIPI_CTRL 0xE04 +#define RK3568_VP2_DUAL_CHANNEL_CTRL 0xE04 #define RK3568_VP2_COLOR_BAR_CTRL 0xE08 #define RK3568_VP2_CLK_CTRL 0xE0C #define RK3568_VP2_DSP_BG 0xE2C @@ -1180,7 +1180,7 @@ #define RK3568_VP2_BCSH_COLOR_BAR 0xE6C #define RK3588_VP3_DSP_CTRL 0xF00 -#define RK3588_VP3_MIPI_CTRL 0xF04 +#define RK3588_VP3_DUAL_CHANNEL_CTRL 0xF04 #define RK3588_VP3_COLOR_BAR_CTRL 0xF08 #define RK3568_VP3_CLK_CTRL 0xF0C #define RK3588_VP3_DSP_BG 0xF2C