From 1f38917aebeea4cfab6954a8d77fd98d254a5558 Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Thu, 17 Nov 2022 15:12:17 +0800 Subject: [PATCH] ARM: dts: rockchip: rk3288: fix base address for i2s to 0xff8b0000 This patch fixes the error base address for the i2s controller from 0xff88b0000 to 0xff8b0000. Also order the i2s node by mapping address. Signed-off-by: Jianqun Xu Change-Id: I613eaf64ee010c41208f1c8169e55efbf39fd34c --- arch/arm/boot/dts/rk3288.dtsi | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 3aa3d3b8611d..966b4d968749 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1034,21 +1034,6 @@ status = "disabled"; }; - spdif: sound@ff88b0000 { - compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; - reg = <0x0 0xff8b0000 0x0 0x10000>; - #sound-dai-cells = <0>; - clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>; - clock-names = "mclk", "hclk"; - dmas = <&dmac_bus_s 3>; - dma-names = "tx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx>; - rockchip,grf = <&grf>; - status = "disabled"; - }; - i2s: i2s@ff890000 { compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff890000 0x0 0x10000>; @@ -1079,6 +1064,21 @@ status = "okay"; }; + spdif: sound@ff8b0000 { + compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; + reg = <0x0 0xff8b0000 0x0 0x10000>; + #sound-dai-cells = <0>; + clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac_bus_s 3>; + dma-names = "tx"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx>; + rockchip,grf = <&grf>; + status = "disabled"; + }; + iep_mmu: iommu@ff900800 { compatible = "rockchip,iommu"; reg = <0x0 0xff900800 0x0 0x40>;