diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c
index 61765899d61e..44d8453cce9d 100644
--- a/drivers/clk/rockchip/clk-rk3588.c
+++ b/drivers/clk/rockchip/clk-rk3588.c
@@ -14,6 +14,7 @@
 #include "clk.h"
 
 #define RK3588_GRF_SOC_STATUS0		0x600
+#define RK3588_PHYREF_ALT_GATE		0xc38
 #define RK3588_FRAC_MAX_PRATE		1500000000
 #define RK3588_DCLK_MAX_PRATE		400000000
 
@@ -2256,6 +2257,15 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
 			RK3588_PMU_CLKSEL_CON(14), 7, 2, MFLAGS, 0, 7, DFLAGS,
 			RK3588_PMU_CLKGATE_CON(4), 3, GFLAGS),
 
+	GATE(CLK_PHY0_REF_ALT_P, "clk_phy0_ref_alt_p", "ppll", 0,
+			RK3588_PHYREF_ALT_GATE, 0, GFLAGS),
+	GATE(CLK_PHY0_REF_ALT_M, "clk_phy0_ref_alt_m", "ppll", 0,
+			RK3588_PHYREF_ALT_GATE, 1, GFLAGS),
+	GATE(CLK_PHY1_REF_ALT_P, "clk_phy1_ref_alt_p", "ppll", 0,
+			RK3588_PHYREF_ALT_GATE, 2, GFLAGS),
+	GATE(CLK_PHY1_REF_ALT_M, "clk_phy1_ref_alt_m", "ppll", 0,
+			RK3588_PHYREF_ALT_GATE, 3, GFLAGS),
+
 	GATE(HCLK_SPDIFRX0, "hclk_spdifrx0", "hclk_vo1", 0,
 			RK3588_CLKGATE_CON(63), 12, GFLAGS),
 	GATE(HCLK_SPDIFRX1, "hclk_spdifrx1", "hclk_vo1", 0,
diff --git a/include/dt-bindings/clock/rk3588-cru.h b/include/dt-bindings/clock/rk3588-cru.h
index b9b6d2be52d0..682158717995 100644
--- a/include/dt-bindings/clock/rk3588-cru.h
+++ b/include/dt-bindings/clock/rk3588-cru.h
@@ -709,8 +709,12 @@
 #define CLK_CORE_LITCORE_PVTM		715
 #define CLK_AUX16M_0			716
 #define CLK_AUX16M_1			717
+#define CLK_PHY0_REF_ALT_P		718
+#define CLK_PHY0_REF_ALT_M		719
+#define CLK_PHY1_REF_ALT_P		720
+#define CLK_PHY1_REF_ALT_M		721
 
-#define CLK_NR_CLKS			(CLK_AUX16M_1 + 1)
+#define CLK_NR_CLKS			(CLK_PHY1_REF_ALT_M + 1)
 
 /********Name=SOFTRST_CON01,Offset=0xA04********/
 #define SRST_A_TOP_BIU			19