From 1fd942ea8bbe25dba2bea406572027666a74d58b Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Wed, 13 Jul 2022 08:47:16 +0800 Subject: [PATCH] clk: rockchip: rv1106: Add pll frac freq for audio This patch add pll frac freq around 1G for audio product, which will do fine tune pll for async clk situation, such as BT, UAC. Because we have no much more PLLs, and much more devices share the same PLL, so, we should setup around 1G to serve all the devices. PLLs in rv1106: APLL: CPU DPLL: DDR GPLL: DEVICES CPLL: DEVICES GPLL: 1188MHz CPLL: 1000MHz * PLLs support frac mode: GPLL DPLL So, the only way to use audio pll frac freq is to switch to use GPLL. and switch the role of GPLL and CPLL. GPLL: audio frac freq (~1G) CPLL: 1188MHz Signed-off-by: Sugar Zhang Change-Id: If26f464ac88cd21195db14084f8b4e9ffb457890 --- drivers/clk/rockchip/clk-rv1106.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/rockchip/clk-rv1106.c b/drivers/clk/rockchip/clk-rv1106.c index 9a9591ba2ecf..551c3396bc84 100644 --- a/drivers/clk/rockchip/clk-rv1106.c +++ b/drivers/clk/rockchip/clk-rv1106.c @@ -88,7 +88,9 @@ static struct rockchip_pll_rate_table rv1106_pll_rates[] = { RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0), RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0), + RK3036_PLL_RATE(993484800, 1, 124, 3, 1, 0, 3113851), RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0), + RK3036_PLL_RATE(983040000, 1, 81, 2, 1, 0, 15435038), RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0), RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0), RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),