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Merge commit '89603c13c51053968d363665de7ae1bdc5e93e73'

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* commit '89603c13c51053968d363665de7ae1bdc5e93e73':
  drm/rockchip: vop2: Remove background property for cluster window
  drm/rockchip: dw-dp: optimizing strategy to select bus format
  clk: rockchip: pll: use ULL for fvco/fout_max to compatible arm32
  ARM: dts: rockchip: add rv1126b-evb1-v11-dual-cam-csi0.dts

Change-Id: Icdbdaa191316749f75f80ad611866690ac6837de
This commit is contained in:
Tao Huang
2025-08-12 19:14:55 +08:00
parent 1f7b0743d6 89603c13c5
commit 20bdac2e67
5 changed files with 94 additions and 40 deletions
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1
arch/arm/boot/dts/Makefile
View File

@@ -1184,6 +1184,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rv1126b-evb1-v10-fastboot-spi-nor.dtb \
rv1126b-evb1-v10-spi-nor.dtb \
rv1126b-evb1-v11.dtb \
rv1126b-evb1-v11-dual-cam-csi0.dtb \
rv1126b-evb1-v11-dual-4k.dtb \
rv1126b-evb1-v11-fastboot-emmc.dtb \
rv1126b-evb1-v11-fastboot-emmc-projector.dtb \

6
arch/arm/boot/dts/rv1126b-evb1-v11-dual-cam-csi0.dts Normal file
View File

@@ -0,0 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*/
#include "arm64/rockchip/rv1126b-evb1-v11-dual-cam-csi0.dts"

33
drivers/clk/rockchip/clk-pll.c
View File

@@ -95,6 +95,13 @@ static inline void rockchip_boost_disable_low(struct rockchip_clk_pll *pll) {}
#define MIN_FOUTVCO_FREQ (800 * MHZ)
#define MAX_FOUTVCO_FREQ (2000 * MHZ)
/* CLK_PLL_TYPE_RK3588/3576_AUTO type ops */
#define RK3588_PLL_FVCO_MIN (2250ULL * MHZ)
#define RK3588_PLL_FVCO_MAX (4500ULL * MHZ)
#define RK3588_PLL_FOUT_MIN (37ULL * MHZ)
#define RK3588_PLL_FOUT_MAX (4500ULL * MHZ)
static struct rockchip_pll_rate_table auto_table;
int rockchip_pll_clk_adaptive_scaling(struct clk *clk, int sel)
@@ -335,18 +342,22 @@ rockchip_rk3066_pll_clk_set_by_auto(struct rockchip_clk_pll *pll,
static u32
rockchip_rk3588_pll_frac_get(u32 m, u32 p, u32 s, u64 fin_hz, u64 fvco)
{
u64 fref, fout, ffrac;
u32 k = 0;
u64 fref, fout, ffrac, k = 0;
fref = fin_hz / p;
fref = fin_hz;
do_div(fref, p);
ffrac = fvco - (m * fref);
fout = ffrac * 65536;
k = fout / fref;
k = fout;
do_div(k, fref);
if (k > 32767) {
fref = fin_hz / p;
fref = fin_hz;
do_div(fref, p);
ffrac = ((m + 1) * fref) - fvco;
fout = ffrac * 65536;
k = ((fout * 10 / fref) + 7) / 10;
fout = ffrac * 655360;
do_div(fout, fref);
k = fout + 7;
do_div(k, 10);
if (k > 32767)
k = 0;
else
@@ -359,7 +370,7 @@ static struct rockchip_pll_rate_table *
rockchip_rk3588_pll_frac_by_auto(unsigned long fin_hz, unsigned long fout_hz)
{
struct rockchip_pll_rate_table *rate_table = rk_pll_rate_table_get();
u64 fvco_min = 2250 * MHZ, fvco_max = 4500 * MHZ;
u64 fvco_min = RK3588_PLL_FVCO_MIN, fvco_max = RK3588_PLL_FVCO_MAX;
u32 p, m, s, k;
u64 fvco;
@@ -396,8 +407,8 @@ rockchip_rk3588_pll_clk_set_by_auto(struct rockchip_clk_pll *pll,
unsigned long fout_hz)
{
struct rockchip_pll_rate_table *rate_table = rk_pll_rate_table_get();
u64 fvco_min = 2250 * MHZ, fvco_max = 4500 * MHZ;
u64 fout_min = 37 * MHZ, fout_max = 4500 * MHZ;
u64 fvco_min = RK3588_PLL_FVCO_MIN, fvco_max = RK3588_PLL_FVCO_MAX;
u64 fout_min = RK3588_PLL_FOUT_MIN, fout_max = RK3588_PLL_FOUT_MAX;
u32 p, m, s;
u64 fvco;
@@ -1345,7 +1356,7 @@ static int rockchip_rk3588_pll_wait_lock(struct rockchip_clk_pll *pll)
static long rockchip_rk3588_pll_round_rate(struct clk_hw *hw,
unsigned long drate, unsigned long *prate)
{
if ((drate < 37 * MHZ) || (drate > 4500 * MHZ))
if ((drate < RK3588_PLL_FOUT_MIN) || (drate > RK3588_PLL_FOUT_MAX))
return -EINVAL;
else
return drate;

92
drivers/gpu/drm/rockchip/dw-dp.c
View File

@@ -1218,7 +1218,7 @@ static void dw_dp_atomic_connector_reset(struct drm_connector *connector)
__drm_atomic_helper_connector_reset(connector, &dp_state->state);
dp_state->bpc = 0;
dp_state->color_format = RK_IF_FORMAT_RGB;
dp_state->color_format = RK_IF_FORMAT_YCBCR_HQ;
}
static struct drm_connector_state *
@@ -1578,12 +1578,8 @@ static int dw_dp_connector_atomic_check(struct drm_connector *conn,
}
if ((dp_old_state->bpc != dp_new_state->bpc) ||
(dp_old_state->color_format != dp_new_state->color_format)) {
if ((dp_old_state->bpc == 0) && (dp_new_state->bpc == 0))
dev_info(dp->dev, "still auto set color mode\n");
else
crtc_state->mode_changed = true;
}
(dp_old_state->color_format != dp_new_state->color_format))
crtc_state->mode_changed = true;
if (dp->mst_mgr.cbs) {
ret = drm_dp_mst_root_conn_atomic_check(new_state, &dp->mst_mgr);
@@ -4613,7 +4609,9 @@ static u32 *dw_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
struct dw_dp_link *link = &dp->link;
struct drm_display_info *di = &conn_state->connector->display_info;
struct drm_display_mode mode = crtc_state->mode;
const struct dw_dp_output_format *fmt;
u32 *output_fmts;
u32 default_fmt = MEDIA_BUS_FMT_RGB888_1X24;
unsigned int i, j = 0;
dp->eotf_type = dw_dp_get_eotf(conn_state);
@@ -4644,7 +4642,7 @@ static u32 *dw_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
return NULL;
for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) {
const struct dw_dp_output_format *fmt = &possible_output_fmts[i];
fmt = &possible_output_fmts[i];
if (fmt->bpc > conn_state->max_bpc)
continue;
@@ -4667,35 +4665,73 @@ static u32 *dw_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
if (!dw_dp_bandwidth_ok(dp, &mode, fmt->bpp, link->lanes, link->max_rate))
continue;
if (dp_state->bpc != 0) {
if (fmt->bpc != dp_state->bpc)
continue;
if (dp_state->color_format != RK_IF_FORMAT_YCBCR_HQ &&
dp_state->color_format != RK_IF_FORMAT_YCBCR_LQ &&
(fmt->color_format != BIT(dp_state->color_format)))
continue;
}
if (dw_dp_is_hdr_eotf(dp->eotf_type) && fmt->bpc < 8)
continue;
output_fmts[j++] = fmt->bus_format;
}
*num_output_fmts = j;
if (*num_output_fmts == 0) {
/*
* If there are not support bus format found, choose the rgb 8bit as
* the default color format.
*/
output_fmts[0] = default_fmt;
*num_output_fmts = 1;
dev_warn(dp->dev, "Not support bus format found, use rgb format\n");
dev_info(dp->dev, "max bpc:%d, max fmt:%x, lanes:%d, rate:%d, eotf:%d\n",
conn_state->max_bpc, di->color_formats, link->lanes, link->max_rate,
dp->eotf_type);
}
if (dp_state->bpc != 0) {
/*
* If userspace select a bpc, match the bus format attach this
* bpc. If can't match, select a bpc by auto mode.
*/
j = 0;
for (i = 0; i < *num_output_fmts; i++) {
fmt = dw_dp_get_output_format(output_fmts[i]);
if (fmt->bpc != dp_state->bpc)
continue;
output_fmts[j++] = fmt->bus_format;
}
if (j)
*num_output_fmts = j;
else
dev_warn(dp->dev, "Not support bpc:%d, auto select bpc\n", dp_state->bpc);
}
if (dp_state->color_format <= RK_IF_FORMAT_YCBCR420) {
/*
* If userspace select a color format, match the bus format
* attach this color format. If can't match, select a color
* format by auto mode.
*/
j = 0;
for (i = 0; i < *num_output_fmts; i++) {
fmt = dw_dp_get_output_format(output_fmts[i]);
if (fmt->color_format != BIT(dp_state->color_format))
continue;
output_fmts[j++] = fmt->bus_format;
}
if (j)
*num_output_fmts = j;
else
dev_warn(dp->dev,
"Not support color format:%d, auto select color formatt\n",
dp_state->color_format);
}
if (dp_state->color_format == RK_IF_FORMAT_YCBCR_LQ)
dw_dp_swap_fmts(output_fmts, j);
*num_output_fmts = j;
if (*num_output_fmts == 0) {
dev_warn(dp->dev, "here is not satisfied the require bus format\n");
dev_info(dp->dev,
"max bpc:%d, max fmt:%x, lanes:%d, rate:%d, bpc:%d, fmt:%d, eotf:%d\n",
conn_state->max_bpc, di->color_formats, link->lanes, link->max_rate,
dp_state->bpc, dp_state->color_format, dp->eotf_type);
}
return output_fmts;
}

2
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -14739,7 +14739,7 @@ static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win, unsigned lon
BIT(DRM_COLOR_YCBCR_FULL_RANGE),
DRM_COLOR_YCBCR_BT601,
DRM_COLOR_YCBCR_LIMITED_RANGE);
if (win->regs->background.mask && !win->parent)
if (win->regs->background.mask && !win->parent && !vop2_cluster_window(win))
drm_object_attach_property(&win->base.base, private->bg_prop, 0);
drm_object_attach_property(&win->base.base, private->async_commit_prop, 0);